This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-118830, filed Jul. 26, 2022, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a display device and a manufacturing method thereof.
Recently, display devices to which an organic light emitting diode (OLED) is applied as a display element have been put into practical use. This display element comprises a lower electrode, an organic layer which covers the lower electrode, and an upper electrode which covers the organic layer.
In the above display device, various types of lines are provided in a surrounding area which surrounds a display area including pixels. There is demand for the improvement of the efficiency of the structure of the surrounding area including the various lines.
In general, according to one embodiment, a display device comprises a substrate, a lower electrode provided above the substrate in a display area including a pixel, a rib comprising an aperture overlapping the lower electrode, a partition provided on the rib in the display area, a thin film including an upper electrode which faces the lower electrode, and an organic layer which emits light based on a potential difference between the lower electrode and the upper electrode, a first sealing layer formed of an inorganic material and covering the thin film and the partition; and a line provided in a surrounding area between an end portion of the substrate and the display area. Each of the partition and the line comprises a conductive lower portion and an upper portion protruding from a side surface of the lower portion.
According to another aspect of the embodiment, a manufacturing method of a display device comprises forming a lower electrode above a substrate in a display area including a pixel, forming a rib comprising an aperture overlapping the lower electrode, forming a partition on the rib in the display area, the partition comprising a conductive lower portion and an upper portion protruding from a side surface of the lower portion, forming a line comprising the lower portion and the upper portion in a surrounding area between an end portion of the substrate and the display area, forming a thin film including an upper electrode which faces the lower electrode and an organic layer which emits light based on a potential difference between the lower electrode and the upper electrode, and forming a first sealing layer which covers the thin film and the partition by an inorganic material.
According to the above display device and the manufacturing method thereof, the efficiency of the structure of the surrounding area including the line can be improved.
Embodiments will be described with reference to the accompanying drawings.
The disclosure is merely an example, and proper changes in keeping with the spirit of the invention, which are easily conceivable by a person of ordinary skill in the art, come within the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, etc., of the respective parts are illustrated schematically in the drawings, rather than as an accurate representation of what is implemented. However, such schematic illustration is merely exemplary, and in no way restricts the interpretation of the invention. In addition, in the specification and drawings, structural elements which function in the same or a similar manner to those described in connection with preceding drawings are denoted by like reference numbers, detailed description thereof being omitted unless necessary.
In the drawings, in order to facilitate understanding, an X-axis, a Y-axis and a Z-axis orthogonal to each other are shown depending on the need. A direction parallel to the X-axis is referred to as a first direction X. A direction parallel to the Y-axis is referred to as a second direction Y. A direction parallel to the Z-axis is referred to as a third direction Z. The third direction Z is a normal direction relative to a plane including the first direction X and the second direction Y. When the plane including the first direction X and the second direction Y is viewed, the appearance is defined as plan view. The positive direction of the Z-axis is referred to as “on” or “above”. When terms indicating the positional relationships of two or more structural elements, such as “on”, “above” and “face”, are used, the target structural elements may be directly in contact with each other or may be spaced apart from each other as a gap or another structural element is interposed between them.
The display device of each embodiment is an organic electroluminescent display device comprising an organic light emitting diode (OLED) as a display element, and could be mounted on a television, a personal computer, a vehicle-mounted device, a tablet, a smartphone, a mobile phone, etc.
In the present embodiment, the substrate 10 is rectangular as seen in plan view. It should be noted that the shape of the substrate 10 in plan view is not limited to a rectangular shape and may be another shape such as a square shape, a circular shape or an elliptic shape.
The display area DA comprises a plurality of pixels PX arrayed in matrix in a first direction X and a second direction Y. Each pixel PX includes a plurality of subpixels SP. For example, each pixel PX includes a red subpixel SP1, a green subpixel SP2 and a blue subpixel SP3. Each pixel PX may include a subpixel SP which exhibits another color such as white in addition to subpixels SP1, SP2 and SP3 or instead of one of subpixels SP1, SP2 and SP3. It should be noted that each pixel PX may consist of two elements or four or more elements as subpixels and may include a color other than the red, green, blue and white shown as examples.
Each subpixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3 and a capacitor 4. The pixel switch 2 and the drive transistor 3 are, for example, switching elements consisting of thin-film transistors.
The gate electrode of the pixel switch 2 is connected to a scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to a signal line SL. The other one is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and the drain electrode is connected to a power line PL and the capacitor 4, and the other one is connected to the display element DE.
The display element DE is an organic light emitting diode (OLED) as a light emitting element. For example, subpixel SP1 comprises a display element DE which emits light in a red wavelength range. Subpixel SP2 comprises a display element DE which emits light in a green wavelength range. Subpixel SP3 comprises a display element DE which emits light in a blue wavelength range.
It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may comprise more thin-film transistors and capacitors.
When subpixels SP1, SP2 and SP3 are provided in line with this layout, in the display area DA, a column in which subpixels SP1 and SP2 are alternately provided in the second direction Y and a column in which a plurality of subpixels SP3 are repeatedly provided in the second direction Y are formed. These columns are alternately arranged in the first direction X.
It should be noted that the layout of subpixels SP1, SP2 and SP3 is not limited to the example of
A rib 5 and a partition 6 are provided in the display area DA. The rib 5 comprises pixel apertures AP1, AP2 and AP3 in subpixels SP1, SP2 and SP3, respectively. In the example of
The partition 6 is provided in the boundary between adjacent subpixels SP and overlaps the rib 5 as seen in plan view. The partition 6 comprises a plurality of first partitions 6x extending in the first direction X and a plurality of second partitions 6y extending in the second direction Y. The first partitions 6x are provided between the pixel apertures AP1 and AP2 which are adjacent to each other in the second direction Y and between two pixel apertures AP3 which are adjacent to each other in the second direction Y. Each second partition 6y is provided between the pixel apertures AP1 and AP3 which are adjacent to each other in the first direction X and between the pixel apertures AP2 and AP3 which are adjacent to each other in the first direction X.
In the example of
Subpixel SP1 comprises a lower electrode LE1, an upper electrode UE1 and an organic layer OR1 overlapping the pixel aperture AP1. Subpixel SP2 comprises a lower electrode LE2, an upper electrode UE2 and an organic layer OR2 overlapping the pixel aperture AP2. Subpixel SP3 comprises a lower electrode LE3, an upper electrode UE3 and an organic layer OR3 overlapping the pixel aperture AP3. In the example of
The lower electrode LE1, the upper electrode UE1 and the organic layer OR1 constitute the display element DE1 of subpixel SP1. The lower electrode LE2, the upper electrode UE2 and the organic layer OR2 constitute the display element DE2 of subpixel SP2. The lower electrode LE3, the upper electrode UE3 and the organic layer OR3 constitute the display element DE3 of subpixel SP3.
The lower electrode LE1 is connected to the pixel circuit 1 (see
In the example of
The circuit layer 11 is covered with a second organic insulating layer 12. The second organic insulating layer 12 functions as a planarization film which planarizes the irregularities formed by the circuit layer 11. Although not shown in the section of
The lower electrodes LE1, LE2 and LE3 are provided on the second organic insulating layer 12. The rib 5 is provided on the second organic insulating layer 12 and the lower electrodes LE1, LE2 and LE3. The end portions of the lower electrodes LE1, LE2 and LE3 are covered with the rib 5.
The partition 6 includes a conductive lower portion 61 provided on the rib 5 and an upper portion 62 provided on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. By this configuration, in
The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3.
In the example of
The organic layer OR1, the upper electrode UE1 and the cap layer CP1 are partly located on the upper portion 62. These portions are spaced apart from the other portions of the organic layer OR1, the upper electrode UE1 and the cap layer CP1. Similarly, the organic layer OR2, the upper electrode UE2 and the cap layer CP2 are partly located on the upper portion 62, and these portions are spaced apart from the other portions of the organic layer OR2, the upper electrode UE2 and the cap layer CP2. Further, the organic layer OR3, the upper electrode UE3 and the cap layer CP3 are partly located on the upper portion 62, and these portions are spaced apart from the other portions of the organic layer OR3, the upper electrode UE3 and the cap layer CP3.
In the following explanation, a stacked layer body including the organic layer OR1, the upper electrode UE1 and the cap layer CP1 may be called a thin film FL1. A stacked layer body including the organic layer OR2, the upper electrode UE2 and the cap layer CP2 may be called a thin film FL2. A stacked layer body including the organic layer OR3, the upper electrode UE3 and the cap layer CP3 may be called a thin film FL3.
First sealing layers SE11, SE12 and SE13 are provided in subpixels SP1, SP2 and SP3, respectively. The first sealing layer SE11 continuously covers the cap layer CP1 and the partition 6 which surrounds the subpixel SP1 side. The first sealing layer SE12 continuously covers the cap layer CP2 and the partition 6 which surrounds the subpixel SP2 side. The first sealing layer SE13 continuously covers the cap layer CP3 and the partition 6 which surrounds the subpixel SP3 side.
In the example of
The first sealing layers SE11, SE12 and SE13 are covered with a second sealing layer SE2. The second sealing layer SE2 is covered with a first resin layer RS1. The first resin layer RS1 is covered with a third sealing layer SE3. Further, the third sealing layer SE3 is covered with a second resin layer RS2. The second sealing layer SE2, the third sealing layer SE3, the first resin layer RS1 and the second resin layer RS2 are continuously provided at least in the entire display area DA and partly extend to the surrounding area SA.
The display device DSP may further comprise an optical element such as a polarizer provided on the second resin layer RS2 and cover glass. The optical element and the cover glass are attached to the second resin layer RS2 by, for example, a transparent adhesive material.
Each of the first organic insulating layer 34 and the second organic insulating layer 12 is formed of an organic insulating material. Each of the rib 5, the first sealing layers SE11, SE12 and SE13, the second sealing layer SE2 and the third sealing layer SE3 is formed of, for example, an inorganic material such as silicon nitride (SiNx). Each of the rib 5, the first sealing layers SE11, SE12 and SE13, the second sealing layer SE2 and the third sealing layer SE3 may be formed of silicon oxide (SiOx) or silicon oxynitride (SiON) or may be a stacked layer body consisting of at least two of a silicon nitride layer, a silicon oxide layer and a silicon oxynitride layer. Each of the first resin layer RS1 and the second resin layer RS2 is formed of a resinous material (organic insulating material) such as acrylic resin.
Each of the lower electrodes LE1, LE2 and LE3 comprises an intermediate layer formed of, for example, silver (Ag), and a pair of conductive oxide layers covering the upper and lower surfaces of the intermediate layer. Each conductive oxide layer may be formed of, for example, a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO).
Each of the upper electrodes UE1, UE2 and UE3 is formed of, for example, a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2 and LE3 correspond to anodes, and the upper electrodes UE1, UE2 and UE3 correspond to cathodes.
For example, each of the organic layers OR1, OR2 and OR3 comprises a multilayer structure consisting of a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer. Each of the organic layers OR1, OR2 and OR3 may comprise a tandem structure including a plurality of light emitting layers. It should be noted that, in the organic layers OR1, OR2 and OR3, at least one of the functional layers shown here may be omitted, or another functional layer may be added.
Each of the cap layers CP1, CP2 and CP3 is formed of, for example, a multilayer body consisting of a plurality of transparent thin films. As the thin films, the multilayer body may include a thin film formed of an inorganic material and a thin film formed of an organic material. These thin films have refractive indices different from each other. The materials of the thin films constituting the multilayer body are different from the materials of the upper electrodes UE1, UE2 and UE3 and are also different from the materials of the first sealing layers SE11, SE12 and SE13. It should be noted that at least one of the cap layers CP1, CP2 and CP3 may be omitted.
The lower portion 61 of the partition 6 is formed of, for example, aluminum (Al). The lower portion 61 may be formed of an aluminum alloy such as an aluminum-neodymium alloy (AlNd) or may comprise a multilayer structure consisting of an aluminum layer and an aluminum alloy layer. Further, the lower portion 61 may comprise a thin film formed of a metal material different from aluminum and an aluminum alloy under the aluminum layer or the aluminum alloy layer. This thin film can be formed of, for example, molybdenum (Mo).
For example, the upper portion 62 of the partition 6 comprises a multilayer structure consisting of a thin film formed of a metal material such as titanium (Ti) and a thin film formed of conductive oxide such as ITO. The upper portion 62 may comprise a single-layer structure of a metal material such as titanium. The upper portion 62 may comprise a single-layer structure of an inorganic material different from the first sealing layers SE11, SE12 and SE13.
Common voltage is applied to the partition 6. This common voltage is applied to each of the upper electrodes UE1, UE2 and UE3 which are in contact with the side surfaces of the lower portions 61. Pixel voltage is applied to the lower electrodes LE1, LE2 and LE3 through the pixel circuits 1 provided in subpixels SP1, SP2 and SP3, respectively.
When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light emitting layer of the organic layer OR1 emits light in a red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light emitting layer of the organic layer OR2 emits light in a green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light emitting layer of the organic layer OR3 emits light in a blue wavelength range.
The organic layer OR1, the upper electrode UE1 and the cap layer CP1 are formed by vapor deposition and are patterned together with the first sealing layer SE11. An end portion FL1a of the thin film FL1 including the organic layer OR1, the upper electrode UE1 and the cap layer CP1 is located on the upper portion 62. An end portion SE11a of the first sealing layer SE11 is also located on the upper portion 62. The end portion FL1a is not covered with the first sealing layer SE11.
Similarly, the organic layer OR3, the upper electrode UE3 and the cap layer CP3 are formed by vapor deposition and are patterned together with the first sealing layer SE13. An end portion FL3a of the thin film FL3 including the organic layer OR3, the upper electrode UE3 and the cap layer CP3 is located on the upper portion 62. An end portion SE13a of the first sealing layer SE13 is also located on the upper portion 62. The end portion FL3a is not covered with the first sealing layer SE13.
The end portion FL1a and the end portion FL3a are spaced apart from each other across an intervening gap. The end portion SE11a and the end portion SE13a are spaced apart from each other across an intervening gap. The second sealing layer SE2 is continuously provided in the entire display area DA and covers the end portions FL1a, FL3a, SE11a and SE13a. Further, the gap between the end portion FL1a and the end portion FL3a and the gap between the end portion SE11a and the end portion SE13a are filled with the second sealing layer SE2. The second sealing layer SE2 is in contact with the upper portion 62.
It should be noted that the configuration of the partition 6 between subpixels SP1 and SP2 and its vicinity and the configuration of the partition 6 between subpixels SP2 and SP3 and its vicinity are similar to the configuration of the example of
Now, this specification explains a structure which can be applied to the surrounding area SA.
The first gate drive circuit GD1 and the second gate drive circuit GD2 supply a scanning signal to the scanning line G shown in
The substrate 10 comprises end portions 10a, 10b, 10c and 10d. The end portions 10a and 10b extend parallel to the second direction Y. The end portions 10c and 10d extend parallel to the first direction X.
In the example of
Further, the display device DSP comprises a conductive layer CL (dotted portion) and a dam structure DS (hatched portion) in the surrounding area SA. In the example of
The conductive layer CL is connected to the partition 6 provided in the display area DA. The conductive layer CL overlaps the first gate drive circuit GD1, the second gate drive circuit GD2 and the selector circuit ST as seen in plan view.
It should be noted that the conductive layer CL may not necessarily have a shape surrounding the display area DA. For example, the conductive layer CL may not be provided between the display area DA and the end portion 10c or between the display area DA and the end portion 10d.
An organic layer ORs, an upper electrode UEs, a cap layer CPs and a first sealing layer SE1 are provided in the surrounding area SA. The organic layer ORs is formed of the same material by the same process as one of the organic layers OR1, OR2 and OR3. The upper electrode UEs is formed of the same material by the same process as one of the upper electrodes UE1, UE2 and UE3. The cap layer CPs is formed of the same material by the same process as one of the cap layers CP1, CP2 and CP3. The first sealing layer SE1 is formed of the same material by the same process as one of the sealing layers SE11, SE12 and SE13. For example, the organic layer ORs, the upper electrode UEs, the cap layer CPs and the first sealing layer SE1 are formed of the same material by the same process as the organic layer OR1, the upper electrode UE1, the cap layer CP1 and the first sealing layer SE11, respectively. In the following explanation, a stacked layer body including the organic layer ORs, the upper electrode UEs and the cap layer CPs may be called a thin film FL.
The thin film FL and the first sealing layer SE1 overlap the conductive layer CL as seen in plan view. However, the thin film FL or the first sealing layer SE1 does not overlap the dam structure DS as seen in plan view.
In
The feed line PW comprises a pair of pads PD located near the end portion 10c. These pads PD are electrically connected to the terminal portion T. Common voltage is applied to the feed line PW through the terminal portion T and each pad PD. Further, the common voltage of the feed line PW is applied to the relay line RL.
Lines LN1 and LN2 are further provided in the surrounding area SA. The lines LN1 and LN2 apply power supply voltage to each portion of the display device DSP such as the pixel circuit 1 shown in
The lines LN1 and LN2 are electrically connected to the terminal portion T. For example, as shown in
As shown in
For example, the distance between two adjacent protrusions of the protrusions R1, R2, R3 and R4 is greater than the width of each of the protrusions R1, R2, R3 and R4. For example, the width of each of the protrusions R1, R2, R3 and R4 is 15 to 25 μm. The distance between two adjacent protrusions of the protrusions R1, R2, R3 and R4 is 25 to 35 μm. The height of each of the protrusions R1, R2, R3 and R4 is 3 to 4 μm.
In the example of
Each of the inorganic insulating layers 31, 32 and 33 is formed of, for example, an inorganic material such as silicon nitride or silicon oxide. For example, each of the metal layers 41, 42 and 43 comprises a single-layer structure of a metal material such as molybdenum (Mo), tungsten (W), molybdenum tungsten alloy (MoW), aluminum (Al) or copper (Cu), or a multilayer structure of these metal materials.
The first gate drive circuit GD1 consists of the metal layers 41, 42 and 43 and a semiconductor layer. Similarly, the second gate drive circuit GD2 and selector circuit ST shown in
The protrusions R1, R2, R3 and R4 are provided on the inorganic insulating layer 33. The rib 5 is also provided in the surrounding area SA. In the example of
In the example of
The conductive layer CL covers the rib 5 in the surrounding area SA. The conductive layer CL includes a lower portion 61 and an upper portion 62 in a manner similar to that of the partition 6 shown in
As shown in
In the example of
The relay line RL is largely provided on the second organic insulating layer 12 and is covered with the rib 5. For example, the relay line RL is formed of the same material by the same process as the lower electrodes LE1, LE2 and LE3.
The relay line RL is connected to the feed line PW in a first contact portion CN1 and is connected to the conductive line CL in a second contact portion CN2. By this configuration, the common voltage of the feed line PW is applied to the conductive layer CL via the relay line RL. Further, the common voltage of the conductive layer CL is applied to the partition 6 of the display area DA and the upper electrodes UE1, UE2 and UE3.
The first contact portion CN1 is provided between the end portion CLa of the conductive layer CL and the protrusion R1. In the first contact portion CN1, the relay line RL is in contact with the second portion P2 of the feed line PW. For example, the first contact portion CN1 corresponds to the area in which the feed line PW overlaps the relay line RL in the plan view of
As shown in
As shown in
In
As shown in
As shown in
As shown in
Further, the second sealing layer SE2 covers part of the dam structure DS. Specifically, in the example of
An end portion RS1a of the first resin layer RS1 is located at a position closer to the end portion 10a of the substrate 10 than the end portion CLa of the conductive layer CL, the end portion FLa of the thin film FL and the end portion SEla of the first sealing layer SE1. In the example of
The third sealing layer SE3 entirely covers the first resin layer RS1. Further, the third sealing layer SE3 is in contact with, of the second sealing layer SE2, the portion which covers the dam structure DS. In this configuration, the end portion RS1a of the first resin layer RS1 is covered with the second sealing layer SE2 and the third sealing layer SE3. The position of an end portion SE3a of the third sealing layer SE3 is substantially coincident with that of the end portion SE2a of the second sealing layer SE2.
The second resin layer RS2 entirely covers the third sealing layer SE3. The position of an end portion RS2a of the second resin layer RS2 is substantially coincident with that of the end portion SE3a of the third sealing layer SE3. Thus, in the example of
As shown in
As shown in
In
The end portion CLa is covered with the second sealing layer SE2. The end portion FLa of the thin film FL and the end portion SEla of the first sealing layer SE1 above the conductive layer CL are also covered with the second sealing layer SE2.
In addition to the lower portion 61 and the upper portion 62, each of the lines LN1 and LN2 comprises a first metal layer M1. Further, the line LN2 comprises a second metal layer M2. The first metal layer M1 is formed of the metal layer 42 shown in
In each of the lines LN1 and LN2, the first metal layer M1 is provided on the inorganic insulating layer 32 and is partly covered with the inorganic insulating layer 33. The lower portion 61 of the line LN1 is in contact with the upper surface of the first metal layer M1 through an aperture formed in the inorganic insulating layer 33.
In the line LN2, the second metal layer M2 is in contact with the upper surface of the first metal layer M1 through an aperture formed in the inorganic insulating layer 33. Further, the lower portion 61 of the line LN2 is in contact with the upper surface of the second metal layer M2.
The third metal layer M3 of the line LN1 is provided on the inorganic insulating layer 31 and is partly covered with the inorganic insulating layers 32 and 33. The lower portion 61 of the line LN1 is in contact with the upper surface of the third metal layer M3 through an aperture formed in the inorganic insulating layers 32 and 33.
The third metal layer M3 of the line LN2 is provided on the inorganic insulating layer 31 and is partly covered with the inorganic insulating layer 32. The first metal layer M1 of the line LN2 is in contact with the upper surface of the third metal layer M3 through an aperture formed in the inorganic insulating layer 32. The second metal layer M2 of the line LN2 is in contact with the upper surface of the first metal layer M1 through an aperture formed in the inorganic insulating layer 33. The lower portion 61 of the line LN2 is in contact with the upper surface of the second metal layer M2.
In each of
In
The display device DSP may comprise only one of the lines LN1 and LN2. Alternatively, the display device DSP may comprise three or more lines comprising structures similar to those of the lines LN1 and LN2.
Now, this specification explains the manufacturing method of the display device DSP.
When the second organic insulating layer 12 and the first organic insulating layer 34 of the circuit layer 11 are formed, these organic insulating layers 12 and 34 are patterned, and the dam structure DS including the protrusions R1, R2, R3 and R4 is formed in the surrounding area SA as shown in
Subsequently, the lower electrodes LE1, LW2 and LE3 shown in
The lower and upper portions 61 and 62 of the lines LN1 and LN2 are formed together with the partition 6 and the conductive layer CL. When the lines LN1 and LN2 include the first, second and third metal layers M1, M2 and M3 shown in
Subsequently, the thin film FL1 including the organic layer OR1, the upper electrode UE1 and the cap layer CP1 and the first sealing layer SE11 are formed in subpixel SP1. The thin film FL2 including the organic layer OR2, the upper electrode UE2 and the cap layer CP2 and the first sealing layer SE12 are formed in subpixel SP2. The thin film FL3 including the organic layer OR3, the upper electrode UE3 and the cap layer CP3 and the first sealing layer SE13 are formed in subpixel SP3. Although the formation order of the thin films FL1, FL2 and FL3 is not particularly limited, for example, the thin film FL3 is formed firstly, and the thin film FL2 is formed secondly, and the thin film FL1 is formed lastly.
For example, the thin film FL (the organic layer ORs, the upper electrode UEs and the cap layer CPs) and first sealing layer SE1 shown in
The layers (the organic layer, upper electrode and cap layer) constituting the thin films FL, FL1, FL2 and FL3 are formed by vapor deposition. The first sealing layers SE1, SE11, SE12 and SE13 are formed by, for example, chemical vapor deposition (CVD).
After the formation of the thin film FL and the first sealing layer SE1, as shown in
After the formation of the second sealing layer SE2, as shown in
After the formation of the first resin layer RS1, as shown in
After the formation of the third sealing layer SE3, as shown in
Subsequently, as shown in
By this etching, the end portion SE2a of the second sealing layer SE2 and the end portion SE3a of the third sealing layer SE3 are aligned with the end portion RS2a of the second resin layer RS2. Before the etching, as shown in
In the present embodiment described above, the lines LN1 and LN2 each comprising the lower portion 61 and the upper portion 62 in a manner similar to that of the partition 6 provided in the display area DA are provided in the surrounding area SA. Thus, the efficiency of the structure of the surrounding area SA can be improved by using the layers of the partition 6 to form the lines LN1 and LN2.
Specifically, the lower portion 61 of the partition 6 is formed so as to be thick to divide the thin film layers FL1, FL2 and FL3. In the lines LN1 and LN2 using the thick lower portion 61 and the upper portion 62, the voltage is not easily decreased. If each of the lines is formed by using a layer which is thinner than the lower portion 61, such as the metal layer 41, 42 or 43, to prevent the decrease in voltage, the width of each line needs to be increased. To the contrary, when each of the lines LN1 and LN2 is formed using the thick lower portion 61 and the upper portion 62, the width of each of the lines LN1 and LN2 can be reduced even while preventing the decrease in voltage. As a result, the efficiency of the layout of the surrounding area SA can be improved, and the surrounding area SA can be made narrow and small.
When the lines LN1 and LN2 comprise the first metal layer M1, the second metal layer M2 and the third metal layer M3 like the examples of
As shown in
Further, the first resin layer RS1, the third sealing layer SE3 and the second resin layer RS2 are provided above the lines LN1 and LN2. By this structure, the lines LN1 and LN2 can be further satisfactorily protected.
As shown in
To the contrary, in the present embodiment, as the thin film FL does not extend to the dam structure DS, the second sealing layer SE2 is in contact with the dam structure DS. The second sealing layer SE2 is formed by, for example, CVD, and has an excellent adherence to the base compared to the thin film FL formed by vapor deposition. Thus, the adhesion strength of the peripheral portion of the display device DSP is improved. In the present embodiment, as the end portion FLa of the thin film FL is covered with the second sealing layer SE2, moisture penetration through the thin film FL can be prevented. In this way, according to the configuration of the display device DSP of the present embodiment, the reliability of the display device DSP can be improved.
As shown in
In the present embodiment, the third sealing layer SE3 is provided on the first resin layer RS1, and the end portion RS1a of the first resin layer RS1 is covered with the second sealing layer SE2 and the third sealing layer SE3. In this configuration, the first resin layer RS1 is covered with the second and third sealing layers SE2 and SE3 each of which is entirely formed of an inorganic material, thereby preventing moisture from entering the first resin layer RS1. Further, the third sealing layer SE3 is in contact with, of the second sealing layer SE2, the portion which covers the dam structure DS. As the third sealing layer SE3 is formed by, for example, CVD, the third sealing layer SE3 has an excellent adherence to the second sealing layer SE2. By this structure, the adhesion strength of the peripheral portion of the display device DSP is further improved.
Moreover, in the manufacturing method of the display device DSP of the present embodiment, the second sealing layer SE2 and the third sealing layer SE3 are partly removed by using the second resin layer RS2 as a mask. By this configuration, the number of manufacturing processes of the display device DSP can be reduced compared to a case where a mask for etching is formed by a resist.
In the configuration of the example shown in
The end portion RS1a may not be dammed up by the same protrusion over the entire surrounding area SA. This configuration is also applied to the end portion RS2a.
A second embodiment is explained. The structures which are not particularly referred to are the same as those of the first embodiment.
In the present embodiment, a dam structure DS comprises six protrusions R1, R2, R3, R4, R5 and R6. In the example of
In a manner similar to that of the first embodiment, each of the protrusions R1, R2, R3, R4, R5 and R6 includes a portion formed of a first organic insulating layer 34 and a portion formed of a second organic insulating layer 12. A feed line PW includes a first portion P1 and a second portion P2.
In the example of
The lines LN1 and LN2 are covered with a second sealing layer SE2. Further, a third resin layer RS3 is provided above the lines LN1 and LN2. The third resin layer RS3 is spaced apart from a first resin layer RS1 and is located between the protrusions R2 and R3. The space between the protrusions R2 and R3 is filled with the third resin layer RS3. For example, the third resin layer RS3 is formed of the same material as the first resin layer RS1.
The third resin layer RS3 is covered with a third sealing layer SE3. The third sealing layer SE3 is entirely covered with a second resin layer RS2. In the area between the first resin layer RS1 and the third resin layer RS3, the third sealing layer SE3 is in contact with the second sealing layer SE2. In addition, on the side closer to an end portion 10a of a substrate 10 than the third resin layer RS3, similarly, the third sealing layer SE3 is in contact with the second sealing layer SE2.
When the lines LN1 and LN2 are provided in the dam structure DS like the present embodiment, the efficiency of the layout of the surrounding area SA can be improved, and the surrounding area SA can be made narrower and smaller.
Further, as the lines LN1 and LN2 are covered with the third resin layer RS3 spaced apart from the first resin layer RS1, the resin material can be saved compared to a case where the first resin layer RS1 is extended to the upper side of the lines LN1 and LN2.
Moreover, when the second sealing layer SE2 is in contact with the third sealing layer SE3 in the area between the first resin layer RS1 and the third resin layer RS3, the moisture penetration path in the surrounding area SA can be satisfactorily blocked.
It should be noted that the line LN1 or LN2 may not be provided between the protrusions R2 and R3. The lines LN1 and LN2 may be provided at another position such as a position between the protrusions R1 and R2. Alternatively, the line LN1 may be provided between two adjacent protrusions, and the line LN2 may be provided between other two adjacent protrusions.
A third embodiment is explained. The structures which are not particularly referred to are the same as those of the first embodiment.
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In the example of
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All of the display devices that can be implemented by a person of ordinary skill in the art through arbitrary design changes to the display device described above as each embodiment of the present invention come within the scope of the present invention as long as they are in keeping with the spirit of the present invention.
Various modification examples which may be conceived by a person of ordinary skill in the art in the scope of the idea of the present invention will also fall within the scope of the invention. For example, even if a person of ordinary skill in the art arbitrarily modifies the above embodiments by adding or deleting a structural element or changing the design of a structural element, or adding or omitting a step or changing the condition of a step, all of the modifications fall within the scope of the present invention as long as they are in keeping with the spirit of the invention.
Further, other effects which may be obtained from each embodiment and are self-explanatory from the descriptions of the specification or can be arbitrarily conceived by a person of ordinary skill in the art are considered as the effects of the present invention as a matter of course.
Number | Date | Country | Kind |
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2022-118830 | Jul 2022 | JP | national |