BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram of a prior art LCD device.
FIG. 2 is a signal diagram illustrating driving signals received by the data lines and the gate lines of the LCD device in FIG. 1.
FIG. 3 is a functional diagram of a prior art LCD device.
FIG. 4 is a functional diagram of another prior art LCD device.
FIG. 5 is a functional diagram of an LCD device according to the present invention.
FIG. 6 is a functional diagram of an LCD device according to the first embodiment of the present invention.
FIG. 7 is a functional diagram of an LCD device according to the second embodiment of the present invention.
FIG. 8 is a signal diagram illustrating driving signals received by the data lines and the gate lines of the LCD device according to the present invention.
DETAILED DESCRIPTION
Reference is made to FIG. 5 for a functional diagram of an LCD device 40 according to the present invention. The LCD device 40 includes an LCD panel 42, a timing controller 43, a driving circuit 44, a storage unit 46 and a compensating circuit 48. The timing controller 43 is electrically coupled to the driving circuit 44 and can generate an input driving voltage VIN. The storage unit 46 can store a lookup table (LUT) related to each signal line of the LCD panel 42 and its corresponding compensating signal. The compensating circuit 48 is electrically coupled to the storage unit 46 and the driving circuit 44. When the LCD device 40 drives a signal line of the LCD panel 42, the compensating circuit 48 accesses a compensating signal VOS corresponding to the signal line from the LUT stored in the storage unit 46, and sends the compensating signal VOS to the driving circuit 44. Therefore, the driving circuit 44 can generate a corresponding driving voltage VOUT to be applied to the signal line based on the input driving voltage VIN and the compensating signal VOS.
Reference is made to FIG. 6 for a diagram of an LCD device 40 according to the first embodiment of the present invention. As shown, the driving circuit 44 is a source driver of the LCD device 40 and can transmit data signals corresponding to display images to the plurality of data lines of the display panel 42. For ease of explanation, only three data lines D1, D2 and D3 and corresponding connecting lines d1, d2 and d3 are illustrated in FIG. 6. The data lines D1, D2 and D3, respectively representing data lines disposed at the left side, the middle and the right side of the LCD panel 42, receive output driving voltages sent from the source driver 44 via the connecting lines d1, d2 and d3, respectively. The output driving voltages VOUT received by the data lines D1, D2 and D3 are respectively represented by data signals DATA1, DATA2 and DATA3. RD1, RD2 and RD3 respectively represent the resistances of signal transmission paths of the data signals DATA1, DATA2 and DATA3. Since the lengths of the connecting lines d1, d2 and d3 can vary due to different circuit layouts, and the data lines D1, D2 and D3 can have different resistances due to process variations, RD1, RD2 and RD3 can thus have distinct values. According to the preferred embodiment of the present invention, an LUT established based on the connecting line of each data line and its corresponding compensating signal is stored in the storage unit 46. When driving the data lines D1, D2 and D3, the compensating circuit 48 accesses compensating signals VOS—D1, VOS—D2 and VOS—D3 respectively related to the connecting lines d1, d2, d3 of the data lines D1, D2 and D3. The compensating signals VOS—D1, VOS—D2 and VOS—D3 are then sent to the driving circuit 44 (i.e., the source driver) for generating corresponding data signals DATA1, DATA2 and DATA3 to the data lines D1, D2 and D3, respectively. In the first embodiment of the present invention, the LCD device 40 adopts a fan-shaped layout in which the connecting line d2 disposed in the middle is the shortest, while the connecting lines disposed at corresponding locations at the left and right sides (such as the connecting line d1 and the connecting line d3) have the same length. Under these circumstances, the resistances of the signal transmission paths have the relationship RD1=RD3>RD2, the compensating signals of the data lines D1, D2 and D3 have the relationship VOS—D1=VOS—D3>VOS—D2, and the data signals received by the data lines D1, D2 and D3 have the relationship DATA1=DATA3>DATA2. Therefore, the resistance variations between different signal paths can be compensated by applying different data signals to the data lines D1, D2 and D3. The data lines can thus be driven with driving signals having identical slew rate, thereby improving the display quality of the LCD device.
Reference is made to FIG. 7 for a diagram of an LCD device 40 according to the second embodiment of the present invention. As shown, the driving circuit 44 is a gate driver of the LCD device 40 and can output scan signals corresponding to display images to the plurality of gate lines of the display panel 42. For ease of explanation, only three gate lines G1, G2 and G3 and corresponding connecting lines g1, g2 and g3 are illustrated in FIG. 7. The gate lines G1, G2 and G3, respectively representing gate lines disposed at the upper side, the middle and the lower side of the LCD panel 42, receive output driving voltages sent from the gate driver 44 via the connecting lines g1, g2 and g3, respectively. The output driving voltages VOUT received by the gate lines G1, G2 and G3 are respectively represented by scan signals SCAN1, SCAN2 and SCAN3. RG1, RG2 and RG3 respectively represent the resistances of signal transmission paths of the scan signals SCAN1, SCAN2 and SCAN3. Since the lengths of the connecting lines g1, g2 and g3 can vary due to different circuit layouts, and the gate lines G1, G2 and G3 can have different resistances due to process variations, RG1, RG2 and RG3 can thus have distinct values. In the present invention, an LUT established based on the connecting line of each gate line and its corresponding compensating signal is stored in the storage unit 46. When driving the gate lines G1, G2 and G3, the compensating circuit 48 accesses compensating signals VOS—G1, VOS—G2 and VOS—G3 respectively related to the connecting lines g1, g2, g3 of the gate lines G1, G2 and G3. The compensating signals VOS—G1, VOS—G2 and VOS—G3 are then sent to the driving circuit 44 (gate driver) for generating corresponding scan signals SCAN1, SCAN2 and SCAN3 to the gate lines G1, G2 and G3, respectively. In the second embodiment of the present invention, the LCD device 40 adopts a fan-shaped layout in which the connecting line g2 disposed in the middle is the shortest, while the connecting lines disposed at corresponding locations at the upper and lower sides (such as the connecting line g1 and the connecting line g3) have substantially the same length. Under these circumstances, the resistances of the signal transmission paths have the relationship RG1=RG3>RG2, the compensating signals of the gate lines G1, G2 and G3 have the relationship VOS—G1=VOS—G3>VOS—G2, and the scan signals received by the gate lines G1, G2 and G3 have the relationship SCAN1=SCAN3>SCAN2. Therefore, the resistance variations between different signal paths can be compensated by applying different scan signals to the gate lines G1, G2 and G3. The gate lines can thus be driven with driving signals having identical slew rate, thereby improving the display quality of the LCD device.
Reference is made to FIG. 8 for a signal diagram illustrating driving signals received at the data lines and the gate lines of the LCD device 40 according to the present invention. In FIG. 8, waveform A represents the actual driving voltages received at each data line and each gate line of the LCD device 40. Since different data signals and scan signals are outputted based on the resistances of each data line and each gate line, each data line and each gate line can thus be driven with driving signals having identical slew rate, thereby improving the display quality of the LCD device.
The compensating circuit 48 can include an application specific integrated circuit (ASIC) or a micro-controller unit (MCU), and the storage unit 46 can include a synchronous dynamic random access memory (SDRAM) or other types of memory. The storage unit 46 can provide compensating signals corresponding to different signal lines by accessing the stored LUT. The driving signals outputted to different signal lines can then be adjusted for compensating the resistance variations between different signal transmission paths. Each signal line can thus be driven with driving signals having identical slew rate, thereby improving the display quality of the LCD device.
In the above-mentioned embodiments, the data lines and the gate lines of an LCD device are used for illustrating the present invention. The outputs of the source driver and the gate driver can be adjusted based on an LUT, so that each data line and each gate line of the LCD device can be driven with driving signals having identical slew rate. However, the present invention is not limited to applications in LCD devices. The present invention can also be applied to display devices and driving methods so as to provide different loads with driving signals having identical slew rate by adjusting the outputs of a driving circuit based on an LUT.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Patent Application
20080062155
