Patent Application
20100053123
This application claims the benefit of priority based on Japanese Patent Application No. 2008-222453, filed on Aug. 29, 2008, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a display device and method for data transmission to a display panel driver, more particularly, to clock data recovery (CDR) from image data signal used for transmitting image data.
2. Description of Related Art
One requirement imposed on a display device is reduction in the number of signal lines connected to a display panel driver which drives a display panel (such as a liquid crystal display (LCD) panel). For example, a liquid crystal display device preferably has a reduced number of signal lines connected between an LCD controller and a data line driver. The reduction in the signal lines contributes the reduction in the cost, weight and size of the display device.
One approach for reducing the number of signal lines is clock data recovery from an image data signal used for transmitting image data. This approach eliminates the need for transmitting the image data signal and the clock signal through separate signal lines, effectively reducing the number of signal lines. Such technique is disclosed in Seiichi Ozawa et al. “A Wide Band CDR for Digital Video Data transmission”, A-SSCC 2005, 12-2, pp. 33-36 (2005), for example.
The control apparatus 101 is provided with an image data processing circuit 111, a transmitter 112, and a PLL (phase locked loop) circuit 113. The image data processing circuit 111 receives an external image signal 104 and generates image data to be transmitted to the driver 102 from the external image signal 104. The transmitter 111 encodes the image data, and thereby generates an image data signal 105. The transmitter 112 transmits the image data signal 105 to the driver 102 in synchronization with a clock signal received from the PLL circuit 113.
The image data signal 105 is generated in a format in which clock data recovery can be implemented within the driver 102. In other words, the image data signal 105 is superposed with a clock signal. Other control data used for controlling the driver 102 are also incorporated into the image data signal 105 in addition to the image data and the clock signal.
The driver 102 is responsive to the image data signal 105 received from the transmitter 112 for driving the display elements within the display panel 103. In detail, the driver 102 is provided with a receiver 121, a PLL circuit 122, and a display element driver circuit 123. The receiver 121 receives the image data signal 105 and decodes the received image data signal 105 to reproduce the image data. The reproduced image data are fed to the display element driver circuit 123. In
The reception of the image data signal 105 by the receiver 121 is synchronous with a recovered clock 125 fed from the PLL circuit 122. In detail, the receiver 121 forwards the received image data signal 105 to the PLL circuit 122 with the waveform unchanged. In
In addition, the receiver 121 generates a driving timing signal 127 indicative of the driving timings of the display elements within the display panel 103 in response to the control data incorporated within the image data signal 105. Furthermore, the receiver 121 generates a clock signal 128 synchronous with the recovered clock 125 and feeds the clock signal 128 to the display element driver circuit 123.
One issue of a display device thus constructed is that large noises are generated on the ground line and the power supply line by currents which flow when the drive of the display elements is started, and the noises causes undesired variations in the oscillation frequency and phase of the PLL circuit 122. Referring back to
In an aspect of the present invention, a display device is provided with a display panel; a driver driving the display panel; and a control apparatus transmitting image data and control data to the driver by using an image data signal. The driver includes a PLL circuit which performs clock data recovery from the image data signal and is configured to drive the display panel in response to the image data. The control data include: drive timing data indicating to start driving display elements within the display panel; and PLL control data which are specific data used to control a frequency and/or phase of the PLL circuit. The control apparatus is configured to transmit the PLL control data after transmission of the drive timing data.
The display device of the present invention, which is designed to transmit the PLL control data, allows quickly remedying the variations in the oscillation frequency and/or phase of the PLL circuit 122 caused by the noises generated by the currents which flows when the drive of the display elements is started.
The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.
The control apparatus 1 is provided with an image signal processing circuit 11, a PLL control data generator circuit 12, a switch 13, a transmitter 14, a PLL circuit 15 and a timing control circuit 16. The image data processing circuit 11 receives an external image signal 4 and generates from the external image signal 4 image data 41 to be transmitted to the driver 2.
The PLL control data generator circuit 12 generates PLL control data, which are data used for controlling the oscillation frequency and phase of a PLL circuit integrated within the driver 2. As described later, the PLL control data 42 are transmitted to the driver 2 and used to control the oscillation frequency and phase of the PLL circuit integrated within the driver 2. Details of the PLL control data 42 are described later.
The switch 13 is responsive to a switch control signal 33 received from the timing control circuit 16 for selectively forwarding to the transmitter 14 the image data 41 received from the image data processing circuit 11 and the PLL control data 42 received from the PLL control data generator circuit 12.
The transmitter 14 generates an image data signal 5 by encoding the image data 41 received from the image data processing circuit 11, and transmits the generated image data signal 5 to the driver 2. The transmission of the image data signal 5 to the driver 2 is synchronous with a clock signal 35 received from the PLL circuit 15. The image data signal 5 is generated by the transmitter 14 in a format which allows clock data recovery in the driver 2. In other words, a clock signal is incorporated within the image data signal 5. The incorporation of the clock signal is important for implementing clock data recovery in the driver 2.
The timing control circuit 16 is responsive to an external clock signal and synchronization signals fed thereto (such as a vertical sync signal VSYNC, a horizontal sync signal HSYNC, and a data enable signal DE) for controlling the control apparatus 1 and the driver 2. In detail, the timing control circuit 16 feeds timing control signals 31 and 32 to the image signal processing circuit 11 and PLL circuit 15, respectively, to control the operation timings thereof. In addition, the timing control circuit 16 feeds a switch timing control signal to the switch 13 to control the switching timings of the switch 13. Furthermore, the timing control circuit 16 feeds a transmitter control signal 34 to the transmitter 14 to thereby control the transmitter 14. Besides, the timing control circuit 16 controls the timings at which the driver 2 drives the display elements within the display panel 3. More specifically, the timing control circuit 16 generates drive timing data 43 indicative of the drive timings of the driver 2, and feeds the generated drive timing data 43 to the transmitter 14. The transmitter 14 transmits the drive timing data 43 to the driver 2 at proper timings under the control of the transmitter control signal 34.
As shown in
Referring back to
The receiver 21 receives the image data signal 5 in synchronization with a reproduced clock 25 fed from the PLL circuit 22. In detail, the receiver 21 forwards the received image data signal 5 to the PLL circuit 22 with the waveform thereof unchanged. In
In addition, the receiver 21 generates a drive timing signal 27 indicating the drive timings of the display elements within the display panel 3 in response to the control data 44 incorporated within the image data signal 5. Furthermore, the receiver 21 feeds a clock signal 28 from the reproduced clock 25 fed from the PLL circuit 25.
Next, a description is given of an exemplary operation of the display device in this embodiment.
One feature of the display device of this embodiment is that the PLL control data are fed to the driver 2 to thereby remedy the variations in the frequency and/or phase of the reproduced clock 25 caused by the noise generated by the currents in driving the display elements. The PLL control data 42 are specific data defined so that the waveform of the image data signal 5 (that is, the clock data recovery signal 24) is suitable for controlling the frequency and phase of the reproduced clock 25. It should be noted that the PLL control data 42 are not used for other purposes; the PLL control data 42 are dedicatedly used for controlling the frequency and phase of the reproduced clock 25. In the display device of this embodiment, the frequency and phase of the reproduced clock 25 are remedied as early as possible by performing clock data recovery by using the PLL control data 44 after the initiation of the drive of the display elements.
In this case, the image data signal 5, that is, the clock data recovery signal 24 has the maximum number of rising and falling edges in each transmission cycle period, when maximum frequency data 45 consisting of one or more data symbols in which bits “1” and “0” are alternately repeated are transmitted as the PLL control data 42. The use of the clock data recovery signal 24 with such waveform for clock data recovery allows quickly remedying the oscillation frequency of the PLL circuit 24 (that is the frequency of the recovered clock 25). In
When minimum frequency data 46 consisting of one or more data symbols in which the leading bit is “1” and the remaining bits are “0” are repeatedly transmitted as the PLL control data 42, on the other hand, the generation cycle period of the rising edges are coincident with the transmission cycle period and the positions of the rising edges are coincident with the start timings of the respective transmission cycle periods. The clock data recovery signal 24 with such waveform is suitable for stabilizing the phase of the recovered clock 25 and for facilitating the detection of the position of the leading bit of each data symbol, when the PLL circuit 22 is configured to control the frequency and phase of the recovered clock 25 so that the rising edge positions of the clock data recovery signal 24 are coincident with those of the recovered clock 25. In
Alternatively, minimum frequency data 46 consisting of one or more data symbols in which the leading bit is “0” and the remaining bits are “1” may be repeatedly transmitted as the PLL control data 42 so that the generation cycle period of the falling edges are coincident with the transmission cycle period and the positions of the falling edges are coincident with the start timings of the respective transmission cycle periods. The clock data recovery signal 24 with such waveform is suitable for stabilizing the phase of the recovered clock 25 and for facilitating the detection of the position of the leading bit of each data symbol, when the PLL circuit 22 is configured to control the frequency and phase of the recovered clock 25 so that the falling edge positions of the clock data recovery signal 24 are coincident with those of the recovered clock 25.
In the following, a detailed description is given of the operation of the display apparatus of this embodiment with reference to
The drive timing data 43 are used for the control apparatus 1 to control the drive timings of the display elements within the display panel 3. In this embodiment, in which the display element driver circuit 23 in the driver 2 are configured to start driving selected display elements in response to the activation of the drive timing signal 27, the control apparatus 1 controls the activation and deactivation of the drive timing signal 27 of the driver 2 by transmitting the drive timing data 43.
In detail, the control apparatus 1 transmits drive timing data 43 at the timing at which the drive timing signal 27 is to be activated in each blanking period, and transmits drive timing data 43 once again at the timing at which the drive timing signal 27 is to be deactivated. The receiver 21 activates the drive timing signal 27 when first detecting the drive timing data 43 in a certain blanking period BLNK. The value of the drive timing data 43 are define as a specific value. When a value of a data symbol transmitted to the receiver 21 by the image data signal 5 is the specific value, the receiver 21 judges that drive timing data 43 are fed thereto and activates the drive timing signal 27.
The display element driver circuit 23 starts driving display elements in the selected line within the display panel 3 in response to the image data 41 transmitted in the just previous active period ACT, when detecting the activation of the drive timing signal 27. In detail, the display element driver circuit 23 sets the display element drive signals 6 to the signal levels corresponding to the values of the image data 41 transmitted in the just previous active period ACT to thereby drive the display elements in the selected line. That is, the drive timing data 43 firstly transmitted and detected are used for the control apparatus 1 to indicate to start driving the display elements in the selected line. When then detecting drive timing data 43 again, the receiver 21 deactivates the drive timing signal 27.
As described above, the frequency and phase of the recovered clock 25 generated by the PLL circuit 22 may vary from the frequency and phase suitable for the reception of the image data signal 5 due to the noises generated on the ground line and power supply line by the currents flowing when the drive of the display elements is started. In order to avoid this problem, the control apparatus 1 transmits the PLL control data 42 after transmitting the drive timing data 43 indicating the activation of the drive timing signal 27. As described above, the PLL control data 42 are composed of specific data symbols suitable for clock data recovery, and the transmission of the PLL control data 42 just after the start of the drive of the display elements allows quickly recovering the frequency and phase of the recovered clock 25 generated by the PLL circuit 22 to the frequency and phase suitable for the reception of the image data signal 5.
It is significant that the PLL control data 42 are transmitted after the drive of the display elements is started and before the next image data 41 are then transmitted. This allows quickly recovering the frequency and phase of the recovered clock 25 to the frequency and phase suitable for the reception of the image data signal 5 before the reception of the next image data 41, improving the reliability of the reception of the image data 41. In the operation shown in
It is more preferable that the PLL control data 42 are transmitted after the drive of the display elements is started (that is, after the drive timing data 43 are first transmitted in the blanking period) and before valid data to be next received by the receiver 21 are transmitted. It should be noted that the valid data to be next received means control data actually used for the control of the driver 2 (other than the PLL data 42). In the example of
It is preferable that the PLL control data 42 are transmitted just after the drive of the display elements is started. In other words, it is preferable that, the PLL control data 42 are transmitted just after the drive timing data 43 are first transmitted in the blanking period. This allows recovering the frequency and phase of the recovered clock 25 to the frequency and phase suitable for the reception of the image data signal 5, more quickly.
The PLL control data 42 may be also transmitted before the start of the drive of the display elements, in addition to after the start of the drive of the display elements. This increases the length of the period during which the frequency and phase of the recovered clock 25 are effectively adjusted, improving the stability of the frequency and phase of the recovered clock 25. In the example shown in
The PLL control data 42 may include the maximum frequency data 45 and/or the minimum frequency data 46 shown in
It is preferable that, when the PLL control data 42 include both of the maximum frequency data 45 and the minimum frequency data 46, the maximum frequency data 45 are first transmitted, and the minimum frequency data 46 are then transmitted after the transmission of the maximum frequency data 45. This is because, when the oscillation frequency and phase of the PLL circuit 22 are once varied, it is desirable that the oscillation frequency is first remedied.
As thus described, the display device of this embodiment is configured to feed the PLL control data 42 to the driver 2 after the drive of the display elements is started, and to thereby quickly remedy variations of the frequency and/or phase of the recovered clock 25 caused by the noises generated by the currents flowing when the display elements are driven.
Although embodiments of the display device according to the present invention are specifically described above, the person skilled in the art would appreciate that the present invention is not limited to the above-described embodiments; the present invention may be implemented with various changes or modifications. It should be especially noted that the person skilled in the art would appreciate that the functions of the control apparatus 1 may be realized by hardware, software or a combination thereof, although the functions of the control apparatus 1 are described as being realized by hardware in the above-described embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-222453 | Aug 2008 | JP | national |
