Patent Application
20060139251
This invention relates to a display device which displays desired image information on a display panel comprising a plurality of display pixels which have current drive type optical elements, and more particularly regarding a display device and the method for driving the display device.
In recent years, personal computer and visual equipment monitors with an electronic screen called a Cathode Ray Tube (CRT) are fast becoming obsolete with the emergence of flat panel display devices, such as Liquid Crystal Display (LCD) flat panel monitors, at an astonishing rate. In particular, LCD's are commonplace because they offer some real advantages over other display technologies. They are thinner, lighter and draw much less power than conventional CRT's. LCD's are all around us everyday as they come in all shapes and sizes ranging from large screen televisions to small laptop computers and Personal Digital Assistants (PDA's), and even smaller cellular phones, digital cameras and many other electronic devices.
As the display device (display) of the next generation following in this revolutionary LCD technology, such as organic electroluminescent (EL) devices (hereinafter referred to as organic EL devices), inorganic electroluminescent elements (hereinafter referred to as inorganic EL elements), or Light Emitting Diodes (LEDs) and the like, full-scale application of the self-light type display (display device) comprising a display panel configured with self-light type light emitting elements called active matrix is evolving. Specifically, an active matrix is a type of LCD where each display element (each pixel) includes an active component such as a transistor to maintain its state between scans, and is also known as Thin-Film Transistor or TFT.
In such a self-light generation display, notably, a self-light type display which applies an active matrix drive method as compared with LCD's, the display speed response is fast with an unrestricted viewing angle. Also, higher luminosity, higher contrast, high definition display panels with much lower power consumption and the like are inevitable in the future. Since backlight is not needed in such an LCD display, it has very predominant characteristics that still more thinly shaped and lightweight models are possible.
This particular type of display panel, briefly, is comprises an array of display pixels which contain light emitting elements arranged near each of the intersecting points of the signal lines and in the direction of the scanning lines set in the line writing direction; a scanning driver applies sequentially scanning signals to predetermined timing and sets the display pixels of a specified line in a selection state; and a data driver generates write-in current (drive current) according to the display data which is supplied to each of the display pixels via signal lines and the above-mentioned write-in current is supplied to each of the display pixels. Each of the light emitting elements performs a light generation operation by predetermined luminosity gradation according to the display data, and the desired image information is displayed on the display panel. Afterwards, the configuration of a self-light generation type display will be described.
In the display drive operation of such a display, individual write-in currents are generated which have a current value according to the display data from the data driver to a plurality of display pixels and supplied simultaneously to the display pixels of a specified line selected by the scanning driver. This is in contrast to a current specification type drive method which repeats successively an operation to make each light emitting element emit light by predetermined luminosity gradation for each line of one screen and the display pixels of a specified line selected by a scanning driver. A Pulse Width Modulation (PWM) type drive method and the like which repeats successively for one screen an operation which supplies constant drive current of a constant value from the data driver, individual time width (signal width) according to the display data, and makes each of the light emitting elements emit light by predetermined luminosity gradation is commonly known.
However, there is a problem in the light emitting element type display mentioned above and the fact they do suffer from this drawback will be explained below.
Specifically, the data driver generates the write-in current according to the display data corresponding to each of the display pixels and the above-mentioned write-in current changes according to the display data in a conventional configuration and a conventional drive controlling method, which are supplied to the display pixels via each of the signal lines connected to an output terminal of the data driver. Thus, the current supplied to a circuit arrangement of transistors, latch circuits and the like which are individually formed in the data driver corresponding to each of the signal lines from a predetermined current source will also change. Here, generally a capacitative element (wiring capacity) exists in the signal wiring. Consequently, current supplied from the above-mentioned current source to the data driver, when supplied to the circuit arrangement via the signal wiring for current supply, the operation which alters the current supplied from the current source is equivalent to the charge or discharging of predetermined electric potential in parasitic capacitance which exists in the signal wiring. As a result, when the current supplied via the signal wiring is extremely low, the charge and discharge operation of the signal wiring for current supply takes time, and by the time the electric potential of the signal lines are stabilized, a relatively lengthy period will be required.
On the other hand, the operational period assigned to a current holding operation and the like in each of the signal lines becomes brief and attains high-speed operation essential in the data driver so the number of signal lines increases in proportion to the buildup of the number of display pixels of the display panel.
However, as mentioned above, the charge and discharge operation of the current supply in the signal wiring requires a certain amount of time, particularly; the current value of the write-in current supplied via the signal lines to the display panel in connection with miniaturization of the display panel or high definition (high resolution) and the like becomes low. It has disadvantages in the amount of time required in the charge and discharge operation of the signal wiring increases, rate controlling of the operating speed of data driver due to the rate of the charge and discharge operation has to be performed and achieving favorable image quality becomes difficult.
Additionally, display devices comprising a conventional data driver are configured so the write-in current is generated according to the display data by the data driver and supplied to the display pixels via each signal line. However, because the write-in current is an analog signal which changes according to the light generation state of the light emitting elements, the signal is easily influenced by external noise or signal degradation which produces a decline or change in the light generation luminosity in the light emitting elements. This problem makes it difficult to obtain a stable image display in suitable luminousity gradation.
The present invention has been made in view of the circumstances mentioned above. Accordingly, the present invention has an advantage to provide a display device which displays image information in response to a display signal on a display panel which has display pixels that have current drive type optical elements to enhance the operating speed with regard to generation of drive current in response to the display signals supplied to the optical elements, even in the case of reduced drive current during periods of low gradation; to reduce the amount of time required for generation of the drive current; and to improve the display response characteristics with the resultant effect to achieve favorable display image quality.
To achieve the foregoing advantage, the first display device in the present invention comprises a display panel with a plurality of signal lines and a plurality of scanning lines which intersect at right angles with each other, and a plurality of display pixels with optical elements arranged near the intersecting point of the plurality of signal lines and the plurality of scanning lines; a scanning driver circuit for sequentially applying a scanning signal to each of the scanning lines for setting the selective state of each line of each display pixel; and a signal driver circuit comprises a plurality of current generation circuits; the current generation circuits comprise at least a gradation current generation circuit and a drive current generation circuit; the gradation current generation circuit generates a plurality of gradation currents corresponding to each of the display signal bits based on constant, predetermined reference current, and the drive current generation circuit generates drive current from a plurality of gradation currents based on the value of the display signals which supplies the generated drive current to each signal line.
According to the display device of this invention, each of the current generation circuits in the above-mentioned signal drive circuit further comprise a signal holding circuit which takes in and holds the display signal; selects and integrates the gradation currents according each bit value of the display signal from the plurality of gradation currents based on a value of the signals held in the signal holding circuit and generates drive current.
According to the present invention, each of the current generation circuits generate a plurality of gradation currents which comprises a plurality of gradation current transistors, wherein the channel width of each the gradation current transistors is set at a different ratio with each other specified by 2n. Each control terminal thereof is connected in parallel and the gradation currents flow in the current path of each of the gradation current transistors. Furthermore, each of the gradation current generation circuits comprise a reference voltage generation circuit for generating reference voltage based on the reference current. The reference voltage generation circuits comprise reference current transistors for generating reference voltage to the control terminals, and the reference current is supplied to the current path. The reference current transistor control terminals are connected in common to the control terminals of a plurality of gradation current transistors. The reference current transistors and the plurality of gradation current transistors constitute a current mirror circuit.
In addition, according to the present invention, the signal driver circuit comprises a configuration in which the reference current is supplied to a plurality of gradation current generation circuits. The reference current is supplied via a reference current supply line. Each of the gradation generation circuit comprises a supply control switching circuit for controlling the supply state of the reference current from the reference current supply line to the proper gradation current generation circuit. The supply control switching circuit synchronizes to timing when taking in and holding the display signals for the signal holding means in each of the current generation circuits, and selectively performs switching control so that the reference current is supplied only to any one of the gradation current circuits of the plurality of gradation current generation circuits.
According to the present invention, each of the current generation circuits comprise a specified state setting circuit for setting the signal line to a specified voltage which makes the optical elements drive in a specified operating state when the display signal has a specified value. The display signal specified value is a value from which all of each of the gradation currents is non-selected from the display signals. The specified voltage is the voltage for setting the optical elements drive in a state of lowest gradation.
In addition, according to the present invention, each of the current generation circuits further comprises a reset circuit for applying predetermined reset voltage to the signal lines in advance of the timing which supplies the drive current to the signal lines. The reset voltage is at least the low potential voltage for discharging the electric charge stored up in the capacitative element attached to the optical elements in the display pixels and for initializing the optical elements. The reset voltage is applied when the display signal specified value presupposes non-selection of all of the plurality of gradation currents.
Moreover, according to the present invention, the optical elements in the display pixels comprise light emitting elements for accomplishing light generation operation by way of luminosity gradation according to the current value of the supply current. For example, the optical elements have light emitting elements consisting of organic EL devices. The display pixels comprise at least a pixel driver circuit which has a voltage holding circuit for holding the voltage component in response to the drive current supplied by the signal driver circuit; and a current supply circuit for supplying luminescent drive current to the light emitting elements based on the voltage component held in the voltage holding circuit and for making the light emitting elements emit light. The current supply circuit comprises transistors for use of luminescent drive for supplying luminescent current to the light emitting elements.
To achieve the foregoing advantage, the second display device in the present invention set to a display device for displaying image information according to display signals consisting of digital signals comprises: (1) a display panel equipped with a plurality of display pixels equipped with a current generation circuit; the current generation circuit comprises a plurality of signal lines and a plurality of scanning lines which intersect at right angles with each other; at least optical elements formed of the current drive type and arranged close to the intersecting point of a plurality of signal lines and a plurality of scanning lines; a gradation current generation circuit for generating a plurality of gradation currents corresponding to each of the display signal bits based on predetermined, constant reference current; a drive current generation circuit for generating drive current based on the value of the display signals which supplies the drive current to the optical elements; (2) a scanning driver circuit for sequentially applying a scanning signal for setting the selective state of each line of each scanning line; and (3) a signal driver circuit for supplying the display signals to a plurality of signal lines.
According to the present invention, the current generation circuit comprises a signal holding circuit which takes in the display signals and holds the signals based on the value of the display signals held in the holding circuit; selects and integrates the gradation currents according each bit value of the display signal from the plurality of gradation currents; and generates drive current.
According to the present invention, according to the present invention, each of gradation current generation circuits generate a plurality of gradation currents which comprise a plurality of gradation current transistors, wherein the channel width of each of the gradation current transistors are set at a different ratio with each other specified by 2n. Each control terminal thereof is connected in parallel and the gradation currents flow in the current path of each of the gradation current transistors. Also, each of the gradation current generation circuits comprise a reference voltage generation circuit for generating reference voltage based on the reference current. The reference voltage generation circuits comprise reference current transistors for generating reference voltage to the control terminals, and the reference current is supplied to the current path. The reference current transistor control terminals are connected in common to the control terminals of a plurality of gradation current transistors. The reference current transistors and the plurality of gradation current transistors constitute a current mirror circuit.
According to the present invention, each of the current generation circuits comprise a specified state setting circuit for setting the signal line to a specified voltage which makes the optical elements drive in a specified operating state when the display signal has a specified value. The display signal specified value is a value from which all of each of the gradation currents is non-selected from the display signals. The specified voltage is the voltage for setting the optical elements drive in a state of lowest gradation.
In addition, according to the present invention, each of the current generation circuits further comprises a reset circuit for applying predetermined reset voltage to the signal lines in advance of the timing, which supplies the drive current to the signal lines. The reset voltage is at least the low potential voltage for discharging the electric charge stored up in the capacitative element added in the optical elements in the display pixels and for initializing the optical elements. The reset voltage is applied when the display signal specified value presupposes non-selection of all of the plurality of gradation currents.
According to the present invention, the optical elements in the display pixels comprise light emitting elements for accomplishing light generation operation by way of luminosity gradation according to the current value of the supply current. For example, the optical elements have light emitting elements consisting of organic EL devices.
Additionally, according to the present invention, the reference current transistors, the gradation current transistors and the light generation drive at least any has a configuration of transistors comprising a body terminal electrode.
The above and further objects and novel features of the present invention will more fully appear from the following detailed description when the same is read in conjunction with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.
The present invention will hereinafter be described in detail with reference to the preferred embodiments shown in the accompanying drawings is applied to a display device and a drive method of the display device related to this invention.
First, the configuration of the data driver in the display device related to this invention or a current generation circuit is applied to a pixel driver circuit, and a controlling method of the current generation circuit will be explained with reference to the drawings.
1. Current Generation Circuit
Initially, the first embodiment of the current generation circuit in the display device related to this invention will be explained with reference to the drawings.
As shown in
Here, the current generator IRA is connected to a voltage contact +V connected to high supply voltage to flow reference current Iref in the direction of the current generation section 20A through a reference current supply line Ls.
Hereafter, the above-mentioned configuration will be explained in detail.
The signal latch section 10, as shown in
Here, each of the latch circuits LC0-LC3 which constitute the signal latch section 10, as shown in
Specifically, as illustrated in
At the CMOS 11 input contact point (clock input terminal of latch circuit LC) CK, the timing control signal (clock signal) CLK is supplied and an output contact point N11 (hereinafter references to “contact point” will be denoted as “contact” for convenience of explanation) is connected to the CMOS 12 input contact. Further, the above-mentioned timing control signal CLK is supplied to the CMOS 13 input terminal. The CMOS 13 output contact N12 connects the CMOS 12 output contact with the CMOS 14 input contact. The CMOS 14 output contact N13 is connected to the CMOS 15 and CMOS 16 input contacts. On one side, the signal levels of output contact N13 are output as inverse output signals from an inverted output terminal OT* (Denoted as “OT*” for convenience of explanation in the description and reference element in
In addition, CMOS 11, CMOS 14, CMOS 15 and CMOS 16 are constituted by each of the Pch transistors Tr1, Tr7, Tr9 and Tr11 whereby one end of the current path is connected to the high supply voltage Vdd, as well as each of the Nch transistors Tr2, Tr8, Tr10, and Tr12 whereby one end of the current path is connected to a low supply voltage Vgnd (voltage to ground). As for the CMOS 12 Pch transistor Tr3 and the CMOS 13 Nch transistor Tr6, one end of the current path is connected to a signal input terminal IN of the latch circuit LC and the above-mentioned digital signals d0-d3 are supplied. Further, CMOS 12 Nch transistor Tr4 and CMOS 13 Pch transistor Tr5, one end of the current path is connected to the above CMOS 16 output contact N14.
In the signal latch section 10 which has such a configuration, initially when the timing control signal CLK (a high-level pulse signal which has a predetermined signal width) is applied, CMOS 12 Pch transistor Tr3 side and CMOS 13 Nch transistor Tr6 perform an “ON” operation, the digital signals d0-d3 in suitable timing are taken in, and the signal levels of CMOS 12 and CMOS 13 common output contact N12 are specified by the digital signals d0-d3. Accordingly, based on the signal levels (signal levels of the digital signals d0-d3) of the output contact N12, each signal level (high-level/low-level) of the non-inverted output terminal OT and the inverted output terminal OT* supplied to CMOS 16 output contact N14 is determined.
Here, while CMOS 12 Pch transistor Tr3 side and CMOS 13 Nch transistor Tr6 performs an “OFF” operation after application of the above-mentioned timing control signal CLK (that is, the timing control signal CLK low-level state), the CMOS 12 Nch transistor Tr4 and CMOS 13 Pch transistor Tr5 perform an “ON” operation. The signal level of common output contact N12 of CMOS 12 AND CMOS 13 is specified, and the signal level (equivalent to the non-inverted output signals (signal levels of the non-inverted output terminal OT)) of CMOS 16 output contact N14 is taken in. Accordingly, the non-inverted output signals (signal levels of the non-inverted output terminal OT) and the inverted output signal (signal level of inverted output terminal OT*), which have signal levels equivalent to the time of application of the timing control signal CLK, continue and are output. The signal levels of this output signal are held in the same output state until the signal levels (signal levels of digital signals d0-d3) of the signals input terminal IN changes at the time of application of the next timing control signal CLK.
As shown in
Specifically, as shown in
The reference current transistor Tr21 generates a reference voltage Vref for the control terminal (gate terminal: contact Ng). When the reference current Iref is supplied to the current input contact INi the reference current Iref flows to the current path. Each of the gradation current transistors Tr22-Tr25, based on the reference voltage Vref supplied to each control terminal, gradation currents flow to each current path.
Additionally, a switching circuit 22A is applied to the current generation section 20A, which has a configuration whereby the current path is connected between a current output contact OUTi and each of the contacts Na, Nb, No and Nd to which a load is connected. The output signals d10-d13 output individually from each of the above-mentioned latch circuits LC0-LC3 to control terminals applied in parallel with a plurality (4 devices) of Nch transistors Tr26, Tr27, Tr28 and Tr29.
Here, in the current generation section 20A as applied to this embodiment, in particular the gradation currents Idsa-Idsd, which flow to each of the gradation current transistors Tr22-Tr25 and constitute the current mirror circuit 21A, are set to have a current value of an individually different predetermined ratio as opposed to the reference current Iref which flows to the reference current transistor Tr21. Specifically, the transistor size of each of the gradation current transistors Tr22-Tr25 is an individually different ratio. For example, in the case where the fixed channel length of each of the gradation current transistors Tr22-Tr25, the ratio (W2:W3:W4:W5) is formed so each channel width corresponds to 1:2:4:8.
Accordingly, if the channel width of the reference current transistor Tr21 is presupposed as W1, the current value of the gradation currents Idsa-Idsd which flow to each of the gradation current transistors Tr22-Tr25 will be individually set as Idsa=(W2/W1)×Iref, Idsb=(W3/W1)×Iref, Idsc=(W3/W1)×Iref, and Idsd=(W4/W1)×Iref. Thus, the current value between gradation currents can be set to a ratio specified as 2n by setting each one to the channel width of the gradation current transistors Tr22-Tr25 as 2n (n=0, 1, 2, 3, . . . ; 2n=1, 2, 4, 8, . . . ).
In this way, the current value from each of the gradation currents Idsa-Idsd is set up to generate the drive current ID comprising the current value 2n step. Further described later, random gradation currents are selected and integrated based on the plurality of digital signal d0-d3 bits (output signals d10-d13). Thus, as illustrated in
In the current generation section 20A which has such configuration, depending upon the signal levels of the output signals d10-d13 output from the above-mentioned latch circuits LC0-LC3, the particular transistor(s) of switching circuit 22A performs an “ON” operation (When comprised of any one or more of the transistors Tr26-Tr29 that perform an “ON” operation, other than cases of any of the transistors Tr26-Tr29 that perform an “OFF” operation.). The reference current Iref flows to the reference current transistor Tr21 to the gradation current transistors (any one or more of Tr22-Tr25) of the current mirror circuit 22A connected to the relevant transistor(s) that performed an “ON” operation. The gradation currents Idsa-Idsd have a current value of a predetermined ratio (2n gradation) and flow as mentioned above. At the current output contact OUTi, the drive current ID has a current value consisting of a composite value of these gradation currents. From the load side connected to the current output contact OUTi, the current output at contact OUTi flows to the low supply voltage Vgnd via the “ON” state transistor (whichever Tr26-Tr29)and the gradation current transistor (whichever Tr22-Tr25).
Therefore, in the current generation circuit ILA related to this embodiment, the drive current ID generated is converted to analog current which has a predetermined current value from the current generation section 20A, based on the timing specified by the timing control signal CLK in response to the plurality of digital signal d0-d3 bits input into signal latch section 10 and supplied to the load. (In this embodiment as mentioned above, the drive current is drawn in the direction of the current generation circuit from the load side.)
Thus, in the current generation circuit ILA related to this embodiment, reference current Iref is supplied to the current generation section 20A via the reference current supply line Ls from the current generator IRA, based on a plurality of digital signal d0-d3 bits (output signals d10-d13 of the signal latch section 10). Specified gradation currents are selected and integrated from a plurality of gradation currents Idsi-Idsl which have a current value of a predetermined ratio to the relevant reference current Iref. The drive current ID is constituted so the generated output has the desired current value. The current (reference current) supplied to the above-mentioned referenced current supply line Ls (signal wiring) is constant, since a current supply voltage fluctuation following a change is not produced. For example, even if negligible drive current is generated, there is no delay in the operation of the current generation circuit resulting from the electrical charge or discharge of present parasitic capacitance; thereby, the operating speed of the current generation circuit can be raised and the load can be driven at a faster speed.
Furthermore, as described later in detail, the above-mentioned plurality of digital signal bits apply the display data on the display device for the purpose of displaying desired image information. In this case, the drive current generated and output by the current generation circuit corresponds to the write-in current supplied to each display pixel which forms the display panel or supplied to the light emitting element of each of the display pixels.
Next, the second embodiment of the current generation circuit related to this invention will be explained with reference to the drawings.
Here, concerning any configuration equivalent in the embodiment mentioned above, the same or equivalent nomenclature is appended and the explanation is simplified or omitted from the description.
In the embodiment mentioned above, although the case illustrated is configured (described as “current sinking method” for convenience) from the load side connected to the current generation circuit ILA so the drive current ID is drawn in the direction of current generation circuit ILA, this embodiment has a configuration (described as “current application method” for convenience) which flows (pours) the drive current ID in the direction of the load from the current generation circuit ILA side.
Specifically, as shown in
The signal latch section 10 has a configuration in which the latch circuits LC0-LC3 are individually formed corresponding to a plurality of the digital signals d0-d3. The inverted output signals d10*-d13* (Denoted in the description for convenience as d10*-d13* in reference to the same element in
As shown in
Specifically, the configuration of current mirror circuit 21B and the switching circuit 22B consist of the Pch transistors Tr31 -Tr39. A reference current transistor Tr31 is connected in between current input contact INi and the voltage contact +V, along with the control terminal connected to the voltage contact +V via the current input contact INi and contact Nh together with the capacitor C1. In addition, the gradation current transistors Tr32-Tr35 are individually connected in between the contacts Ni, Nj, Nk and Nl and the voltage contact +V, along with the control terminals connected in common to the contact Nh. Also, the transistors Tr36-Tr39 for switching are configured so each one is connected in between the above-mentioned contacts Ni, NJ, Nk and Nl and the current output contact OUTi, along with the output signals d10*-d13* output from the latch circuits LC0-LC3 each applied to the control terminals in parallel.
Here also set in the embodiment configuration of current mirror circuit 21B, the size (Namely, the channel width at the time of setting the fixed channel length.) of each of the gradation current transistors Tr32-Tr35 is formed to correspond to a predetermined ratio based on the reference current transistor Tr31. The gradation currents Idsi-Idsl which flow in each current path are set up so the current value of each one is a different predetermined ratio as opposed to the reference current Iref.
Therefore, also in the current generation circuit 20B related to this embodiment, in response to the signal levels of output signals d10*-d13* output from the signal latch section 10 (the latch circuits LC0-LC3), the particular transistor(s) Tr36-Tr39 of the switching circuit 22B perform an “ON” operation. Accordingly, the gradation currents Idsi-Idsl, which have a current value twice the predetermined ratio of the reference current Iref, flows via the gradation current transistors Tr32-Tr35. These composite currents are supplied to a load connected to the current output contact OUTi as the drive current ID via the current output contact OUTi. (In this embodiment, the drive current flows in the direction of the load from the current generation circuit side).
Also, the current generation circuit ILB of this embodiment, resembling the case of the first embodiment, has a configuration which selects and integrates particular gradation currents from the plurality of gradation currents Idsi-Idsl to generate and output the drive current ID having the desired current value. Since the current (reference current) supplied to the above-mentioned reference current supply line LS (signal wiring) is constant, even if negligible drive current is generated, the operating speed of the current generation circuit can be raised and the load can be driven at a faster speed.
Next, the third embodiment of the current generation circuit related to this invention will be explained with reference to the drawings.
Here, concerning any configuration equivalent in the embodiments mentioned above, the same or equivalent nomenclature is appended and the explanation is simplified or omitted from the description.
As shown in
Here, the current generator IRA connected to the voltage contact +V connected to the high supply voltage flows (pours) the reference current Iref in the direction of the current generation section 20A via the reference current supply line Ls.
The specified state setting section 30A, shown in
Here, the NOR circuit 31 as shown in
In the specified state setting section 30A which has such as configuration, the NOR circuit 31 judges whether or not all of the signal levels of the output signals d10-d13 output from the above-mentioned latch circuits LC0-LC3 are in the specified state set to zero (0). Only when in this specified state, the specified voltage application transistor TN32 performs an “ON” operation, and the specified voltage (Vbk, Vr) is applied to the load current supply line CL.
Therefore, according to the current generation circuit ISA of this embodiment, along with the same effect as the first embodiment, the current generation circuit performs drive control of the load from a plurality of digital signal bits. When all of the digital signal bits (output signals d10-d13) are set to zero (0), by isolating the current output in the current generation section 20A, the signal levels of the current supply source line CL will be in a high impedance state. This problem which makes the operating state of the load unstable can be solved. Furthermore, with all of the digital signal bits (output signals d10-d13) set to zero, by setting the signal levels of the load current supply line CL as a specified voltage the load can be driven by a specified operating state. These functions are suitable for eliminating abnormalities in the display, or application of the reset voltage when applied to the display device data driver of this current generation circuit (described later in detail).
Next, the fourth embodiment of the current generation circuit related to this invention will be explained with reference to the drawings.
Here, concerning any configuration equivalent in the embodiments mentioned above, the same or equivalent nomenclature is appended and the explanation is simplified or omitted from the description.
Although the case illustrated in the third embodiment mentioned above is configured (described as “current sinking method” for convenience) so the load drive current ID is drawn in the direction of the current generation circuit ISA from the load side connected to the current generation circuit ISA, the fourth embodiment has a configuration (described as “current application method” for convenience) which flows (pours) the load drive current ID in the direction of the load from the current generation circuit ISB side.
Specifically, as shown in
Here, the current generator IRB is connected to the low supply voltage Vgnd so reference current Iref flows in the current generator IRB direction from the current generation section 20B side via the reference current supply line Ls.
The specified state setting section 30B, as shown in
Here, OR circuit 33, for example as shown in
Specifically, as shown in
Also, a NAND circuit 33c illustrated, as shown in
Also, in the specified state setting section 30B which has such a configuration, the OR circuit 33 judges whether or not all of the signal output signals d10-d13 output from the above-mentioned latch circuits LC0-LC3 are in the specified state set to zero (0). The specified voltage application transistor TP34 performs an “ON” operation only in this specified state, and the specified voltage Vbk is applied to the load via the current supply source line CL.
Therefore, also in the current generation circuit ISB of this embodiment, the same effect as the case of the third embodiment can be acquired in the current application method.
Next, the fifth embodiment of the current generation circuit related to this invention will be explained with reference to the drawings.
As described later, in the case of applying the current generation circuits in accordance with the present invention to the write-in current generation circuit clusters of the display device data driver, although configured so the plurality of current generation circuits operate in parallel and configured so the predetermined reference current is supplied to each of the plurality of current generation circuits, when the reference current is supplied in common to the plurality of current generation circuits from one constant current power source, the value of the current supplied to each current generation circuit becomes the current value into which the reference current supplied from the constant current power source was divided according to the number of current generation circuits. At this time, the current supplied to each current generation circuit, where the component characteristics (channel resistance and the like) of the reference current transistors of the current generation section of each current generation circuit are almost identical to each other, the current supplied to each current generation circuit as reference current becomes almost uniform current (constant current) as it is divided almost equally. Therefore, equal drive current can be generated.
However, if a variation occurs in one another of the component characteristics of each of the current generation circuit reference current transistors (e.g., manufacturing differences or environmental surroundings, a change in the physical properties such as aging with time and the like), because the current supplied to each current generation circuit becomes that in which a variation divided unequally has reference current, the drive current generated will also produce variation.
Then, in addition to the configuration in each of the above-mentioned embodiment, this embodiment comprises a configuration which is intermittent in the supply of reference current in the current generation circuit from a current generator. Accordingly, applying to the data driver of the display device which describes the current generation circuit related to this invention later, when operating simultaneously in parallel with a plurality of current generation circuits, along with supplying selectively to each of the current generation circuits reference current from a current generator, that is to say, it can be constituted so reference current can be supplied to the current generation circuits one at a time. Therefore, each current generation circuit generates drive current using the same reference current and drive current variations can be controlled. When applied to the display device, it can control variations in the luminosity gradation of each display pixel and can acquire excellent display image quality.
Here, concerning any configuration equivalent in the embodiments mentioned above, the same or equivalent nomenclature is appended and the explanation is simplified or omitted from the description.
In particular, the current mirror circuit 21C is configured with Pch transistors Tr61-Tr65 and switching circuits TS1 and TS2. A reference current transistor Tr61 is connected in between contact Nm and the voltage contact +V, along with the control terminal connected to contact Np. In addition, gradation current transistors Tr62-Tr65 are individually connected in between the voltage contact +V and contacts Nq, Nr, Ns and Nt, along with the control terminals connected in common to contact Np. A capacitor C1 is connected in between the above-mentioned contact Np and the voltage contact +V. Further, the switching circuit TS1 is connected in between the current input INi and the above-mentioned contact Nm, and the switching circuit TS2 is connected in between the above-mentioned contact Nm and contact Np.
Resembling the current generation section 20B mentioned above, the switching circuit 22C is configured with Pch transistors Tr66-Tr69 applied in parallel connected in between each of the above-mentioned contacts Nq, Nr, Ns and Nt and the current output contact OUTi, along with the output signals d10*-d13* output to each control terminal from a plurality of latch circuits.
Thus, also in this embodiment, the current mirror 21C is formed so the transistor size of each gradation current transistor Tr62-Tr65 consists of a predetermined ratio based on the reference current transistor Tr61, and the gradation current Idsq-Idst which flows to each current path is set up so the current value of each one is a different predetermined ratio as opposed to the current (reference current Iref) which flows to the reference current transistor Tr61. Accordingly, in response to the signal levels of output signals d10*-d13*, the specified transistors Tr66-Tr69 of the switching circuit section 22C perform an “ON” operation. The gradation currents Idsq, Idsr, Idss, Idst which have a current value twice the predetermined ratio of the reference current Iref flows via the gradation current transistors Tr62-Tr65. Random gradation currents are selected and integrated from a plurality of the gradation currents Idsq, Idsr, Idss and Idst, the drive current ID is generated and output from the current output contact OUTi.
Further, the current mirror circuit 21C related to this embodiment is configured with the switching circuit TS1 formed between the current input contact INi and contact Nm, and the switching circuit TS2 formed between contact Nm and contact Np. The switching circuits TS1 and TS2 perform setting control to correctly execute the “ON” and “OFF” operations. Thus, the switching circuits TS1 and TS2 are configured to supply or cutoff the current path of the reference current Iref of reference current transistor Tr61, as well as perform switching control of the connection or cutoff between the current path of the reference current transistor Tr61 and the control terminal.
Here, for example as shown in
Additionally, when applied to the data driver which describes a plurality of current generation circuits comprising a current generation section 20C later in this embodiment, generation of the drive current in each current generation circuit is addressed. By performing “ON” and “OFF” control selectively of switching circuits TS1 and TS2 formed in each of current generation circuits; perform an “ON” operation only of the switching circuits TS1 and TS2 formed in any one current generation circuit; and perform and “OFF” operation of the switching circuits TS1 and TS2 formed in the other current generation circuits, it controls all at one time so the reference current Iref is supplied only to the relevant current generation circuit. Accordingly, as reference current Iref is supplied to the reference current transistors of only one current generation circuit of the plurality of current generation circuits, drive current is generated based on the present reference current Iref.
Furthermore, the current generation circuit shown in this embodiment and a configuration which can realize the equivalent functions, for example, the current generation section 20D (current mirror circuit 21D) which has the circuit arrangement shown in
Thus, the current mirror circuit 21D, along with the current mirror circuit 21C shown in
In addition, in this embodiment although the circuit arrangement attached the switching circuits TS1-TS2 or TS3-TS4 to a configuration comprises the current generation section 20B shown in
2. Display Device
A current generation circuit which has such a composition and functions mentioned above is applicable as a favorable pixel driver circuit which forms the drive control device of a display device or the display pixels of a display panel. A display device comprising such a current generation circuit related to the present invention will be described in detail below.
First, an embodiment in the case of applying a current generation circuit related to this invention to the drive control device of a display device will be explained with reference to the drawings.
Here, explanation will be made to the configuration comprising display pixels corresponding to an active-matrix display panel. Also, in this embodiment, explanation will be made to the adopted configuration of the current sinking method.
As shown in
Hereinafter, explanation of each of the above-mentioned construction will be explained in detail.
<<Display Panel>>
Specifically, the display panel 110A as shown
Here, the pixel driver circuits DCx, briefly, have the functions to take in write-in current Ipix in response to the display data selection state and hold as the voltage level, which is controlled according to the selection/non-selection state of each of the display pixels EM in response to the scanning signal Vsel; to supply light generation drive current to the organic electroluminescent(EL)devices OEL (hereinafter referred to as organic EL devices) (optical elements)according to the voltage level held (above-mentioned) in the non-selection state; and to maintain operation to emit light by predetermined luminosity gradation. In addition, explanation of a possible example circuit arrangement applicable to the pixel driver circuits DCx will be described later.
<<Scanning Driver>>
The scanning driver 120A sets the selection state for each line of the display pixel clusters by sequentially applying the scanning signal Vsel to each scanning lines SL at predetermined timing, based on the scanning control signal supplied from the system controller 150; supplies the write-in current Ipix based on the display data to each of the signal lines DL by the data driver 130A; and controls the write of predetermined write-in current in each display pixel.
Specifically, the scanning driver 120A shown in
<<Data Driver>>
The data driver 130A takes in and holds the display data which comprises a plurality of digital signal bits supplied from the display signal generation circuit 160, based on the data control signals supplied from the system controller 150; generates a write-in current Ipix which has a current value according to the relevant display data; and controls the write-in current supply to each of the signal lines DL simultaneously and parallel. Thus, in the data driver 130A related to this embodiment, the current generation circuit of each embodiment mentioned above is favorably compatible. A detailed circuit arrangement example of the data driver 130A and its drive control operation will be described later.
<<Voltage Driver>>
The voltage driver 140 draws in the predetermined write-in current Ipix based on the display data and synchronizing with the timing sets the selection state for each line of every display pixel cluster from the scanning driver 120 based on a voltage control signal supplied from the system controller 150, by applying the power supply voltage Vso selection level (For instance, a low-level set less than the ground supply (voltage to ground)) to the voltage lines VL, for example, in the direction of the data driver 130A via the display pixels EM (pixel driver circuits DCx) from the voltage lines VL. Meanwhile, the voltage driver 140 controls the flow of the light generation drive current equivalent to the above-mentioned write-in current Ipix in the direction of the organic EL devices OEL (optical elements) via the display pixels EM (pixel driver circuits DCx) from the voltage lines VL, synchronizing with the timing sets of the non-selection state for each line of every display pixel cluster from the scanning driver 120 by applying the power supply voltage Vs. non-selection level (For example, a high-level) to the voltage lines VL.
Specifically, the voltage driver 140 shown in
<<System Controller>>
The system controller 150 receives each of at least the scanning driver 120A, the data driver 130A and the voltage driver 140 according to the timing signal supplied from the display signal generation circuit 160 described later. By generating and outputting the scanning control signal (the scanning start signal SSTR, the scanning clock signal SCLK and the like which were mentioned above), the data control signals and a voltage control signal (the power start signal VSTR, the voltage clock signal VCLK and the like which were mentioned above), each driver operates to predetermined timing. The power supply voltage Vs., the scanning signal Vsel and the write-in current Ipix are made to output to the display panel 110A; perform continuously predetermined drive control operations in the pixel driver circuits DCx; and perform control to the display panel 110A made to display predetermined image information based on the video signal.
The system controller 150 generates and outputs the scanning control signal, the data control signals (the scanning start signal SSTR, the scanning clock signal SCLK; the sampling start signal STR and the shift clock signal SFC and the like; the voltage control signal(the power start signal VSTR and the voltage clock signal VCLK and the like) to each of at least the scanning driver 120A, the data driver 130A and the voltage driver 140 according to the timing signal supplied from the display signal generation circuit 160 described later. By generating and outputting the above mentioned signals, the system controller 150 performs each driver to operate at predetermined timing; to output the power supply voltage Vsc, the scanning signal Vsel and the write-in current Ipix to the display panel 110A; to perform continuously predetermined drive control operations in the pixel driver circuits DCx; and to perform control to the display panel 110A made to display predetermined image information based on the video signal.
<<Display Signal Generation Circuit>>
The display signal generation circuit 160, for example, extracts the luminosity gradation signal component from the video signal supplied from outside the display device 100A; supplies a luminosity gradation signal component for every one line period (horizontal scanning period)of the display data panel 110A; and supplies the display data and the data driver 130A, which is made up from a plurality of digital signal bits. Here, when the above-mentioned video signal contains the timing signal component which specifies the display timing of image information such as a television broadcasting signal (composite video signal), the display signal generation circuit 160 has a function which extracts the timing signal component supplied to the system controller 150 and another function which extracts the above-mentioned luminosity gradation signal component. In this case, the above-mentioned controller 150 generates the above-mentioned scanning control signal, the data control signal and the voltage control signal supplied to the scanning driver 120, the data driver 130A and the voltage driver 140 based on the timing signal supplied from the display signal generation circuit 160.
In addition, although in this embodiment, as shown in
Furthermore, the configuration of the display device as shown in
<<Pixel Driver Circuit>>
Subsequently an example of the configuration of the pixel driver circuit as applied to each display pixel of the display panel mentioned above will be described.
In addition, the pixel driver circuit shown here only represents an example applicable to the display device related to this invention. Needless to say, there can be other circuit arrangements having an equivalent operational function.
As shown in
Additionally, the organic EL devices OEL described earlier for light generation luminosity are controlled by the light generation drive current supplied from the pixel driver circuits DCx. The organic EL devices OEL anode terminal is connected to contact Nxb of the above-mentioned pixel driver circuit, and the cathode terminal is individually connected to the low supply voltage Vgnd (voltage to ground). Here, the capacitor Cx may be parasitic capacitance formed in between the gate-source of the Nch transistor Tr73, and a capacitative element (a capacitor) can be attached (added) separately in between the gate-source in addition to the parasitic capacitance.
Initially, the drive control operation of the organic EL devices OEL in the pixel driver circuits DCx of such construction, in a write-in operation period, while applying a high-level (selection level) scanning signal Vsel to the scanning lines SL, the power supply voltage Vsc at the same time applies a low-level to the voltage lines VL. Also, synchronizing with this timing, the pixel driver circuits DCx supplies the predetermined write-in current Ipix (equivalent to the drive current ID mentioned above) to the signal lines DL, which is required to perform a light generation operation of the organic EL devices OEL byway of predetermined luminosity gradation. Here, negative polarity current is supplied as the write-in current Ipix and set up so the relevant current is drawn in the direction of the data driver 130A via the signal lines DL from the side of the pixel driver circuits DCx (current sinking method).
Accordingly, Nch transistors Tr71 and Tr72 which constitute the pixel driver circuits DCx perform an “ON” operation. At the same time, a low-level of the power supply voltage Vso is applied to contact Nxa (Namely, the gate terminal of the Nch transistor Tr73 and one end side of the capacitor Cx), along with a low supply voltage level applied to contact Nxb (Namely, the source terminal side of the Nch transistor Tr73 and the other end side of the capacitor Cx) rather than a low-level of the power supply voltage Vsc via the Nch transistor Tr72 by the drawing in operation of the write-in current Ipix.
In this way, when a voltage potential difference occurs between the contacts Nxa and Nxb (between the gate-source of the Nch transistor Tr73), Nch transistor Tr73 performs an “ON” operation and the write-in operating current according to the write-in current Ipix flows in the signal lines DL direction via Nch transistor Tr73, contact Nxb and Nch transistor Tr72 from the voltage lines VL (Reference
At this time, the electric charge corresponding to the voltage potential difference produced between the contacts Nxa and Nxb is stored in capacitor Cx, and is held as the voltage component (the capacitor charges). Also, at this time since the supply applied to the anode terminal (contact Nxb) of the organic EL device OEL becomes lower than the supply (voltage to ground) of the cathode terminal, reverse-bias voltage is applied to the organic EL devices OEL. The light generation drive current does not flow into the organic EL devices OEL, and light generation is not performed.
Subsequently, in the light generation operation period, at the same time it applies a low-level (non-selection level) scanning signal Vsel to the scanning lines SL, a high-level of the power supply voltage Vso is applied to the voltage lines VL. Also, synchronizing with this timing, the drawing in operation of the write-in current Ipix (Namely, write-in control current) is suspended.
Accordingly, since application of the voltage level resulting from the drawing in operation of the write-in current Ipix to contact Nxb is interrupted (shut down) while Nch transistorsTr71 andTr72 perform an “OFF” operation, application of the power supply voltage Vsc to contact Nxa is accordingly interrupted. The capacitor Cx then holds the electric charge stored in the write-in operation mentioned above.
In this way, when capacitor Cx holds the charge voltage at the time of the write-in operation, the voltage potential difference between contact Nxa and Nxb (between gate-source of the Nch transistor Tr73) will be held, and Nch transistor Tr73 maintains an “ON” state. Also, because the power supply voltage Vsa which has a voltage level higher than the voltage to ground is applied to the voltage lines VL, the supply applied to the anode terminal (contact Nxb) of the organic EL devices OEL becomes higher than the supply (voltage to ground) of the cathode terminal.
Therefore, the light generation drive current flows into the organic EL devices OEL in the forward-bias direction via Nch transistor Tr73 and contact Nxb from the voltage lines VL, and the organic EL devices OEL emit light by predetermined luminosity gradation. Here, since the voltage potential difference (charge voltage) held by the capacitor Cx is equivalent to the voltage potential difference when flowing in the write-in operating current to Nch transistor Tr73 at the time of the above-mentioned write-in operation, the light generation drive current which flows to the organic EL devices OEL will have the current value equivalent to the above-mentioned operating current. Accordingly, in the light generation operation period, based on the voltage component in response to the predetermined light generation state (luminosity gradation) written in the write-in operation period, the light generation drive current will be supplied continuously and the organic EL devices OEL continue operation and emit light by the desired luminosity gradation (Reference
Subsequently, the first embodiment of the data driver applied to the display device related to this invention will be explained. The current generation circuit of each of the above-mentioned embodiment is formed individually in each signal line, and the data driver related to this embodiment is constituted so the supplied reference current has a constant value via a common current supply source line from a single current generator for example, as opposed to each current generation circuit.
Here, an explanation will be provided matching the configuration of the current generation circuit mentioned above. Furthermore, with reference to any configuration equivalent in each embodiment mentioned above, the same or equivalent nomenclature is appended and hereinafter the explanation is simplified or omitted from the description.
As shown in
<<Drive Control Method>>
Next, the drive control method of the display device which has the configuration mentioned above will be explained with reference to the drawings.
Here, in addition to the configuration shown in
Initially, the drive control operation in the data driver 130A performs a signals holding operation which takes in the display data d0-d3 supplied from the display signal generation circuit 160 to the signal latch circuits 101, 102, 103 . . . formed in the write-in current generation circuits ILA1, ILA2, ILA3 . . . mentioned above and holds the display data d0-d3 during a fixed period; and performs by setting the current generation supply operation which generates the write-in current Ipix according to the above-mentioned display data d0-d3 that is supplied to each display pixel via each of the signal lines DL1, DL2, DL3 . . . , based on the holding signals d10-d13, d20-d23, d30-d33, of the display data d0-d3 taken in by the signals holding operation from the current generation circuits 201A, 202A, 203A, . . . formed in the write-in current generation circuits ILA1, ILA2, ILA3 . . .
Here, in the signals holding operation, as shown in
Additionally, in the current generation supply operation, as shown in
Here, the write-in current Ipix is controlled to all the signal lines DL1, DL2, DL3, . . . supplied simultaneously in parallel for at least a fixed period.
In addition, as mentioned above in this embodiment, a plurality of gradation currents are generated which have a current value of a predetermined ratio (For example, 2n; n=0, 1, 2, 3, . . . ) from the specified transistor size established in advance to the reference current Iref. Based on the above-mentioned holding signals, predetermined gradation currents are selected and integrated in response to the “ON/OFF” operation of the switching transistors. Negative polarity write-in current Ipix is generated in response to the light generation luminosity in each of the display pixels EM, and the write-in current Ipix flows so it may be drawn in the direction of the data driver 130A from the signal lines DL1, DL2, DL3, . . . side.
Also, in the data driver related to this embodiment, as shown in
Furthermore, the drive control operation in the display panel 110A, as shown in
To be exact, the write-in operation period Tse to the display panel, as shown in
As shown in
Consequently, in the data driver 130A and the display device 100A related to this embodiment, the write-in current Ipix is supplied to specified lines of the display pixel clusters via each of the signal lines DL in the data driver 130A and the display device 100A related to this embodiment. Since it is generated from each of the write-in current generation circuits ILA1, ILA2, ILA3 . . . based on the reference current Iref (In detail, the current which is the reference current Iref equally divided by the number of the write-in current generation circuits.) supplied in common via the reference current lines Ls from the current generator IR according to the display data d0-d3 (or the write-in current Ipix) supplied to each of the write-in current generation circuits ILA1, ILA2, ILA3 . . . , the current value does not fluctuate. The limitations of operation resulting from the electrical charge and discharge process of the reference current supply line Ls can be alleviated. Furthermore, significant enhancement in the operating speed of the data driver, the display response characteristics in the display device, as well as the display image quality can be achieved with distinctly improved performance.
Besides, the data driver (write-in current generation circuit), in contrast to the reference current transistors into which the above-mentioned reference current flows, the channel width of a plurality of gradation current transistors that have a circuit arrangement with a current mirror circuit are set so each consists of a predetermined ratio (For example, 2n gradation) Since the write-in current flows to a plurality of gradation currents set to a 2n current value, display data is generable by integrating these according to their status. With a relatively simple circuit arrangement, write-in current can be generated using analog current that has a suitable current value corresponding to the display data (a plurality of digital signal bits), as well as a light generation operation of the display pixels EM can be performed by the proper luminosity gradation.
Subsequently, the second embodiment of the data driver applied to the display device related to this invention will be explained.
Although the data driver in the first embodiment of the above-mentioned is configured with a circuit arrangement corresponding to the current sinking method whereby write-in current is drawn in the direction of the data driver from the display pixels, this invention is not limited to this and conversely may be configured with a circuit arrangement of the current application method whereby supplied write-in current flows (pours) in the direction of the display pixels from the data driver.
The data driver concerning this embodiment is configured with a circuit arrangement of the current application method.
Here, an explanation will be provided matching the configuration of the current generation circuit mentioned above. Furthermore, with reference to any configuration equivalent in each embodiment mentioned above, the same or equivalent nomenclature is appended and hereinafter the explanation is simplified or omitted from the description.
A data driver 130B related to this embodiment, for example, as shown in
The drive control operation of data driver 130B is the essentially the same as that of the first drive control method (Reference
In addition, the current generation supply operation, based on the holding signals d10*-d13, d20*-d23*, d30*-d33* . . . , selects and integrates the predetermined gradation current from a plurality of gradation currents which have a current value of a predetermined ratio specified in advance to the reference current Iref drawn out from each of the current generation circuits 201B, 202B, 203B, . . . ; generates the write-in current Ipix of positive polarity, which is supplied sequentially so as to flow in the direction of the display pixels EM of each of the signal lines DL1, DL2, D3, . . . from the data driver 130B side.
<<Pixel Driver Circuit>>
In addition, the shown pixel driver circuit is just one example applicable to the display device concerning this embodiment. Needless to say, there can be other circuit arrangements which have an equivalent operational function.
As shown in
In addition, this example configuration comprises the organic EL devices OEL with which light generation luminosity is controlled by the light generation drive current supplied from such a pixel driver circuit DCy. The anode terminal is each other connected to contact Nyc of the above-mentioned pixel driver circuit DCy, and the cathode terminal is connected separately to the low supply voltage Vgnd. It is here, the capacitor Cy may be parasitic capacitance formed in between the gate-source of the transistor Tr83, and a capacitative element (a capacitor) can be attached (added) separately in between the gate-source in addition to the parasitic capacitance.
The drive control operation of the organic EL devices OEL in the pixel driver circuit DCy which has such a configuration, first, in the write-in operation period, supplies the write-in current Ipix for performing a light generation operation of the organic EL devices OEL by predetermined luminosity gradation to the signal lines DL synchronizing with this timing while applying a high-level (selection level) scanning signal Vsel to the scanning lines SL. Here, the write-in current Ipix supplies positive polarity current set up so the relevant current flows in the direction of the pixel driver circuit DCy via the signal lines DL from the data driver 130B side.
Accordingly, at the same time the transistors Tr82 and Tr84 which form the pixel driver circuit DCy perform an “ON” operation, the transistor Tr81 performs an “OFF” operation, and positive current is supplied corresponding to the write-in current Ipix supplied to the signal lines DL which is applied to contact Nya. Furthermore, as between contact Nyb and contact Nyc connect, between the gate-source and between the source-drain of the transistor Tr83 controls this electric potential. By this, a voltage potential difference according to the write-in current occurs in capacitor Cy (between contact Nya and contact Nyb). The electric charge corresponding to this voltage potential difference is accumulated and held as the voltage component (charge).
Subsequently, in the light generation operation period, while applying a low-level (non-selection level) scanning signal Vsel to the scanning lines SL, it synchronizes with this timing to interrupt (turn off) the supply of the write-in current Ipix. Consequently, capacitor Cy holds the electric charge accumulated in the write-in operation mentioned above by intervening electrically between the transistors Tr82 and Tr84 performing an “OFF” operation, the signal lines DL and contact Nya, together with between contact Nyb and contact Nyc.
In this way, when capacitor Cy holds the charge voltage at the time of the write-in operation, the voltage potential difference between contact Nyb and contact Nyc (between the gate-source of transistor Tr83 ) will be held, and the transistor Tr83 performs and “ON” operation. As a result, by application of the above-mentioned scanning signal Vsel (low-level), since the transistor Tr81 performs an “ON” operation simultaneously, the light generation drive current responsive to the write-in current Ipix flows to the organic EL devices OEL via transistors Tr81 and Tr83 from the voltage contact +V (high supply voltage), and the organic EL devices OEL emit light by predetermined luminosity gradation. In this way, in the pixel driver circuit related to this embodiment, an Nch transistor Tr83 will have the function as the transistor for the light generation drive.
Accordingly, in the write-in operation period in the display panel 110A which has the pixel driver circuit (Reference
Therefore, as explained in this embodiment, the write-in current supplied to the display panel (display pixels EM) can in fact be generated based on the current value of the reference current supplied via a common current supply source line. The current value supplied to each of the write-in current generation circuits which form the data driver does not fluctuate. Thus, limitations in the operating speed originating in the charge and discharge of the current supply source line can be alleviated, as well as the operating speed of the data driver can be elevated.
Subsequently, the third embodiment of the data driver applied to the display device mentioned above will be explained.
The data driver in this third embodiment applies the current generation section of the current generation circuit in the fifth embodiment shown in
Here, concerning any configuration equivalent in the embodiments mentioned above, the same or equivalent nomenclature is appended and the explanation is simplified or omitted from the description.
A current generation circuit ILC configured with each of the write-in current generation circuits provided in the data driver related to this embodiment, for example, as shown in
In a current generation circuit ILC which has such a configuration, if the high-level selection signal SL is input, the transistor Tr71 formed in the operation setting circuit 70 performs an “ON” operation, the current output contact OUTi of current generation section 20C will be connected to the signal lines DL via the transistor Tr71, and the current generation circuit will be set to a selection state.
Concurrently at the same time, a low-level timing control signal is input to contact CK of each of the latch circuits LC0-LC3 that form the signal latch section 10, which is uninvolved with the output timing of the shift signal SR, from the inverter 72 and the NAND circuit 73, and the inverters 74 and 75; as well as a high-level timing control signal is input regularly to input contact CK*. The display data d0-d3 are taken in and held in each of the latch circuits LC0-LC3, as well as timing to which the high-level control signal rck mentioned above is applied. Subsequently, the reference current Iref is supplied to the current generation section 20C, gradation currents according to the display data d0-d3 are integrated, and the write-in current Ipix corresponding to the light generation luminosity in each of the display pixels EM is generated. Accordingly, the write-in current Ipix based on the display data d0-d3 generated to which timing is applied selectively by the control signal rck mentioned above in each of the current generations circuits ILC is supplied sequentially to each of the display pixels EM via the signal lines DL.
On the other side, if a low-level of the selection signal SL is input, the transistor Tr71 will perform an “OFF” operation, the current output contact OUTi of the current generation section 20C will be separated from the signal lines DL, and the current generation circuit ILC will be set as a non-selection state.
Instantaneously, the inverter 72 and NAND circuit 73 along with the inverters 74 and 75 respond to the output timing of the shift signal SR (high-level) to the input contact CK and input contact CK* of each of the latch circuits LC0-LC3. The timing control signal which has a signal level of opposite polarity takes in and holds the display data d0-d3. Timing by the control signal rck mentioned above is applied and the write-in current Ipix is generated according to the display data d0-d3. Accordingly, although the write-in current Ipix is generated based on the display data d0-d3, it will be in the state where the signal lines DL are not supplied.
The drive control operation in the data driver comprising such as the current generation circuit ILC is similar to the drive control method (Reference
Furthermore, it is the timing by which the above-mentioned control signal rck is applied selectively (It does not become a high-level simultaneously.) to only the current generation circuit ILC in a plurality of current generation circuits ILC in the current generation supply operation. The reference current Iref is supplied to the current generation section 20C based on the holding signals d10*-d13*. Predetermined gradation currents are selected and integrated from a plurality of gradation currents which have a current value specified in advance based on this reference current Iref, generated write-in current Ipix of regular polarity via each of the signal lines DL1, DL2, DL3 . . . is supplied sequentially so it flows in the direction of the display pixels EM.
Therefore, according to the display device related to this embodiment, generation of the write-in current is addressed by supplying selectively the reference current Iref to each of the current generation circuits ILC formed corresponding to each of the signal lines DL1, DL2, DL3, . . . , by generating and integrating the gradation currents according to the display data d0-d3 based on the reference current Iref. Because the write-in current has an equal and suitable current value which can be supplied to each of the display pixels EM, without being influenced by variations in circuit characteristics between each of the current generation circuits and the component characteristics of the active device transistors and the like, a favorable gradation display operation can be realized and enhancement in the display image quality can be achieved.
In addition, when generating the write-in currents in this embodiment, the control signal rck performs switching control to set the switching circuits TS1-TS2 or TS3-TS4 supply state of the reference current Iref to each of the current generation circuits ILC (current generation section 20C). Although this case applied the signal generated and output to the system controller 150 was explained. This invention is not limited to this in order to reduce the processing load in the system controller and the like, and to simplify circuit arrangement. For example, using other control signals currently supplied for operational control in each current generation circuit ILC, you may constitute a configuration so the switching control of the above-mentioned switching circuits TS1-TS2 or TS3-TS4 may be performed.
For example, as shown in
Namely, the timing (The timing of the shift signals SR1 and SR2 output from the shift register circuit 131, and synchronizing the timing) based on the timing control signal to input contacts CK and CK* of each of the latch circuits LC0-LC3 as mentioned above, in each of the latch circuits LC0-LC3 a signal holding operation which takes in and holds the display data d0-d3 is performed and, a high-level control signal rck timing is applied on the other side. The current generation supply operation is performed which generates the write-in current Ipix according to the display data d0-d3 and the reference current Iref is supplied to the current generation section 20C. In applying the drive control method of repeating successively each of these operations simultaneously (in parallel), the timing control signal and the above-mentioned control signal rck supplied timing input to input contact CK of each of the latch circuits LC0-LC3 will be set in sync. Thus, each operation is controllable using a single timing control signal.
Therefore, the circuit arrangement can be simplified while the processing load in the system controller and the like can be reduced; since drive control can be performed simultaneously using the existing control signal supplied to each of the current generation circuits ILC, the signal holding operation in the signal latch section 10 and the current generation supply operation in the current generation section 20C according to such a configuration.
In addition, in the current generation circuits ILC and ILD shown in
Next, the fourth embodiment of the data driver applied to the display device mentioned above will be explained.
As for the data driver related to this embodiment, briefly, in this configuration two sets of write-in current generation circuits are formed in each of the signal lines. Each set of the write-in current generation circuits to predetermined operation timing perform taking in of the display data, holding, generation of the write-in current and the supply operation are performed complementarily and successively. Also, when each of the write-in current generation circuits comprises the same configuration as the current generation circuit in the third embodiment of the current generation circuit, each of the write-in current generation circuits supply specified voltage (black display voltage) to the signal lines, thereby each has a specified state setting section and the display data becomes a specified value accordingly. Here, in this embodiment, positive reference current which has a constant current value from a single current generator is supplied to the write-in current generation circuit cluster.
Here, the explanation matches with the configuration of the current generation circuit mentioned above. Here, concerning any configuration equivalent in the embodiments mentioned above, the same or equivalent nomenclature is appended and the explanation is simplified or omitted from the description.
The data driver 130C related to this embodiment, for example as shown in
Here, two sets of write-in current generation circuit clusters 135A and 135B are configured at least so the reference current Iref input in common has a constant current value regularly supplied from the current generator IR (equivalent to the current generator IRA mentioned above) and the display data d0-dk supplied from the display signal generation circuit 160.
Two sets of the write-in current generation circuit clusters 135A and 135B have a configuration each comprising a plurality of write-in current generation circuits ISC1, ISC2,. . . and ISD1, ISD2, . . . . Each of the write-in current generation circuits ISC1, ISC2, . . . and ISD1, ISD2, . . . shown in
Here, since the signal latch section 10x, the current generation section 20x and the specified state setting section 30x are equivalent to the signal latch section 10 each shown in
The operation setting circuit 40x, for example, as shown in
In the write-in current generation circuit ISx which has such a configuration, if a high-level selection setpoint signal (A control signal which sets the write-in current generation circuit into a selection state) is input from the selection setting circuit 136A, the Nch transistor TN41 formed in the operation setting circuit 40xwill perform an “ON” operation. The current output contact OUTi of the current generation section 20x is connected to the signal lines DL via the Nch transistor TN41. Simultaneously at this time, a low-level timing control signal to signal latch section 10x input contact CK not involved with the output timing of the shift signal SR from the inverter 42, the NAND circuit 43 and the inverters 44 and 45, and also a high-level timing control signal is input regularly to input contact CK*. The display data d0-d3 are taken in, and the write-in current Ipix according to the display data d0-d3 is generated by the current generation section 20x.
When display data d0-d3 are all set to zero (0), at the same time the write-in current Ipix in the current generation section 20x is interrupted (shut down) and a light generation operation (for example, black display operation) in the specified state of the display pixels EM is performed. The specified voltage vbk (black display voltage)in response to a black display operation to output contact OUTi current of the current generation section 20x by the specified state setting section 30x is applied.
Accordingly, in an ordinary gradation display operation excluding a black display state, the write-in current Ipix generated, based on the display data d0-d3, is supplied to the display pixels EM via the signal lines DL. A predetermined specified voltage Vbk (black display voltage) is applied to the signal lines DL, while shutting down the supply of the above-mentioned write-in current Ipix at the time of a black display operation.
Conversely, if a low level selection setpoint signal (a control signal which sets the write-in current generation circuit as the non-selection state) is input from the selection setting circuit 136A, the Nch transistor TN41 will perform an “OFF” operation, and the current output contact OUTi of the current generation section 20x will be isolated (separated) from the signal lines DL.
Simultaneously at this time, corresponding to the output timing of the shift signal SR, a timing control signal which has a complementary (matching) signal level is input to the input contact CK and input contact CK* of the signal latch section 10x corresponding to the output timing of the shift signal SR from the inverter 42 and the NAND circuit 43, along to the inverters 44 and 45, taking in the display data d0-d3, held and the generation operation of the write-in current Ipix are performed. Accordingly, although the write-in current Ipix is generated based on display data d0-d3, it will be in the state where the signal lines DL are not supplied, and the write-in current generation circuit will be essentially set into a non-selection state. Thus, from the selection setting circuit 136A described later, by setting appropriately the signal level of the selection setpoint signal (The non-inverted signal SLa and the inversion signal SLb of the switching control signal SEL.) input to two sets of the write-in current generation circuit clusters 135A and 135B, the selection-state of either of the two sets of the write-in current generation circuit clusters 135A and 135B can be set into the selection state and the other can be set into the non-selection state.
Moreover, the inverted latch circuit 133A and the selection setting circuit 136A, briefly, has a circuit arrangement equivalent, for example, as shown in
Specifically, the inverted latch circuit 133A and the selection setting circuit 136A, the shift clock signal SFC or the switching control signal SEL is input into the input contact INs (the input terminal of the inverted latch circuit 133A or the selection setting circuit 136A) of an inverter INV1 and the output contact of the inverter INV1 is connected to the input contact of an inverter INV2. The output contact of the inverter INV2 is connected to the input contact of the inverter INV4. Also, the above-mentioned shift clock signal SFC or the switching control signal SEL is input into the input terminal of an inverter INV3 and the output contact is connected to the input contact of an inverter INV5. While the output contact of the inverter INV4 is connected to the input contact of the inverter INV5 and an inverter INV6, the output contact of the inverter INV5 is connected to the input contact of the inverter INV4 and an inverter INV7. Also, the output contact of then inverter INV6 is connected to a non-inverted output terminal OUTs of the inverted latch circuit 133A or the selection setting circuit 136A, and the output contact of the inverter INV7 is connected to inverted output terminal OUTS* of the inverted latch circuit 133A or selection setting circuit 136A.
In the inverted latch circuit 133A and the selection setting circuit 136A which have such a configuration, if the shift clock signal SFC or the switching control signal SEL is applied, the relevant signal level is held by the inverters INV4 and INV5. A non-inverted signal and an inverted signal of the present signal levels are each output from the non-inverted output terminal OUTs and the inverted terminal OUTs* to the shift register circuit 134A as the non-inverted clock signal CK1 and inverted clock signal CK2. Also, the non-inverted signal SLa and the inverted signal SLb are supplied to the write-in current generation circuit cluster 135A (Each of the write-in current generation circuits ILA1, ILA2, . . . ) and the write-in current generation circuit cluster 135B (Each of write-in current generation circuits ILB1, ILB2, . . . ).
<<Drive Control Method>>
Next, the drive control method of the display device which has the configuration mentioned above will be explained with reference to the drawings.
Explanations will also refer accordingly to the configuration of the third embodiment of the current generation circuit shown in
First, the drive control operation in the data driver 130C, the signal holding operation takes in the display data d0-d3 supplied from the display signal generation circuit 160 to each of the signal latch sections 10x formed in each current write-in current generation circuit formed by the write-in current generation circuit clusters mentioned above and is held during a fixed period. The current generation section 20x is formed in the write-in current generation circuit ISx, based on the holding signals d10-d13 of the display data d0-d3 taken in by the present signal holding operation. While performing sequential execution of the current generation supply operation, the write-in current Ipix is generated according to the above-mentioned display data d0-d3 and supplied to each of the display pixels EM via each of the signal lines DL1, DL2, . . . . At the same time as performing this series of operations in two sets of write-in current generation circuit clusters from the selection setting circuit 136A, while performing the above-mentioned current generation supply operation from one of the write-in current generation circuit cluster, it accomplishes, by performing repeatedly, an alternate operation to perform simultaneously (in parallel) the above-mentioned signal holding operation from the write-in current generation circuit cluster on other side.
Especially, in the data driver related to this embodiment, when and the like accomplishing a black display operation which performs a light generation operation simultaneously by the minimum luminosity gradation of the pre-display pixels that constitute the display panel, for example, in addition to the above-mentioned signal holding operation and the current generation supply operation, while shutting down the supply of the write-in current Ipix to all of the signal lines DL1, DL2, . . . , it is controlled to apply the specified voltage Vbk (black display voltage) to all of the signal lines DL1, DL2, . . . .
First, the signal holding operation, as shown in
Also, as shown in
Here, the write-in current Ipix is set up so it is supplied simultaneously in parallel during a constant period, at least, to each of the signal lines DL1, DL2, . . . . Also, in this embodiment as mentioned above, a plurality of gradation currents are generated which have a current value of a predetermined ratio (For example, 2n; n=0, 1, 2, 3, . . . ) (see claims 12 and 15 formula) specified from the transistor size in advance to a single reference current Iref; selects and integrates the predetermined gradation currents by an “ON/OFF” operation of switch transistors based on the above-mentioned holding signal; generates the write-in current Ipix of negative polarity; and flows the write-in current Ipix so it is drawn in the direction of the data driver 130A from the signal lines DL1, DL2, . . . side.
In the black display operation, as show in
The write-in current generation circuit clusters formed in the data driver 130A are controlled so two cluster sets alternately set into a selection state. For example, the write-in current Ipix from one write-in current generation circuit cluster 135A supplies the display pixels EM of the oddth lines (odd numbered lines), and the write-in current Ipix from the write-in current generation circuit cluster 135B supplies the display pixel clusters of the eventh lines (even numbered lines) on the other side.
Consequently, in the data driver 130C and the display device 100A related to this embodiment, at the time of an ordinary gradation display operation with each of the write-in current generation circuits ISx formed corresponding to each of the signal lines DL1, DL2, . . . , gradation currents according to the display data d0-d3 are generated, integrated and each of the display pixels EM is supplied with the write-in current Ipix which has a suitable current value. While on the other side, at the time of a black display operation, write-in current Ipix from the current generation circuit ISx is interrupted (shutdown). Since the predetermined black display voltage in response to a light generation operation by the minimum luminosity gradation in the display pixels EM is applied to each of the signal lines DL1, DL2, . . . , it is possible to attain a favorable gradation display and the specified voltage can successfully stabilize the signal level of each of the signal lines DL1, DL2, . . . at the time of a black display operation. It can shift to a black display state rapidly and enhancement in the display response characteristics in the display device together with the display image quality can be achieved.
In the write-in current generation circuit ISx in the data driver 130C while applying a current mirror circuit arrangement, by setting the channel width of a plurality of gradation current transistors which constitute the current mirror circuit to the reference current transistor, so each one consists of a predetermined ratio (for example, 2n gradation), a plurality of gradation currents that have a current value specified with the above-mentioned ratio can be flowed to a single reference current supplied from a single current generator with the display data d0-d3 (a digital signal which is two or more bits). Since the write-in current Ipix has 2n gradation of current value, integrating these suitably is generable. Therefore, a relatively simple circuit arrangement can generate the write-in current composed of analog current which has a suitable current value corresponding to the display data, and a light generation operation of the display pixels EM can be performed by the proper luminosity gradation.
Also, although the case where the data driver comprising two sets of the write-in current generation circuits were applied to each of the signal lines arranged to the display panel in this embodiment was explained, this invention is not limited to this and may apply a data driver which, for example, performs the current supply operation and generation of the write-in current by taking in and holding the display data serially comprising a single write-in current generation circuit to each of the signal lines.
Next, the fifth embodiment of the data driver applied to the display device mentioned above will be explained.
Although it has the current sinking method circuit arrangement which draws the current in the data driver side from the display pixels EM in the fourth embodiment of the above-mentioned data driver, the circuit arrangement of the current application method can be applied which flows in (pours in) the write-in current in the direction of the display pixels EM from the data driver. The fifth embodiment of the data driver comprises a circuit arrangement of the current application method.
Furthermore, the data driver of the write-in current generation circuits concerning this embodiment resembles the fourth embodiment of the data driver mentioned above. While two sets are formed in each of the signal lines, the write-in current generation circuit of each set with predetermined operation timing encompasses taking in and holding the display data complementary and continuously, as well as generating write-in current and a configuration that performs a supply operation. When the display data becomes a specified value, it has a configuration which supplies specified voltage (black display voltage) to the signal lines. Here, in this embodiment, supplied negative reference current has a constant current value from a single current generator to the write-in current generation circuit cluster.
Here, an explanation will be provided matching the configuration of the current generation circuit mentioned above. Furthermore, with reference to any configuration equivalent in each embodiment mentioned above, the same or equivalent nomenclature is appended and hereinafter the explanation is simplified or omitted from the description.
A data driver 130D related to this embodiment, for example, as shown in
Here, two sets of the write-in current generation circuit clusters 135C and 135D are formed so, at least, while the display data d0-d3 are input in common, the reference current Iref which has a constant current value regulated by the current generator IR may be drawn out in common.
Two sets of the write-in current generation circuit clusters 135C and 135D each comprise a plurality of the write-in current generation circuits ISE1, ISE2, . . . and ISF1, ISF2, . . . . Each of the write-in current generation circuits ISE1, ISE2, . . . and ISF1, ISF2, . . . is the equivalent to the current generation circuit ISB (Hereinafter generically named as a write-in current generation circuit ISy) shown in
Here, since the signal latch section 10y, the current generation section 20y and specified state setting section 30y are equivalent to the signal latch section 10 each shown in
The operation setting 40y, for example as shown in
In the write-in current generation circuit ILy which has such a configuration, if a high-level selection setpoint signal is input from the selection setting circuit 134B, a Pch transistor TP101 formed in the operation setting circuit 40y will perform an “ON” operation, and the current output contact OUTi of the current generation section 20y will be connected to the signal lines DL via the Pch transistor TP101. Concurrently at the same time, a low-level timing control signal is input to contact CK of the signal latch section 10y, which is uninvolved with the output of the timing of. the shift signal SR, from the inverter 102, the NAND circuit 103 and the inverters 104 and 105, as well as a high-level timing control signal is input regularly to contact CK*. The display data d0-d3 are taken in and the write-in current Ipix according to the display data d0-d3 is generated by the current generation section 20y.
When the display data d0-d3 are all set to zero (0), while the output of the write-in current Ipix in the current generation section 20y is interrupted (shut down), a specified voltage Vbk (black display voltage) in response to a black display operation is applied to the current output contact OUTi of the current generation section 20y by the specified state setting section 30y so a light generation operation (for example, black display operation) of the display pixel may be performed in the specified state.
Accordingly, in an ordinary gradation display operation, except a black display state, a predetermined black specified voltage Vbk (black display voltage) is applied to the signal lines DL, the write-in current Ipix generated based on the display data d0-d3 is supplied to the display pixels EM via the signal lines DL, thereby interrupting the supply of the above-mentioned write-in current Ipix in a black display operation (The selection state of a write-in current generation circuit).
On the other side, if a low-level selection setpoint signal is input from the selection setting circuit 134B, the Pch transistor TP101 will perform an “OFF” operation, and the current output contact OUTi of the current generation section 20y will be separated from the signal lines DL. Also, at this time, a timing control signal which has a complementary signal level is input to the input contact CK and input contact CK* of the signal latch section 10y in response to the output timing of the shift signal SR by the inverter 102 and NAND circuit 103, and inverters 104 and 105. A generation operation of the write-in current Ipix is performed by taking in and holding the display data d0-d3.
Accordingly, comparable to the fourth embodiment mentioned above, although the write-in current Ipix is generated based on the display data d0-d3, it will be in the state where signal lines DL are not supplied, and the write-in current generation circuit will be essentially set into a non-selection state.
The drive control operation such as the data driver 130D is same as that of the fourth embodiment mentioned above, and set in signal holding operation. With the signal latch circuits 10y formed in each write-in current generation circuits ISy of the write-in current generation circuit clusters set as a selection state, based on the shift signals SR1, SR2, . . . output sequentially from the shift register circuit 134B, the display data d0-d3 of each line are taken in sequentially and holding signals d10-d13 equivalent to the inversion signal of the display data d0-d3 are output to the current generation section 20y.
Additionally, the current generation supply operation. selects and integrates predetermined gradation currents from a plurality of gradation currents which have a current value specified in advance based on the holding signals d10*-d13*. Here, the write-in current Ipix of positive polarity is generated so the relevant current is supplied (applicable to poured in/flowed in) sequentially in the direction of the display pixels EM via each of the signal lines DL1, DL2, from the data driver 130B side.
In a black display operation, by setting the display data d0-d3, . . . as a black display state (the holding signals d10-d13 are all set to zero (0)), while generation of gradation currents in the current generation section 20y and the write-in current Ipix supply are suspended. A black display state is judged in the specified state setting section 30y and the specified voltage Vbk (black display voltage) corresponding to the black display (light generation operation by the minimum luminosity gradation) is applied sequentially to each of the signal lines DL1, DL2, . . . .
Therefore, also set to the display device which applied the data driver 130D related to this embodiment, by generating and integrating the gradation currents according to the display data d0-d3 from each of the write-in current generation circuits ISy formed corresponding to each of the signal lines DL1, DL2, . . . , each of the display pixels EM can be supplied as the write-in current Ipix which has a suitable current value, and a favorable gradation display operation can be achieved. On the other side, at the same time of a black display operation, while shutting down the write-in current Ipix from each of the current generation circuits ISy, by applying predetermined black display voltage to each of the signal lines DL1, DL2, . . . , it can shift to a black display state rapidly and enhancement in the display response characteristics in the display device, together with the display image quality can be achieved.
Next, the sixth embodiment of the data driver applied to the display device mentioned above will be explained.
While the write-in generation circuits are formed for every signal line; take in, hold and generate the write-in current; and a configuration that performs a supply operation to predetermined timing, each of the write-in current generation circuits are a system comprising the same configuration and write-in current generation circuits as the data driver of the fifth embodiment. Particularly, it has a specified state setting section and has a configuration which can accordingly supply specified voltage (reset voltage) to the signal lines as a specified value for the display data. Here, in this embodiment, a negative reference current which supplies a constant value from a single current generator to the write-in current generation circuit clusters.
Here, concerning any configuration equivalent in the embodiments mentioned above, the same or equivalent nomenclature is appended and the explanation is simplified or omitted from the description.
The data driver 130E in this embodiment, for example as shown in
Here, the write-in current generation circuits PXA1, PXA2, and PXA3, . . . are comprised of a configuration equivalent to the write-in current generation circuit ISy in the fifth embodiment of the data driver as shown in
<<Pixel Driver Circuit>>
Subsequently, the pixel driver circuit applied to each of the display pixels EM of the display panel 110B in the display device concerning this embodiment is explained briefly.
In addition, the pixel driver circuit shown here is only one example applicable to the display device related to this embodiment. Needless to say, there can be other circuit arrangements which have an equivalent function.
As shown in
Furthermore, each of the organic EL devices OEL with which luminescent brightness is controlled by the luminescent drive current from the pixel driver circuits DCx, are connected respectively with the anode terminal connected to the contact Nxc of the above-mentioned pixel driver circuits DCx and the cathode terminal connected to the low supply voltage Vgnd (for example, voltage to ground). Here, the capacitor Cx may be parasitic capacitance formed in between the gate-source of the Nch transistor Tr93, and a capacitative element (a capacitor) can be attached (added) separately in between the gate-source in addition to the parasitic capacitance.
The drive control operation of the organic EL devices OEL in the pixel driver circuits DCx which has such a configuration, first, in a write-in operation period applies a low-level scanning signal Vsel* to the scanning lines SLb as it applies a high-level (selection level) scanning signal Vsel to the scanning lines SLa. Subsequently, synchronizing with this timing, the pixel driver circuits DCx supplies the write-in current Ipix to the signal lines DL for performing luminescent operation of the organic EL devices OEL by predetermined brightness gradation. Here, the write-in current Ipix current of positive polarity is supplied and set up so the proper current flows in (pours in) the direction of the display pixels EM (pixel driver circuits DCx) via the signal lines DL from the data driver 130E side.
Accordingly, as the transistors Tr92 and Tr94, which constitute the pixel driver circuits DCx perform an “ON” operation, the transistor Tr91 performs an “OFF”operation and positive potential corresponding to the write-in current Ipix supplied to the signal lines DL is applied to contact Nxa. Furthermore, as contact Nxb and contact Nxc instantly connect with each other, the voltage potential between the gate-source of the transistor Tr93 is controlled to the equivalent voltage potential. Therefore, as transistor Tr93 performs an “OFF” operation, between the ends of capacitor Cx (between contact Nxa and contact Nxb), the voltage potential difference according to the amount of increase in the write-in current Ipix occurs, and the corresponding electric charge in relation to the voltage potential difference is accumulated and held as the voltage component.
Subsequently, in the luminescent operation period, as the low-level (non-selection level) scanning signal Vsel is applied to the scanning lines SLa together with a high-level scanning signal Vsel* also applied to the scanning lines SLb, in synchronizing with this timing, the supply of the write-in current Ipix is interrupted (shut down). Accordingly, capacitor Cx holds the charge stored up in the write-in operation mentioned above by transistors Tr92 and Tr94 which performed an “OFF” operation and electrically interrupt between the signal lines DL and contact Nxa, as well as between contact Nxb and contact Nxc.
Thus, when capacitor Cx retains (stores) the charge voltage at the time of the write-in operation, the voltage potential difference between contact Nxa and contact Nxb (between the gate-source of Tr93 of a transistor) will be held, and the transistor Tr93 performs an “ON” operation.
Additionally, by application of the above-mentioned scanning signal Vsel (low-level), transistor Tr91 performs an “ON” operation simultaneously. The luminescent drive current according to the write-in current Ipix (the charge retained in capacitor Cx) flows into the organic EL devices OEL via transistors Tr91 and Tr93 from the supply contact Vdd (high supply voltage), and the organic EL devices OEL emit light by predetermined brightness gradation. Thus, in the pixel driver circuits DCx as applied to this embodiment, the transistor Tr93 has the function as the transistor for the luminescent drive.
<<Drive Control Method>>
Next, the operation of the display device which has the configuration mentioned above is explained with reference to the drawings.
Here, in addition to the configuration shown in
The drive control operation in the data driver 130E, performs by setting up sequentially a reset operation, a signal holding operation and a current generation supply operation. Initially, the reset operation applies the specified voltage Vr(reset voltage) to each of the signal lines DL1, DL2, DL3, . . . via the specified state setting section formed in each of the gradation current generation circuits PXA1, PXA2, and PXA3, . . . mentioned above in advance of the signal holding operation described later. The signal holding operation outputs during a fixed period an inverted signal based on the display data d0-d3 while taking in and holding the display data d0-d3 supplied from the display signal generation circuit 160 to the data latch sections formed in each of the gradation current generation circuits PXA1, PXA2, and PXA3, . . . . The current generation supply operation supplies individually each of the display pixels EM via each of the signal lines DL1, DL2, DL3, . . . by generating the write-in current Ipx according to the above-mentioned display data d0-d3 from the current generation section formed in each of the gradation current generation circuits PXA1, PXA2, and PXA3, . . . based on the output signal from the data latch sections.
Also, the above-mentioned reset operations are performed simultaneously to each of the gradation current generation circuits PXA1, PXA2, and PXA3, . . . during periods other than a period that performs the signal holding operation within one horizontal select period and the current generation supply operation, for example, within retrace line periods. Conversely, the signal holding operation and the current generation supply operation are performed sequentially in each of the gradation current generation circuits PXA1, PXA2, and PXA3, . . . in a period except retrace line periods of one horizontal select period.
Here, as shown in
Subsequently, in furnishing a low -level reset control signal RST by outputting a low level timing control signal CLK to the data latch section of each of the gradation current generation circuits PXA1, PXA2, PXA3, . . . from each of the OR circuits 301, 302, 303, . . . , a non-inverted output signal of the display-data d0-d3 which were stored as mentioned above is output to the specified state setting section, and the specified voltage Vr (reset voltage) is applied to each of the signal lines DL1, DL2, DL3, . . . . Accordingly, the wiring capacity among other things of each of the signal lines DL1, DL2, DL3, . . . , the electrical charge stored up in the capacity component, such as the retention volume (capacitor Cx) and the like provided in the display pixels EM connected to each of the signal lines DL1, DL2, DL3, . . . discharges and each potential is set as a predetermined low potential state.
Furthermore, in a signal holding operation, as shown in
Additionally, in the current generation supply operation, the “ON/OFF” state of a plurality of switch transistors (switch transistors Tr26-Tr29 shown in
Here, the write-in current Ipix, for example, according to all of the signal lines DL1, DL2, DL3, . . . is set up so it can be supplied in parallel at least during a fixed period. Additionally, in this embodiment as mentioned above, a plurality of gradation currents, which have a current value of a predetermined ratio (For example, 2n; n =0, 1, 2, 3, . . . ) specified by transistor size relative in advance to the reference current Iref, are generated. When a switch transistor performs an “ON/OFF” operation based on the above-mentioned inverted output signal, predetermined gradation currents are selected and integrated; the write-in current Ipix of positive polarity is generated; and the present write-in current Ipix is supplied so it will flow (pour) in the direction of the signal lines DL1, DL2, DL3, . . . from the data driver 130E side.
In this embodiment as applied to the data driver 130E, as shown in
Therefore, the circuit configuration can be set up by m times the ratio, which takes into consideration the above-mentioned current value (Iref/m) supplied to each of the gradation current generation circuits PXA1, PXA2, PXA3, . . . . This current value ratio (Ratio of the channel width of the gradation current transistor to the reference current transistor) of each of the gradation currents to reference current is set up in the current mirror circuit section which forms the current generation section of each of the gradation current generation circuits PXA1, PXA2, PXA3, . . . .
Additionally, as in the other configurations set in each gradation current generation section, a switching means is provided which performs an “ON” operation selectively based on the shift signals SR1, SR2, SR3, . . . output from the shift register circuit 131C, for example, each of the gradation current generation circuits PXA1, PXA2, PXA3, . . . . As the write-in current Ipix is generated only in the period of the current generation supply operation based on the display data d0-d3, the reference current Iref from the above-mentioned current generator IR remains unchanged and supplies selectively each gradation current generation circuit PXA1, PXA2, PXA3, . . . .
The drive control operation in the display panel 110B is illustrated in
Specifically, in the write-in operation period Tse to the display pixels EM, as shown in
As shown in
Therefore, according to the data driver and display device related to this embodiment, the write-in current Ipix is supplied to the display pixels EM cluster of a specified line via each of the signal lines DL from each of the gradation current generation circuits PXA1, PXA2, PXA3, . . . . In particular, the write-in current Ipix generated consists of the constant reference current Iref which is supplied with a signal level that does not fluctuate and based on the display data d0-d3 of a plurality of digital signal bits from the current generator IR (via the common reference current supply line Ls). During the supply time (selection time) of the write-in current Ipix to the display pixels EM, even in the case where the light generation operation is set up briefly using relatively low luminosity gradation (When the current value of the write-in current Ipix is negligible.) with the high definition display panel and the like, the influence of transfer lag (transmission delay) in the signals supplied to the data driver (Each of the gradation current generation circuits PXA1, PXA2, PXA3, . . . ) to generate the write-in current Ipix can be eliminated, reduction of the operating speed of the data driver can be controlled and enhancement in the display response characteristics in the display device together with display image quality can be achieved.
Also, specifically in the case of the supply operation of the write-in current Ipix to each of the display pixels EM, in advance of the signal holding operation and the current generation supply operation in the data driver 130E, a reset voltage consisting of a constant low voltage is applied to each of the signal lines DL. Because the data driver can discharge sufficiently the electric charge accumulated in the capacitative wiring (parasitic capacitance) attached to the signal lines and the capacitative element retention volume (capacitor Cx of the pixel driver circuits) and the like of the display pixels EM, the display device can be initialized(reset). When a selection period of the display pixels EM is set up briefly as the gradation currents are written in based on fresh display data, especially when performing a light generation with low luminosity gradation immediately after performing a light generation operation with especially high luminosity gradation, the influence by the electric charge which remains in the above-mentioned capacitative element can be eliminated, and the time required to stabilize the signal level can be shortened. Therefore, because the level according to the display data can be stabilized quickly, the signal level applied to the signal lines or the display pixels and the writing speed to the display pixels can be raised. Also, the display response characteristics and display image quality of the display device can be enhanced.
Next, the seventh embodiment of the data driver applied to the display device mentioned above will be explained.
Although the above-mentioned data driver in the sixth embodiment comprises a circuit arrangement corresponding to the current sinking method drawing current write-in current in the direction of the data driver from the display pixels, this invention is not limited to this. It may be equipped with a circuit arrangement of the current application method supplied so the write-in current will flow (pour) in the direction of the display pixels from the data driver.
The data driver concerning this embodiment is configured with a circuit arrangement of the current application method.
Here, concerning any configuration equivalent in the embodiments mentioned above, the same or equivalent nomenclature is appended and the explanation is simplified or omitted from the description.
As shown in
Here, each of the write-in current generation circuits PXB1, PXB2, PXB3, . . . have a configuration comprises a configuration equivalent to the write-in current generation circuit ISx in the fourth embodiment of the data driver shown in
<<Pixel Driver Circuits>>
Subsequently, the configuration of the pixel driver circuits applied to each of the display pixels of the display panel 110D related to this embodiment will be explained.
The pixel driver circuits shown here only represents an example applicable to the display device related to this invention. Needless to say, there can be other circuit arrangements having an equivalent operational function.
As shown in
Additionally, the organic EL devices OEL for light generation luminosity are controlled by the light generation drive current supplied from the pixel driver circuits DCy. The organic EL device OEL anode terminal is connected to contact Nyb of the above-mentioned pixel driver circuits DCy, and the cathode terminal is individually connected to the low supply voltage Vgnd (voltage to ground). Here, the capacitor Cx may be parasitic capacitance formed in between the gate-source of the Nch transistor Tr103, and a capacitative element (a capacitor) can be attached separately in between the gate-source in addition to the parasitic capacitance.
Here, as shown in
<<Drive Control Method>>
In the drive control operation in the data driver 130B which has such a configuration is the same as that of the drive control method (Reference
Subsequently, in the signal holding operation, a non-inverted output signal of the display data d0-d3 taken in sequentially by each line (display pixels EM) from the data latch section of each of the write-in current generation circuits PXB1, PXB2, PXB3, . . . is output to each of the current generation sections based on the shift signals SR1, SR2, SR3, . . . output sequentially from the shift register circuit 131D.
Also, in the current generation supply operation, based on the above-mentioned non-inverted output signal from the current generation sections, a plurality of gradation currents are selectively integrated to generate the write-in current Ipix of negative polarity via each of the signal lines DL1, DL2, DL3, . . . from each of the display pixels EM side and supplied sequentially so the write-in current Ipix may be drawn in the data driver 130F direction.
In the write-in operation period, the drive control operation of the organic EL devices OEL in the pixel driver circuits DCy which has such a configuration, initially applies the power supply voltage Vsc of a low-level to the voltage lines VL while applying the scanning signals Vsel of a selection level (high-level) to the scanning lines SL. Also, synchronizing with this timing, the write-in current Ipix is supplied to the signal lines DL from the data driver 130F. Here, as a write-in current Ipix supplying current of negative polarity is set up so the proper current will be drawn in the direction of the data driver 130B via the signal lines DL from the display pixels EM (pixel driver circuits DCy) side. Accordingly, while the Nch transistors Tr101 and Tr102 which constitute the pixel driver circuits DCy perform an “ON” operation and a low-level of the power supply voltage Vsc is applied to contact Nya, a low supply voltage level is applied to contact Nyb rather than the low-level of the power supply voltage Vsc via the Nch transistor Tr102 by a drawing in operation of the write-in current Ipix.
In this way, when a voltage potential difference occurs between contacts Nya and Nyb (between the gate-source of the Nch transistor Tr103), the Nch transistor Tr103 performs an “ON” operation and current corresponding to the write-in current Ipix flows in the direction of the signal lines DL via the Nch transistor Tr103, contact Nyb and the Nch transistor Tr102 from the voltage lines VL.
At this time, the capacitor Cy electric charge corresponding to the potential difference produced in between contacts Nya and Nyb is accumulated and held as the voltage component (the capacitor charges). Also, at this point, since the supply applied to the anode terminal (contact Nxb) of the organic EL devices OEL becomes lower than the supply (voltage to ground) of the cathode terminal and reverse-bias voltage is applied to the organic EL devices OEL, the light generation drive current does not flow into the organic EL devices OEL and a light generation operation is not performed.
Subsequently, in the light generation operation period, while applying a non-selection level (low-level) of the scanning signal Vsel to the scanning lines SL, a high-level of the power supply voltage Vsc is applied to the voltage lines VL. Synchronizing with this timing, the drawing in operation of the write-in current Ipix is suspended.
Since application of a voltage level resulting from drawing in operation of a write-in current Ipix to contact Nyb is interrupted (shut down) while the Nch transistors Tr101 and Tr102 perform an “OFF” operation, application of the power supply voltage Vso to contact Nya is accordingly interrupted. The capacitor Cy then holds the electric charge stored in write-in operation mentioned above.
In this way, when the capacitor Cx holds the charge voltage at the time of the write-in operation, the voltage potential difference between contacts Nya and Nyb (between gate-source of the Nch transistor Tr103) will be held, and Nch transistor Tr103 maintains an “ON” state. Also, because the power supply voltage which has a voltage level higher than the voltage to ground is applied to the voltage lines VL, the light generation drive current flows into the organic EL devices OEL in the forward-bias direction via Nch transistor Tr103 and contact Nyb from the voltage lines VL.
Here, because the potential difference (charge voltage) held in the capacitor Cy is equivalent to the potential difference when the current flows corresponding to the write-in current Ipix to the Nch transistor Tr103 at the time of the above-mentioned write-in operation, the light generation drive current which flows into the organic EL devices OEL will have a current value equal to the above-mentioned current. The organic EL devices OEL continue operation to emit light by the desired luminosity gradation in the light generation operation period, based on the voltage component corresponding to the gradation currents written in the write-in operation period.
Further, like the series of drive control operations, shown in
Therefore, also established in the display device as applied to the data driver 130F related to this embodiment, by the reset operation the electric charge accumulated in the capacitative element attached to the signal lines DL or the display pixels EM is fully discharged. Afterwards it initializes in a predetermined low supply state and each of the gradation currents supplied to the display panel (display pixels) can be generated and supplied based on the display data consisting of the reference current of a constant current value and the digital signals. At the same time, it can control any reduction in the data driver operating speed resulting from the charge and discharge operation of the capacitative element attached to the signal lines, the reference current supply line or the like, as well as enhance the display response characteristics. The gradation currents which have a suitable current value according to the display data from the gradation current supply circuits individually formed corresponding to each of the signal lines can be generated, each of the display pixels can be supplied, and a favorable gradation display can be achieved.
Subsequently, the eighth embodiment of the data driver applied to the display device concerning this embodiment will be explained.
The data driver related to this embodiment is the same as the fifth embodiment of the data driver mentioned above is comprised with two sets of the write-in current generation circuits formed in each of the signal lines. Each set of the write-in current generation circuits perform take in and holding of the display data, generate write-in current, as well as a supply operation complementarily and successively according to predetermined operation timing. Each of the write-in current generation circuits comprises the same configuration as the write-in current generation circuit in the sixth embodiment of the data driver. Specified voltage (reset voltage) can be supplied for the display data to the signal lines as a specified value. Here, in this embodiment, the data driver is constituted so that negative reference current which has a constant value from a single current generator can be supplied to each of the write-in current generation circuit clusters formed in the two sets.
Here, concerning any configuration equivalent in the embodiments mentioned above, the same or equivalent nomenclature is appended and the explanation is simplified or omitted from the description.
As shown in
Here, the inverted latch circuit 133C, the shift register circuit 134C and the selection setting circuit 136C are each equipped with a configuration equal to the inverted latch circuit 133B in the fifth embodiment of the data driver, the shift register circuit 134B and the selection setting circuit 136B.
In addition, each of the write-in current supply circuits PXC and PXD have a configuration which comprises a configuration equal to the write-in current generation circuits ISy in the fifth embodiment of the data driver shown in
In the write-in current generation circuits PXC and PXD which have such a configuration, when the selection setpoint signal of a selection level is input from the selection setting circuit 136C, based on inverted output signals d10*-d13* output from the data latch sections 10y, the write-in current Ipix according to the display data d0-d3 is generated in the current generation section 20y. Concurrently, the display pixels EM are supplied via the signal lines DL and the write-in current generation circuits PXC or PXD are set into a selection state.
Conversely, when a non-selection level of the selection setpoint signal is input from the selection setting circuit 136C, although the display data d0-d3 are taken in and held in the data latch sections 10y the write-in current Ipix is not generated, but the signal lines DL will be supplied and the write-in current generation circuits PXC or PXD will be set into a non-selection state.
Specifically, the selection setting circuit 136C, by setting appropriately the selection setpoint signal (The non-inverted signal SLa or the inverted signal SLb of the switching control signal SEL) input to the two sets of write-in current generation circuit clusters 138C and 138D, either of the two sets of write-in current generation circuit clusters 138C and 138D can be set into a selection state and the other side can be set into a non-selection state.
<<Drive Control Method>>
Next, the operation of the display device which has the configuration mentioned above will be explained with reference to the drawings.
In the drive control operation in the data driver 130G, first, in two sets of the write-in current generation circuit clusters with one side set as a non-selection state, the signal holding operation sequentially takes in and holds the display data d0-d3 corresponding to each of the display pixels EM in each of the write-in current generation circuits (data latch sections) formed in these write-in current generation circuit clusters. The reset operation sets the specified state of each of the write-in current generation circuit clusters via each of the write-in current generation circuits (specified state setting section) and applies simultaneously the specified voltage Vr (reset voltage) to each of the signal lines DL and discharges the stored charge. A current supply operation generates the write-in current Ipix corresponding to the display data d0-d3 held in the above-mentioned signal holding operation by each of the write-in current generation circuits (current generation sections) which is supplied sequentially to each of the display pixels EM via each of the signal lines DL to perform the setting. Further, such a series of setting operations is performed successively and alternately in the two sets of write-in current generation circuit clusters.
The drive control operation in the data driver 130G, as shown in
Subsequently, in a reset operation after the selection setting circuit 136C sets the selection state by supplying the switching control signal SEL from the system controller 150, the display data d0-d3 corresponding to the specified state (Equivalent to a black display state) are taken in simultaneously through supplying the reset control signal RST in each of the write-in current generation circuits PXC1, PXC2, PXC3, . . . of the write-in current generation circuit cluster 138C. Accordingly, the specified voltage Vr (reset voltage) is applied simultaneously to each of the signal lines DL from each of the write-in current generation circuits PXC1, PXC2, PXC3, . . . and the electric charge accumulated in the capacitative element attached to each of the signal lines DL1, DL2, DL3, . . . and the display pixels EM discharges.
Subsequently, in the current generation supply operation based on the display data d0-d3 held in the above-mentioned signal holding operation in each of write-in current generation circuits PXC1, PXC2, PXC3, . . . (data latch sections), by integrating selectively a plurality of the gradation currents which are set so each one has a different current value ratio, the write-in current Ipix which specifies the luminosity gradation in each of the display pixels EM is generated and supplied sequentially via each of the signal lines DL1, DL2, DL3, . . . .
Furthermore, as shown in
Therefore, also set to the display device as applied to the data driver 130G related to this embodiment, the electric charge accumulated in the capacitative element attached to the signal lines DL or the display pixels EM from a reset operation is fully discharged. For that reason it initializes in the predetermined low supply state and each of the gradation currents supplied to the display panel (display pixels EM) can be generated and supplied afterwards based on the display data constituted by the reference current of a constant current value and the digital signals. At the same time, it can control any reduction in the data driver operating speed resulting from the charge and discharge operation of the capacitative element attached to the signal lines, the reference current supply line or the like, as well as enhance the display response characteristics. The gradation currents which have a suitable current value according to the display data from the gradation current supply circuits individually formed corresponding to each of the signal lines can be generated, each of the display pixels EM can be supplied, and a favorable gradation display can be achieved.
Additionally, by having two sets of write-in current generation circuits (clusters), repeating alternately the operation state of each of the write-in current generation circuits and performing this operation to each of the signal lines, and in view of the fact that the gradation currents have a current value corresponding appropriately to the display data and can be supplied continuously to each of the display pixels from the data driver, the light generation operation of the display pixels by predetermined luminosity gradation can be performed rapidly, as well as the display response speed and the display image quality can be further enhanced.
Moreover, in each embodiment of the data driver mentioned above, although the data driver has such a configuration which supplies in common the reference current from a single current generator with regard to supplying the reference current in a plurality of write-in current generation circuits formed in the data driver, this invention is not limited to this. It may have a constant current source for every data driver. Besides, it may have a constant current source for every gradation current generation circuit of a predetermined number of a plurality of gradation current generation circuits formed within a single data driver.
Next, as in the sixth through eighth embodiments mentioned above, the capacitative wiring attached to the signal lines and the like in prior to the operation which writes the gradation currents to the display pixels (parasitic capacitance) based on the display data or by the discharging (reset operation) the electric charge which remains in the capacitative element retention volume of the display pixels and the like to predetermined low supply voltage, the circuit arrangement of the data driver was made to realize a composition which shortens the time required to stabilize the appropriate signal levels according to the display data in the write-in operation of the gradation currents to the display pixels.
However, this invention is not limited to these configurations and can be made to achieve the technical concept that performs a reset operation according to the configuration of the pixel driver circuits which forms each of the display pixels. Hereinafter, explained in detail.
Although applied suitably for the display device concerning this invention, the configuration of the display pixels in this embodiment employs the data driver of the first and fifth embodiments mentioned above, the data driver side is not limited only to these configurations and may be equipped with other supplementary configurations.
Additionally, the configuration in
As shown in
Furthermore, as shown in
Also, in the pixel driver circuits DCxa and DCxb shown in
In such a configuration, by applying a high-level reset control signal RST to the reset line RL from the system controller 150, the Nch transistor Tr85 performs an “ON” operation by means of connecting electrically between the ground potential of the pixel driver circuits DCxa contact Nxc or the pixel driver circuits DCxb contact Nxa. An electric charge is accumulated (held) in the retention volume (capacitor Cx) of each of the pixel driver circuits DCxa and DCxb, which discharges to ground potential via the Nch transistor Tr85, and a reset operation of the display pixels EM is performed.
<<Drive Control Method>>
Here, the data driver which has the configuration of the first embodiment shown in
The drive control operation in the display device related to this embodiment performs by setting up sequentially, first, a reset operation which discharges the electric charge accumulated in the capacitative element attached to each of the display pixels EM prior to the supply operation of the write-in current from the data driver 130A; a signal holding operation which takes in and holds the display data supplied from the display signal generation circuit 160 to each of the write-in current generation circuits ILA1, ILA2, ILA3, . . . of the data driver; and a current generation supply operation which generates the write-in current Ipix based on the held display data and is supplied to each of the signal lines DL.
The drive control operation in the display device related to this embodiment, as shown in
Subsequently, in the signal holding operation, the same as each of the embodiments mentioned above, the operation takes in sequentially and holds the display data performed successively in one line periods and places the display data in the current generation supply operation. By selectively integrating a plurality of gradation currents, which are each set to a current value of a different ratio based on the display data held mentioned above, generates the write-in current Ipix which is supplied sequentially to the display pixels EM via each of the signal lines DL.
In the succeeding light generation operation, each of the display pixels EM emits light by the luminosity gradation corresponding to the display data by supplying continuously the light generation drive current to the organic EL devices OEL based on the held voltage component. The write-in current Ipix is written in simultaneously and supplied in parallel to each of the signal lines DL from the data driver 130A and held as the voltage component in capacitor Cx. By applying the scanning signal of a selection level to the scanning lines SL from the scanning driver 120A to the display pixel clusters discharges the electric charge accumulated in the capacitative element from the above-mentioned reset operation.
Accordingly, as the display device applied to the display panel (display pixels EM) related to this embodiment can be initialized in the predetermined low potential state, the electric charge accumulated in the capacitative element attached to the display pixels EM from a reset operation can be discharged favorably. Furthermore, it is also possible to set the appropriate amount of electrical charge to be accumulated according to the gradation currents generated based on the display data, as well as set the light generation drive current supplied to the organic EL devices OEL as a suitable current value. Consequently, at the same time degradation of the writing speed to the display panel resulting from the charge and discharge operation of the capacitative element attached to the display pixels EM can be controlled while enhancing the display response characteristics. Also, the light generation operation of each of the display pixels EM (organic EL devices) can be performed by the proper luminosity gradation according to the display data, and a favorable gradation display is achievable.
As mentioned above in this embodiment, since this configuration comprises a reset mechanism (the Nch transistor Tr85 and the reset line RL) for discharging the stored charge in advance of the write-in operation of the gradation currents to the display pixels EM (pixel driver circuits), the reset mechanism (For example, the specified state setting section formed in each of the write-in current generation circuits shown in
In addition, the display device related to each embodiment mentioned above illustrated only when setting the current polarity so the light generation drive current flows in the direction of the light emitting elements (organic EL devices) from the pixel driver circuits that forms the display pixels, but this invention is not limited to this. This invention may be constituted so the light generation drive current flows in the direction of the pixel driver circuits from the light emitting elements by inversely connecting the input/output terminals of the light emitting devices while connecting the high potential voltage to the other side of the light emitting devices.
Next, in the current generation circuit related to this invention, an embodiment with regard to applying the pixel driver circuits formed in each of the display pixels which constitutes the display panel in the display device will be explained with reference to the drawings.
Here, concerning any configuration equivalent in the embodiments mentioned above, the same or equivalent nomenclature is appended and the explanation is simplified or omitted from the description.
As shown in
Specifically, the display panel 110E applied to this embodiment, as shown in
Here, as shown in
<<Pixel Driver Circuits>>
The configuration formed in each embodiment of the current generation circuit mentioned above is applied to the pixel driver circuits DCz in this embodiment shown in
Initially, the drive control operation of the organic EL device OEL in the pixel driver circuits DCz which has such a configuration, while applying a high-level (selection level) scanning signal Vsel to the scanning lines SL, the operation synchronizes with this timing. The gradation data DP0-DP3 consisting of a plurality of digital signal bits corresponding to the display data d0-d3 provided from the display signal generation circuit 160 by the data driver 130H (described later) is then supplied to the signal line clusters DLz.
Accordingly, the gradation data DP0-DP3 are taken in individually and simultaneously for holding at each of the signal input contacts IN0-IN3 of the signal latch section 10z which forms part of the pixel driver circuits DCz. The holding signals d10-d13 based on each of the gradation data DP0-DP3 are output to current generation section 20z.
The current generation section 20z, for example, which is the same as current generation section 20A in the first embodiment of the current generation circuit mentioned above, supplies the light generation drive which is acquired and integrated and then selects only the specified gradation currents from a plurality of gradation currents that have a current value of a predetermined ratio. The specified gradation currents are then generated based on reference current Iref according to a signal level of above-mentioned holding signals d10-d13 to the organic EL devices OEL via the current output contact OUTi (In this embodiment, the light generation drive current flows so it is drawn in the direction of the pixel driver circuits DCz from the organic EL devices OEL side).
Accordingly, the light generation drive current according to the display data d0-d3 (gradation data DP0-DP3) flows in the forward-bias direction into the organic EL devices OEL, and the organic EL devices OEL emit light by predetermined luminosity gradation.
<<Data Driver>>
The data driver 130H, for example, the shift register circuit 131E has a configuration equivalent to the embodiment mentioned above as shown in
<<Drive Control Method>>
Next, the operation of the display device which has the configuration mentioned above will be explained with reference to the drawings.
First, the drive control operation in the data driver 130H, as shown in
Here, the display data holding operation takes in sequentially the display data d0-d3 which shifts in response to each line of the display pixels EP in each of the above-mentioned latch sections LD1, LD2, LD3, . . . based on the shift signals SRI, SR2, SR3, . . . output sequentially from the shift register circuit 131E and the holding operation is continuously performed in one line periods.
Furthermore, in the gradation data supply operation, the signal line groups DLz are supplied collectively via each of the switches SW1, SW2, SW3, . . . by using the display data d0-d3 as the gradation data DP0-DP3 held at each of the above-mentioned latch sections LD1, LD2, LD3, . . . based on the output enable signal WE output from the system controller 150. Here, the gradation data supply operation in the display panel 110E is set up to synchronize with the applied timing of the scanning signal Vsel which selects the display pixels EP of a specified line. Thus, in this embodiment, the gradation data DP0-DP3 (digital signals) based on the display data d0-d3 which consist of a plurality of digital signal bits is supplied to the direct presentation pixels (pixel driver circuits DCz) via each of the signal line clusters DLz arranged in the display panel 110E from the data driver 130H.
In the drive control operation in the display panel 110E (display pixels EP), as shown in
Moreover, as mentioned above, based on the reference current Iref and the holding signals DP10O-DP13, the current generation section 20z generates the light generation drive current according to the display data d0-d3 (gradation data DP0-DP3) and supplies the current to the organic EL devices OEL. Accordingly, the organic EL devices OEL emit light by predetermined luminosity gradation.
Also, the display panel 110E (pixel driver circuits DCz) related to this embodiment, as shown in
Sequential execution of a series of the above drive control operations is performed on each and every line that forms the display panel 110E. Furthermore, the light generation operation (supply operation of the light generation drive current) of the organic EL devices OEL of each line is continuously held by the pixel driver circuits DCz until the next scanning signal Vsel is applied.
Therefore, set to the display device 100C related to this embodiment, via each of the signal line groups DLz arranged in the display panel 110E from the data driver 130H, the gradation data DP0-DP3 consisting of a plurality of digital signal bits corresponding to the display data d0-d3 are directly supplied directly to the display pixels EP (pixel driver circuits), and set to the pixel driver circuits. Because the light generation drive current consists of an analog signal generated based on the reference current Iref supplied via a common reference current supply line Ls from a current generator IR (current composed of reference current Iref that is equally divided by the relevant number of write-in current generation circuits), as compared with a configuration which supplies write-in current that constitutes the display pixels EP from analog current and used abundantly in conventional technology, as well as the effects of signal level degradation, external noise and the like all can be markedly improved upon to offset these negative influences. As a direct result of this invention, the signal-to-noise (S/N) ratio can be improved, the light generation operation of the organic EL devices (light emitting elements) can also be accomplished by the appropriate luminosity gradation corresponding to the display data, and enhancement in the display image quality can be achieved as well.
In addition to the embodiment and circumstances which were mentioned above, regarding the signal lines relevant to the light generation operation in the display pixels, because it does not have a configuration which flows an analog signal that changes signal levels, this alleviates the limitation on the operating speed resulting from the charge and discharge operation of the signal lines, as well as enhancing the display response characteristics in the display device comprising the data driver to achieve remarkable display image quality.
In the embodiment mentioned above concerning the display pixels EP, despite the fact the configuration corresponding to the current sinking method flows the light generation drive current generated by the pixel driver circuits DCz in the direction drawn from the organic EL devices OEL side, this invention is not limited to this applies to the configuration shown in
Subsequently, another example of the configuration in the display device concerning this embodiment will be explained.
In the above, where the configuration of the first or the second embodiment of the current generation circuit mentioned above were applied to the pixel driver circuits DCz or DCz′ and explained. However, this invention is not restricted to this and can be applied to the configuration in the third or fourth embodiment of the current generation circuit stated above to the pixel driver circuits DCz or DCz′ as other examples of the configuration. When the display data constitutes a specified value, the circuit can be equipped with the organic EL devices OEL (optical elements) which are configured to supply a specified voltage Vbk (black display voltage) or a specified voltage Vr (reset voltage) the same as the fourth through eighth embodiments of the data driver mentioned above. These example display device and pixel driver circuit configurations are shown in
Specifically, the display panel 110E′ as shown in
In each embodiment mentioned above which applied a 4-bit digital signal for the display data, while the case example performed the display operation of 24=16 gradations, needless to say this invention is not restricted to this and can be applied to an image display of many more gradations.
Furthermore, though in the case explained where the current generation circuit related to this invention was applied to the data driver or the pixel driver circuits of the display device in the embodiment mentioned above, the present invention is not limited to such an example of application. For example, such as a printer head arranged and formed with a lot of light emitting elements. By supplying current which has a predetermined current value, this invention also can be applied advantageously to a driver circuit of a device comprising multifunctional elements which operates in a state of predetermined drive according to that current value.
<<The Configuration of the Field-Effect Transistors>>
Next, the configuration of the Thin-Film Field-Effect Transistors applicable to the current generation circuit related to this invention, and the pixel driver circuit formed in the display panel of the display device will be explained.
Each of the write-in current generation circuits which forms the data driver in each of the embodiments mentioned above (current generation circuits) or set to a pixel driver circuit (current generation section) which forms the display panel, for example, as shown in
Here, the dashed lines in
Therefore, the favorable saturation characteristics of the drain current (voltage-current characteristic) are no longer acquired according to the increased phenomenon of the drain current by such kink phenomenon, and set in a current mirror circuit. In a current generation circuit which requires the ratio of the current value of the gradation current to reference current for the desired design value. That is, the embodiments mentioned above are not set up as the ratio of the channel width of the transistor, and the current values of the write-in current and luminescent drive current at the time of a light generation operation differ in the transistor for the luminescent drive. Therefore, light generation operation in each of the display pixels may be performed by the suitable luminosity gradation based on the display data, and degradation of the display image quality may be caused.
Hereinafter, the transistor for the light drive in the pixel circuits DCy will be explained. Accordingly, explanation will also refer to the pixel driver circuit DCy shown in
Conversely, at the time of light generation operation, because the Pch transistor Tr81 performs and “ON” operation and the Nch transistors Tr82 and Tr84 perform and “OFF” operation, by applying the scanning signal Vsel of a low-level to the scanning lines SL, the light generation drive current flows into the organic EL devices OEL via the Pch transistors Tr81 and Tr83 from the high potential voltage connected to the voltage contact +V. Since the Nch transistor Tr84 is in an “OFF” state at this point, the gate voltage (potential of contact Nyb) of the Pch transistor Tr83 will be in a floating condition. As for the voltage between the gate-source of the Pch transistor Tr83, the potential at the time of the write-in operation ahead of the scanning signal Vsel switches over and is held as the electric charge accumulated in capacitor Cy at the time of the above-mentioned write-in operation. Therefore, as shown in
However, when it has the characteristics in which the drain current −(Ids) increases gradually as the voltage-current characteristic of Pch transistor Tr83 shown in
Then, in this embodiment, in order to control the kink phenomenon which was mentioned above, the present invention configuration applies Thin-Film Transistors (TFTs) which have at least the so-called body terminal configuration, whereby the body region and source region of SOI type Field-Effect Transistors are electrically connected to reference current transistors in current generation circuits, and gradation current transistors together with transistors for light generation drive in pixel driver circuits.
<<Body Terminal Configuration>>
Here, a Pch (p-channel type) transistor which has a body terminal configuration will be described in detail.
Here,
Needless to say, the Field-Effect Transistor that has the body terminal structure shown here may have other transistor structures that have the device characteristics illustrated in the example applications of the current generation circuits or the display device disclosed in this invention, but have equivalent component characteristics.
A Pch (p-channel type) Thin-Film Transistor which has the body terminal configuration as shown in
Additionally, on the upper part the active layer Rac, as shown in
Although a Pch type Thin-Film Transistor which has a body terminal configuration mentioned above was explained, an Nch type Thin-Film Transistor which has a body terminal configuration equipped as shown in
When verified using a basic circuit as shown in
This is because generation of the kink phenomenon is controlled as the minority carrier (An Nch>n-channel type transistor with an electron deficiency or hole and a Pch>p-channel type transistor electron) flows into the source region RS via the body terminal electrode EB in the electron and electron hole pairs produced near the boundary of the channel region Rchn and the drain region RD as mentioned above, thus the accumulation to the channel region Rchn is controlled and the decrease in the threshold voltage of a Field-Effect Transistor is alleviated.
Therefore, according to the present invention, the solution is to apply Field-Effect Transistors which have such a voltage-current characteristic to the transistors for light generation drive in the current mirror circuits of the current generation sections in each of the embodiments mentioned above, as well as the pixel driver circuits. Particularly, when configured in the current generation circuits, the data driver of the display devices, the display panels and the like related to this invention, because the write-in current and light generation drive current have a suitable current value corresponding to the current held based on the display data or gradation data are generable. Thus, the light generation operation in each of the display pixels can be performed by a suitable luminosity gradation based on the display data and enhancement in the display image quality can be achieved.
While the present invention has been described with reference to the preferred embodiments, it is intended that the invention be not limited by any of the details of the description thereof.
As this invention may be embodied in several forms without departing from the spirit of the essential characteristics thereof, the present embodiments are therefore illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by the description preceding them, and all changes that fall within meets and bounds of the claims, or equivalence of such meets and bounds thereof are intended to be embraced by the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2002-317225 | Oct 2002 | JP | national |
| 2002-345876 | Nov 2002 | JP | national |
| 2003-103871 | Apr 2003 | JP | national |
| 2003-170376 | Jun 2003 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP03/13819 | 10/29/2003 | WO | 4/27/2005 |
