Patent Grant
9437154
The present invention relates to a display device including a plurality of data signal line drive circuits and a method for driving such a display device.
In recent years, thin, lightweight, and low-power-consumption display devices such as liquid crystal display devices have been actively used. These display devices have been mounted prominently in mobile phones, smartphones, or laptop personal computers. Further, it is expected that in the future, there will be rapid advancements in the development and spread of electronic paper, which is a thinner display device. Under such circumstances, the current common issue is to reduce amounts of electric power that are consumed by various display devices and costs of these display devices.
Patent Literature 1 discloses a liquid crystal display device that achieves low power consumption and low cost through a reduction in the number of inputs of an LCD driver.
As shown in
Patent Literature 1
Japanese Patent Application Publication, Tokukai, No. 2001-174843 A (Publication Date: Jun. 29, 2001)
However, in the case of an abnormality in an input voltage that is inputted to a data signal line drive circuit (source driver IC 20 of
The present invention has been made in view of the foregoing problems, and it is an object of the present invention to provide: a display device including a plurality of data signal line drive circuits all of which can be safely stopped in the case of an abnormality in an input voltage that is inputted to a data signal line drive circuit or in a drive voltage that is needed for a data signal line drive circuit to be driven; and a method for driving such a display device.
In order to solve the foregoing problems, a display device according to the present invention is a display device including a plurality of data signal line drive circuits, including: voltage generating means, provided for each of the plurality of data signal line drive circuit, for generating, in accordance with an external voltage inputted from an outside source, a drive voltage that is needed for the data signal line drive circuit to be driven; and voltage determining means, provided for each of the plurality of data signal line drive circuit, for determining whether or not a voltage level of at least either the external voltage or the drive voltage falls within a predetermined range of allowable voltages, in a case where it has been determined, in at least one of the plurality of voltage determining means, that the voltage level does not fall within the range of allowable voltages, operation of the voltage generating means corresponding to all of the data signal line drive circuits being stopped.
It should be noted here that the voltage determining means may be configured (1) to include both a determination circuit that detects (determines) a reduction or rise in the external voltage and a determination circuit that detects (determines) a reduction or rise in the drive voltage and detect (determine) an abnormality in either the external voltage or the drive voltage or abnormalities in both the external voltage and the drive voltage, (2) to include only a determination circuit that detects (determines) a reduction or rise in the external voltage and detect (determine) an abnormality in the external voltage, or (3) to include only a determination circuit that detects (determines) a reduction or rise in the drive voltage and detect (determine) an abnormality in the drive voltage.
With the foregoing configuration, the operation of the voltage generating means in all of the data signal line drive circuits is stopped in the case of an abnormality (voltage reduction or voltage rise) in either the external voltage or the drive voltage in a data signal line drive circuit. That is, all of the data signal line drive circuits can be safely stopped. This prevents the external voltage A from continuing to be supplied to a normal data signal line drive circuit and the drive voltage from continuing to be generated as has conventionally been the case, thereby preventing problems such as heating and fuming.
In order to solve the foregoing problems, a method for driving a display device according to the present invention is a method for driving a display device including a plurality of data signal line drive circuits, including: a voltage generating step of, for each of the plurality of data signal line drive circuits, generating, in accordance with an external voltage inputted from an outside source, a drive voltage that is needed for that data signal line drive circuit to be driven; and a voltage determining step of, for each of the plurality of data signal line drive circuits, determining whether or not a voltage level of at least either the external voltage or the drive voltage falls within a predetermined range of allowable voltages, in a case where it has been determined, in at least one of the plurality of data signal line drive circuits, that the voltage level does not fall within the range of allowable voltages, operation of the voltage generating step in all of the data signal line drive circuits being stopped.
The foregoing method brings about effects that are brought about by the configuration of the foregoing display device.
As described above, the display device according to the present invention is configured such that in a case where it has been determined, in at least one of the plurality of voltage determining means, that the voltage level does not fall within the range of allowable voltages, operation of the voltage generating means corresponding to all of the data signal line drive circuits is stopped.
Further, the method for driving a display device according to the present invention is arranged such that in a case where it has been determined, in at least one of the plurality of data signal line drive circuits, that the voltage level does not fall within the range of allowable voltages, operation of the voltage generating step in all of the data signal line drive circuits is stopped.
This makes it possible to safely stop all of the data signal line drive circuits in the case of an abnormality in an external voltage that is inputted to a data signal line drive circuit or in a drive voltage that is needed for a data signal line drive circuit to be driven.
Schematically, a display device of the present invention includes a plurality of data signal line drive circuits, and is configured such that the operation of voltage generation circuits in all of the data signal line drive circuits is stopped, for example, in a case where the voltage level of at least either an external voltage inputted from an outside source to a data signal line drive circuit or a drive voltage generated for driving the data signal line drive circuit no longer falls within a predetermined range of allowable voltages.
Embodiments of display devices thus configured are described below with reference to the drawings.
First, a configuration of a display device (liquid crystal display device) 1 according to Embodiment 1 is described with reference to
The display panel 2 includes: a screen composed of a plurality of pixels arranged in an matrix manner; N (where N is a given integer) scan signal lines G (gate lines) that are selected line-sequentially so that the screen is scanned; and M (where M is a given integer) data signal lines S (source lines via each of which a data signal is supplied to a single row of pixels included in a selected one of the gate lines. The scan signal lines G and the data signal lines S intersect at right angles to each other. Provided at each of the intersections between the scan signal lines G and the data signal lines S is a transistor (thin-film transistor, TFT) having its gate electrode connected to its corresponding one of the scan signal lines G, its source electrode connected to its corresponding one of the data signal lines S, and its drain electrode connected to a pixel electrode.
In
The scan signal line drive circuit 4 scans the scan signal lines G line-sequentially from top to bottom of the screen. In so doing, the scan line drive circuit 4 outputs, to each of the scan signal lines G, a rectangular wave for turning on the transistors provided in the pixels and connected to the pixel electrodes. This brings a single row of pixels in the screen into a selected state.
The timing controller 10 receives sync signals (a clock signal Dotclk, a vertical sync signal Vsync, and a horizontal sync signal Hsyn) from an external control section, generates, in accordance with these sync signals, signals on the basis of which the circuits operate in sync with one another, and outputs the signals thus generated to the circuits. Specifically, the timing controller 10 outputs a gate start pulse signal and a gate clock signal to the scan signal line drive circuit 4, and outputs a source start pulse signal, a source latch strobe signal, and a source clock signal to the data signal line drive circuit 6. Further, the timing controller 10 receives, from the external control section, a digital video signal (picture signal) representing an image to be displayed, generates a digital image signal as a signal that causes a display section to display the image represented by the picture signal, and outputs the digital image signal to the data signal line drive circuit 6.
The data signal line drive circuit 6 computes, from the digital image signal inputted thereto, the values of voltages to be outputted to a single row of pixels selected and outputs voltages (image data) of these values to the data signal lines S, respectively. This causes the image data to be supplied to the pixels on a selected one of the scan signal lines G.
The display device 1 includes a common electrode (not illustrated) provided to each pixel in the screen. The common electrode drive circuit 8 receives a signal from the timing controller 10, generates, in accordance with the signal, a predetermined common voltage for driving the common electrode, and outputs the predetermined common voltage to the common electrode.
Upon receiving the gate start pulse signal from the timing controller 10, the scan signal line drive circuit 4 starts scanning the display panel 2 and applies selection voltages to the scan signal lines G in sequence in accordance with the gate clock signal. Upon receiving the source start pulse signal from the timing controller 10, the data signal line drive circuit 6 stores the image data in a register for each pixel in accordance with the source clock signal and writes the image data to the data signal lines S of the display panel 2 in accordance with the source latch strobe signal that follows.
The external control section is provided with a power supply section (not illustrated) from which voltages that are need for the circuits in the display device 1 to operate are supplied. That is, the display device 1 is supplied with a so-called analog power-supply voltage (hereinafter referred to as “external voltage A”) and a so-called logic power-supply voltage (hereinafter referred to as “external voltage B”) from the power supply section. A external voltage A serves as a source of generation of a power-supply voltage that is needed in the data signal line drive circuit, and an external voltage B is used for processing in a control circuit in the data signal line drive circuit. It should be noted, however, that an external voltage B may be generated in the display device in accordance with an external voltage A supplied from the control section. Therefore, for convenience of explanation,
(Configuration of the Data Signal Line Drive Circuit 6)
The data signal line drive circuit 6 includes a plurality of data signal line drive circuits 6a, 6b, 6c, . . . , and each of the data signal line drive circuits 6a, 6b, 6c, . . . are provided for a plurality of data signal lines. For example, in a case where the display device 1 is provided with three data signal line drive circuits 6a, 6b, and 6c, M/3 out of the M data signal lines are connected to each of the data signal line drive circuits 6a, 6b, and 6c. Each of the data signal line drive circuits 6a, 6b, and 6c can be driven separately.
A case is described here where the display device 1 is provided with three data signal line drive circuits 6a, 6b, and 6c. Further, since the data signal line drive circuits 6a, 6b, and 6c are identical in configuration to one another, the case is described by taking the data signal line drive circuit 6a as a main example.
As shown in
The voltage generation circuit 61a receives an external voltage A inputted from the power supply section of the external control section and generates, in accordance with the external voltage A, a voltage (drive voltage) that is necessary for the output amplifier circuit 62a. For example, the voltage generation circuit 61a receives an external voltage A of 3.3 V and generates a drive voltage of 5.0 V. The drive voltage thus generated is inputted to the output amplifier circuit 62a and the voltage determination circuit 63a. It should be noted that among drive voltages that are generated in the voltage generation circuit 61a are gate voltages (Vgh, Vgl) that are used in the scan signal line drive circuit 4.
The output amplifier circuit 62a includes a plurality of analog amplifier blocks (not illustrated) each of which is connected to a data signal line S and supplies a data signal to that data signal line S.
The voltage determination circuit 63a receives the external voltage A inputted from the power supply section of the external control section and the drive voltage generated in the voltage generation circuit 61a. Then, the voltage determination circuit 63a performs a process (first determination process) of determining, by comparing the external voltage A with a predetermined first range of allowable voltages, whether or not the external voltage A falls within the first range of allowable voltages. Further, the voltage determination circuit 63a performs a process (second determination process) of determining, by comparing the drive voltage with a predetermined second range of allowable voltages, whether or not the drive voltage falls within the second range of allowable voltages.
The voltage determination circuit 63a includes a first determination circuit h1 (see
(1) to include both the first determination circuit h1 and the second determination circuit h2 when configured to detect (determine) an abnormality in either the external voltage A or the drive voltage or abnormalities in both the external voltage A and the drive voltage;
(2) to include only the first determination circuit h1 when configured to detect (determine) an abnormality in the external voltage A alone; or
(3) to include only the second determination circuit h2 when configured to detect (determine) an abnormality in the drive voltage alone.
The following explains the aforementioned case (1), where the voltage determination circuit 63a is configured to include both the first determination circuit h1 and the second determination circuit h2 and detect (determine) an abnormality in either the external voltage A or the drive voltage or abnormalities in both the external voltage A and the drive voltage.
The display device 1 thus configured makes it possible to detect an abnormality in power-supply voltage in the data signal line drive circuit 6a. The voltage determination circuit 63a will be described in detail later. It should be noted that the first range of allowable voltages and the second range of allowable voltages each separately have its lower and upper limits (low-limit and upper-limit voltage levels) set. That is, the external voltage A is determined as normal when its voltage level falls within a range from a first lower limit to a first upper limit (first range of allowable voltages), and is determined as abnormal when its voltage level is out of the first range of allowable voltages. Further, the drive voltage is determined as normal when its voltage level falls within a range from a second lower limit to a second upper limit (second range of allowable voltages), and is determined as abnormal when its voltage level is out of the second range of allowable voltages.
Possible examples of abnormalities in power-supply voltage here include: an abnormality due a reduction in the external voltage A in the case of battery driving; an abnormality due to a reduction or rise in the external voltage A or in the drive voltage due to passage of a large electric current in the case of a short in each drive circuit and in an internal circuit of the display panel; etc.
Upon detecting such an abnormality in power-supply voltage, i.e., in a case where at least either the external voltage A or the drive voltage no longer falls within its corresponding range of allowable voltage (first range of allowable voltages, second range of allowable voltages), the voltage determination circuit 63a transmits a result of determination to that effect to the safety control circuit 64a.
The safety control circuit 64a performs a process of controlling how the voltage generation circuit 61a and the output amplifier circuit 62a are driven. Upon receiving the result of determination from the voltage determination circuit 63a, the safety control circuit 64a outputs, to the voltage generation circuit 61a and the output amplifier circuit 62a, stop signal information corresponding to a drive-stopping command. Upon receiving the stop signal information, the voltage generation circuit 61a stops the operation of generating a drive voltage and the operation of outputting the drive voltage thus generated. Upon receiving the stop signal information, the output amplifier circuit 62a stops the operation of outputting a data signal to a data signal line S.
Further, upon receiving the result of determination from the voltage determination circuit 63a, the safety control circuit 64a further transmits, to the timing controller 10, stop-starting information for starting a stopping process of stopping the operation of the voltage generation circuits 61b and 61c and the output amplifier circuits 62b and 62c in the data signal line drive circuits 6b and 6c.
The timing controller 10 includes a drive control section 11 that controls the operation of each of the data signal line drive circuits 6a, 6b, and 6c. Upon receiving the stop-starting information from the safety control circuit 64a, the drive control section 11 outputs stop signal information for stopping the operation of the voltage generation circuits 61b and 61c and the output amplifier circuits 62b and 62c in the data signal line drive circuits 6b and 6c.
Upon receiving the stop signal information from the drive control section 11, the safety control circuit 64b of the data signal line drive circuit 6b outputs the stop signal information to the voltage generation circuit 61b and to the output amplifier circuit 62b. Upon receiving the stop signal information, the voltage generation circuit 61b stops the operation of generating a drive voltage and the operation of outputting the drive voltage thus generated. Upon receiving the stop signal information, the output amplifier circuit 62b stops the operation of outputting a data signal to a data signal line S.
Similarly, upon receiving the stop signal information from the drive control section 11, the safety control circuit 64c of the data signal line drive circuit 6c outputs the stop signal information to the voltage generation circuit 61c and to the output amplifier circuit 62c. Upon receiving the stop signal information, the voltage generation circuit 61c stops the operation of generating a drive voltage and the operation of outputting the drive voltage thus generated. Upon receiving the stop signal information, the output amplifier circuit 62c stops the operation of outputting a data signal to a data signal line S.
With this configuration of the display device 1, the operation of the voltage generation circuits and the output amplifier circuits in all of the data signal line drive circuits is stopped in the case of an abnormality (voltage reduction or voltage rise) in either the external voltage A or the drive voltage in a data signal line drive circuit. This prevents the external voltage A from continuing to be supplied to a normal data signal line drive circuit and the drive voltage from continuing to be generated as has conventionally been the case, thereby preventing problems such as heating and fuming.
It should be noted that the display device 1 may be configured such that the operation of only the voltage generation circuits is stopped in the case of such an abnormality in voltage. This makes it possible to stop the operation of the data signal line drive circuits by stopping the operation of at least the voltage generation circuits, and to simplify the circuit configuration.
In stopping both the voltage generation circuits and the output amplifier circuits, it is preferable, for the sake of safety, to stop the output amplifier circuits first and then stop the voltage generation circuits.
Further, instead of being limited to being configured, as described above, such that each of the voltage generation circuits provided in the respective data signal line drive circuits and each of the voltage determination circuits provided in the respective data signal line drive circuits perform a voltage generation process and a voltage determination process separately, the display device 1 may alternatively be configured such that at least two of all of the voltage generation circuits perform the voltage generation process and at least two of all of the voltage determination circuits perform the voltage determination process. That is, there may be a data signal line drive circuit configured not to perform the voltage generation process or the voltage determination process. This makes it possible to achieve lower power consumption.
(Configuration of the Control Circuit)
A configuration of the control circuit 60a is specifically described with reference to
The voltage determination circuit 63a includes: the first determination circuit h1, which is composed of a first comparison circuit c1; the second determination circuit h2, which is composed of a second comparison circuit c2; and a logic circuit (AND circuit). The first comparison circuit c1 has a terminal to which the external voltage A is inputted and a terminal to which the first lower limit is inputted, and the second comparison circuit c2 has a terminal to which the drive voltage is inputted and a terminal to which the second lower limit is inputted. The first comparison circuit c1 and the second comparison circuit c2 have their outputs inputted to input terminals s1 and s2 of the AND circuit, respectively.
The first comparison circuit c1 outputs a High-level signal (H level; “1”) in a case where the external voltage A exceeds the first lower limit, and outputs a Low-level signal (L level; “0”) in a case where the external voltage A falls below the first lower limit. It should be noted that the first comparison circuit c1 may be configured to output a L level (“0”) in a case where the external voltage A continues to be below the first lower limit for a predetermined period of time.
The second comparison circuit c2 outputs a High-level signal (H level; “1”) in a case where the drive voltage exceeds the second lower limit, and outputs a Low-level signal (L level; “0”) in a case where the drive voltage falls below the second lower limit. It should be noted that the second comparison circuit c2 may be configured to output a L level (“0”) in a case where the drive voltage continues to be below the second lower limit for a predetermined period of time.
Since the first comparison circuit c1 and the second comparison circuit c2 have their outputs inputted to the input terminals s1 and s2 of the AND circuit, respectively, the AND circuit has its output at a H level (“1”) in a case where both the external voltage A and the drive voltage exceed their corresponding lower limits (i.e., in a case where H levels (“1”) are outputted) and the AND circuit has its output at a L level (“0”) in a case where at least either the external voltage A or the drive voltage falls below its corresponding lower limit (i.e., in a case where a H level (“0”) is outputted), as shown in a truth table of
As just described, the voltage determination circuit 63a determines whether or not the voltage level of at least either the external voltage A or the drive voltage falls below a preset lower limit, and outputs a result of the determination (H level (“1”) or L level (“0”)).
As shown in
Furthermore, as shown in
As soon as the safety control circuit 64b of the data signal line drive circuit 6b receives the stop signal information from the drive control section 11 of the timing controller 10, the voltage generation circuit drive control section d1 (not illustrated) in the safety control circuit 64b causes the voltage generation circuit 61b to stop the operation of generating a drive voltage and the operation of outputting the drive voltage thus generated, and the output amplifier circuit drive control section d2 (not illustrated) in the safety control circuit 64b causes the output amplifier circuit 62b to stop the operation of outputting a data signal to a data signal line S.
Similarly, as soon as the safety control circuit 64c of the data signal line drive circuit 6c receives the stop signal information from the drive control section 11 of the timing controller 10, the voltage generation circuit drive control section d1 (not illustrated) in the safety control circuit 64c causes the voltage generation circuit 61c to stop the operation of generating a drive voltage and the operation of outputting the drive voltage thus generated, and the output amplifier circuit drive control section d2 (not illustrated) in the safety control circuit 64c causes the output amplifier circuit 62c to stop the operation of outputting a data signal to a data signal line S.
It should be noted that the drive control section 11 of the timing controller 10 may be configured to also output the stop signal information to the safety control circuit 64a of the data signal line drive circuit 6a. By performing the drive-stopping operation based on the stop signal information from the timing controller 10 in addition to the drive-stopping operation based on a result of determination from the voltage determination circuit 63a, the safety control circuit 64a can surely execute the stopping process.
This configuration makes it possible, in a case where the voltage level of at least either the external voltage A or the drive voltage in a data signal line drive circuit falls below its corresponding lower limit (first lower limit, second lower limit), to stop the operation of the voltage generation circuits and the output amplifier circuits in the other data signal line drive circuits.
It should be noted here that by causing the “first lower limit” and the “second lower limit” of
Alternatively, a configuration in which it is determined whether or not the voltage level of at least either the external voltage A or the drive voltage falls within its corresponding range of allowable voltages (first range of allowable voltages, second range of allowable voltages) can be achieved by configuring the control circuit 60a as shown, for example, in
The voltage determination circuit 63a of
The first lower-limit comparison circuit c11 has a terminal to which the external voltage A is inputted and a terminal to which the first lower limit is inputted, and the first upper-limit comparison circuit c12 has a terminal to which the external voltage A is inputted and a terminal to which the first upper limit is inputted. The second lower-limit comparison circuit c21 has a terminal to which the drive voltage is inputted and a terminal to which the second lower limit is inputted, and the second upper-limit comparison circuit c22 has a terminal to which the drive voltage is inputted and a terminal to which the second upper limit is inputted. The first lower-limit comparison circuit c11 and the first upper-limit comparison circuit c12 have their outputs inputted to input terminals s1 and s2 of the first AND circuit r1, respectively, and the second lower-limit comparison circuit c21 and the second upper-limit comparison circuit c22 have their outputs inputted to input terminals s1 and s2 of the second AND circuit r2, respectively. The first AND circuit r1 and the second AND circuit r2 have their outputs inputted to input terminals s1 and s2 of the third AND circuit r3, and the third AND circuit r3 has its output inputted to the safety control circuit 64a.
The first lower-limit comparison circuit c11 outputs a High-level signal (H level; “1”) in a case (normal) where the external voltage A exceeds the first lower limit, and outputs a Low-level signal (L level; “0”) in a case (abnormal) where the external voltage A falls below the first lower limit; the first upper-limit comparison circuit c12 outputs a High-level signal (H level; “1”) in a case (normal) where the external voltage A falls below the first upper limit, and outputs a Low-level signal (L level; “0”) in a case (abnormal) where the external voltage A exceeds the first upper limit. Similarly, the second lower-limit comparison circuit c21 outputs a High-level signal (H level; “1”) in a case (normal) where the drive voltage exceeds the second lower limit, and outputs a Low-level signal (L level; “0”) in a case (abnormal) where the drive voltage falls below the second lower limit; the second upper-limit comparison circuit c22 outputs a High-level signal (H level; “1”) in a case (normal) where the drive voltage falls below the second upper limit, and outputs a Low-level signal (L level; “0”) in a case (abnormal) where the drive voltage exceeds the second upper limit.
The configuration of
The following describes modifications of the display device 1. It should be noted that the following describes points of difference from the display device 1 shown in
(Modification 1)
(Modification 2)
Alternatively, the display device 1 according to Modification 2 may be configured such that the voltage determination circuits 63a, 63b, and 63c are provided inside of the control circuits 60a, 60b, and 60c in the data signal line drive circuits 6a, 6b, and 6c, respectively, and the safety control circuits 64a, 64b, and 64c are provided outside of the data signal line drive circuits 6a, 6b, and 6c, respectively.
(Modification 3)
(Modification 4)
This configuration makes it possible to reduce the data signal line drive circuits 6a, 6b, and 6c in size. It should be noted that the voltage generation circuits 61a, 61b, and 61c may be provided outside of the display device 1, e.g., on a substrate on which the control section (
(Modification 5)
(Configuration of a Voltage Generation Circuit)
It should be noted that in the display device 1 according to Modification 4 as shown in
A configuration of a display device (liquid crystal display device) 1a according to Embodiment 2 of the present invention is described below. It should be noted that the following describes points of difference from the display device 1 according to Embodiment 1, and components having the same functions as those of the components described in Embodiment 1 are given the same reference signs, and as such, are not described below.
The data signal line drive circuit 6 includes a plurality of data signal line drive circuits 6a, 6b, 6c, . . . , and each of the data signal line drive circuits 6a, 6b, 6c, . . . are provided for a plurality of data signal lines. In Embodiment 2, too, a case is described where the display device 1 is provided with three data signal line drive circuits 6a, 6b, and 6c. Further, since the data signal line drive circuits 6a, 6b, and 6c are identical in configuration to one another, the case is described by taking the data signal line drive circuit 6a as a main example.
The data signal line drive circuit 6a includes a voltage generation circuit 61a, an output amplifier circuit 62a, and a control circuit 60a, and the control circuit 60a includes a voltage determination circuit 63a and a safety control circuit 64a.
The voltage generation circuit 61a receives an external voltage A inputted from the power supply section (not illustrated) of the external control section and generates, in accordance with the external voltage A, a drive voltage that is necessary for the output amplifier circuit 62a. The drive voltage thus generated is inputted to the output amplifier circuit 62a and the voltage determination circuit 63a.
The output amplifier circuit 62a includes a plurality of analog amplifier blocks (not illustrated) each of which is connected to a data signal line S and supplies a data signal to that data signal line S.
The voltage determination circuit 63a receives the external voltage A inputted from the power supply section of the external control section and the drive voltage generated in the voltage generation circuit 61a. Then, the voltage determination circuit 63a performs a process (first determination process) of determining, by comparing the external voltage A with a predetermined first range of allowable voltages, whether or not the external voltage A falls within the first range of allowable voltages. Further, the voltage determination circuit 63a performs a process (second determination process) of determining, by comparing the drive voltage with a predetermined second range of allowable voltages, whether or not the drive voltage falls within the second range of allowable voltages. This makes it possible to detect an abnormality in power-supply voltage in the data signal line drive circuit 6a. Upon detecting an abnormality in power-supply voltage, i.e., in a case where at least either the external voltage A or the drive voltage no longer falls within its corresponding range of allowable voltage (first range of allowable voltages, second range of allowable voltages), the voltage determination circuit 63a transmits a result of determination to that effect to the safety control circuit 64a.
The safety control circuit 64a performs a process of controlling how the voltage generation circuit 61a and the output amplifier circuit 62a are driven. Upon receiving the result of determination from the voltage determination circuit 63a, the safety control circuit 64a outputs, to the voltage generation circuit 61a and the output amplifier circuit 62a, stop signal information corresponding to a drive-stopping command. Upon receiving the stop signal information, the voltage generation circuit 61a stops the operation of generating a drive voltage and the operation of outputting the drive voltage thus generated. Upon receiving the stop signal information, the output amplifier circuit 62a stops the operation of outputting a data signal to a data signal line S.
Further, upon receiving the result of determination from the voltage determination circuit 63a, the safety control circuit 64a further transmits, to the safety control circuits 64b and 64c of the data signal line drive circuits 6b and 6c, stop-starting information for starting a stopping process of stopping the operation of the voltage generation circuits 61b and 61c and the output amplifier circuits 62b and 62c.
Upon receiving the stop signal information from the safety control circuit 64a of the data signal line drive circuit 6a, the safety control circuit 64b of the data signal line drive circuit 6b outputs the stop signal information to the voltage generation circuit 61b and to the output amplifier circuit 62b. Upon receiving the stop signal information, the voltage generation circuit 61b stops the operation of generating a drive voltage and the operation of outputting the drive voltage thus generated. Upon receiving the stop signal information, the output amplifier circuit 62b stops the operation of outputting a data signal to a data signal line S.
Similarly, upon receiving the stop signal information from the safety control circuit 64a of the data signal line drive circuit 6a, the safety control circuit 64c of the data signal line drive circuit 6c outputs the stop signal information to the voltage generation circuit 61c and to the output amplifier circuit 62c. Upon receiving the stop signal information, the voltage generation circuit 61c stops the operation of generating a drive voltage and the operation of outputting the drive voltage thus generated. Upon receiving the stop signal information, the output amplifier circuit 62c stops the operation of outputting a data signal to a data signal line S.
With this configuration, the operation of the voltage generation circuits and the output amplifier circuits in all of the data signal line drive circuits is stopped in the case of an abnormality (voltage reduction or voltage rise) in either the external voltage A or the drive voltage in a data signal line drive circuit. This prevents the external voltage A from continuing to be supplied to a normal data signal line drive circuit and the drive voltage from continuing to be generated as has conventionally been the case, thereby preventing problems such as heating and fuming.
Further, the configuration of Embodiment 2, in which the operation of the voltage generation circuits and the output amplifier circuits in all of the data signal line drive circuits is stopped without using the timing controller 10, makes it possible to simplify the circuit configuration of the display device 1a.
It should be noted here that the display device 1a may be configured, as shown in Modifications 2 and 3, that the voltage determination circuits 63a, 63b, and 63c and the voltage generation circuits 61a, 61b, and 61c are provided outside of the data signal line drive circuits 6a, 6b, and 6c, respectively.
Further, a specific structure of the control circuit 60a is identical to that described in Embodiment 1.
(Modification 6)
Upon receiving the result of determination, the safety control circuits 64a, 64b, and 64c transmit stop signal information to their corresponding voltage generation circuits 61a, 61b, and 61c and to their corresponding output amplifier circuits 62a, 62b, and 62c, respectively. This causes the operation of the voltage generation circuits 61a, 61b, and 61c and the output amplifier circuits 62a, 62b, and 62c to be stopped.
(Display Panel)
In each of the embodiments described above, the display panel 2 is not limited to a particular configuration.
For example, in a case where the display panel 2 is a liquid crystal display panel, the display device 1 or 1a can be configured as a liquid crystal display device.
Alternatively, in a case where the display panel 2 is an EL display panel such as an organic electroluminescent (EL) display panel, the display device 1 or 1a can be configured as an electroluminescent display device.
(Transistor)
It is desirable, in each of the display devices according to the embodiments described above, that each transistor of the display panel be a TFT having its semiconductor layer made with an oxide semiconductor. Examples of such an oxide semiconductor include IGZO (InGaZnOx).
As shown in
For the reasons stated above, use of a TFT made with an oxide semiconductor in each pixel as a transistor for the display panel in each of the display devices according to the embodiments described above renders the on-state characteristic of the TFT in each pixel very good. This increases the electron mobility with which pixel data is written to each pixel, thus making it possible to shorten the time it takes for the pixel data to be written.
The display device according the embodiment of the present invention can be configured such that: the voltage determining means determines whether or not a voltage level of at least either the external voltage or the drive voltage falls below a lower-limit voltage level serving as a lower limit of the range of allowable voltages; and in a case where it has been determined, in at least one of the plurality of voltage determining means, that the voltage level falls below the lower-limit voltage level, operation of the voltage generating means corresponding to all of the data signal line drive circuits is stopped.
This makes it possible to safely stop all of the data signal line drive circuits in the case of an abnormal reduction in voltage level of either the external voltage or the drive voltage in a data signal line drive circuit.
The display device according the embodiment of the present invention can be configured such that: the voltage determining means determines whether or not a voltage level of at least either the external voltage or the drive voltage exceeds an upper-limit voltage level serving as an upper limit of the range of allowable voltages; and in a case where it has been determined, in at least one of the plurality of voltage determining means, that the voltage level exceeds the upper-limit voltage level, operation of the voltage generating means corresponding to all of the data signal line drive circuits is stopped.
This makes it possible to safely stop all of the data signal line drive circuits in the case of an abnormal rise in voltage level of either the external voltage or the drive voltage in a data signal line drive circuit.
The display device according the embodiment of the present invention can be configured such that: each of the plurality of data signal line drive circuits further comprises safety control means for controlling how the voltage generating means is driven; and upon receiving, from the voltage determining means, a result of determination indicating that the voltage level does not fall within the range of allowable voltages, the safety control means causes operation of the voltage generating means corresponding to the data signal line drive circuit in which that safety control means is provided to be stopped.
According to the foregoing configuration, the operation of the voltage generating means of a data signal line drive circuit suffering from such an abnormality in voltage is stopped in accordance an instruction given within the data signal line drive circuit. This makes it possible to immediately perform a stopping process on a data signal line drive circuit suffering from an abnormality.
The display device according the embodiment of the present invention can be configured to further include a timing controller that outputs a control signal for driving each of the plurality of data signal line drive circuits, wherein in accordance with the result of determination, the timing controller 10 outputs, to each of the safety control means of the plurality of data signal line drive circuits, stop signal information for stopping the operation of the voltage generating means.
According to the foregoing configuration, the operation of each of the voltage generating means is stopped in accordance with a stop instruction (stop signal information) from the timing controller that controls each of the data signal line drive circuits. This makes it possible to surely stop all of the voltage generating means.
The display device according the embodiment of the present invention can be configured such that: upon receiving the result of determination from the voltage determining means, the safety control means further transmits, to the timing controller, stop-starting information for starting a stopping process of stopping the operation of the voltage generating means corresponding to all of the data signal line drive circuits; and upon receiving the stop-starting information from the safety control means, the timing controller outputs stop signal information for stopping the operation of the voltage generating means corresponding to all of the data signal line drive circuits.
The display device according the embodiment of the present invention can be configured such that whereas that one of the safety control means which has received the result of determination from the voltage determining means causes the operation of the voltage generating means corresponding to the data signal line drive circuit in which that safety control means is provided to be stopped, that one of the safety control means which has received the stop signal information from the timing controller causes the operation of the voltage generating means corresponding to the data signal line drive circuit in which that safety control means is provided to be stopped.
The display device according the embodiment of the present invention can be configured to further include a timing controller that outputs a control signal for driving each of the plurality of data signal line drive circuits, wherein upon receiving the result of determination from the voltage determining means, the timing controller outputs, to each of the safety control means of the plurality of data signal line drive circuits, stop signal information for stopping the operation of the voltage generating means; and upon receiving the stop signal information from the timing controller, each of the safety control means of the plurality of data signal line drive circuits causes the operation of the voltage generating means corresponding to the data signal line drive circuit in which that safety control means is provided to be stopped.
The display device according the embodiment of the present invention can be configured such that: in a case where in at least one of the data signal line drive circuits the voltage level does not fall within the range of allowable voltages, the voltage determining means corresponding to that data signal line drive circuit transmits the result of determination to the safety control means of that data signal line drive circuit; and upon receiving the result of determination from the voltage generating means, the safety control means further transmits, to the safety control means of all of the other data signal line drive circuits, stop-starting information for starting a stopping process of stopping the operation of the voltage generating means corresponding to those data signal line drive circuits.
According to the foregoing configuration, the safety control means of a data signal line drive circuit suffering from such an abnormality in voltage transmits stop-starting information to the safety control means of the other data signal line drive circuits. That is, the stopping process is performed without using the timing controller. This makes it possible to simplify the circuit configuration of the display device.
The display device according the embodiment of the present invention can be configured such that upon receiving the stop-starting information from at least one of the safety control means of the plurality of data signal line drive circuits, each of the safety control means of the plurality of data signal line drive circuits causes the operation of the voltage generating means corresponding to the data signal line drive circuit in which that safety control means is provided to be stopped.
The display device according the embodiment of the present invention can be configured such that in a case where in at least one of the data signal line drive circuits the voltage level does not fall within the range of allowable voltages, the voltage determining means corresponding to that data signal line drive circuit transmits the result of determination to the safety control means of that data signal line drive circuit and to the safety control means of all of the other data signal line drive circuits.
The display device can be configured such that at least either the voltage determining means or the voltage generating means are provided inside or outside of the data signal line drive circuits.
The display device according the embodiment of the present invention can be configured such that: each of the plurality of data signal line drive circuits includes an amplifier circuit which receives the drive voltage and which supplies a data signal to its corresponding data signal line; and in case where the voltage level does not fall within the range of allowable voltages, operation of the amplifier circuits in all of the data signal line drive circuits is further stopped.
According to the foregoing configuration, the operation of the amplifier circuits as well as the voltage generation circuits is stopped in the case of such an abnormality in voltage. This makes it possible to prevent a failure or the like in an internal circuit of a data signal line drive circuit.
The display device according the embodiment of the present invention can be configured such that the range of allowable voltages is set separately for the external voltage and the drive voltage.
This makes it possible to appropriately determine (detect) an abnormality in voltage even in a case where the external voltage and the drive voltage are different.
The display device according the embodiment of the present invention can be configured such that in a case where it has been determined by the voltage determining means that the voltage level of at least either the external voltage or the drive voltage does not continues to be out of the range of allowable voltages for a predetermined period of time, the operation of the voltage generating means corresponding to all of the data signal line drive circuits is stopped.
The foregoing configuration makes it possible to perform an operation-stopping process in a case where an abnormality in voltage continues for a predetermined period of time, and to avoid performing an operation-stopping process in an essentially normal case, thus making it possible to enhance reliability.
The display device according the embodiment of the present invention is preferably configured to further include a display panel including data signal lines, scan signal lines, pixel electrodes, and transistors each connected to its corresponding one of the data signal lines, its corresponding one of the scan signal lines, and its corresponding one of the pixel electrodes, wherein each of the transistors has its semiconductor layer made with an oxide semiconductor.
The display device according the embodiment of the present invention is preferably configured such that the oxide semiconductor is IGZO.
The display device according the embodiment of the present invention can be a liquid crystal display device including a liquid crystal display panel or an organic EL display device including an organic electroluminescent display panel.
The present invention is not limited to the description of the embodiments above, but may be altered by a skilled person within the scope of the claims. An embodiment based on a proper combination of technical means disclosed in different embodiments is encompassed in the technical scope of the present invention.
A display device of the present invention is applicable to a display device including a plurality of data signal line drive circuits and to a method for driving such a display device.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2011-086817 | Apr 2011 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2012/059414 | 4/5/2012 | WO | 00 | 10/4/2013 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2012/137886 | 10/11/2012 | WO | A |
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