Patent Grant
12039928
The following disclosure relates to a display device and a method for driving the display device, and particularly to a method for driving a display device that adopts pause driving.
In recent years, an organic EL display device including pixel circuits each including an organic EL element has been put to practical use. The organic EL element is also called an organic light-emitting diode (OLED), and is a self-emissive display element that emits light at luminance determined based on a current flowing therethrough. As such, since the organic EL element is a self-emissive display element, the organic EL display device can easily achieve slimming down, a reduction in power consumption, an increase in luminance, etc., compared to a liquid crystal display device that requires a backlight, a color filter, and the like.
For the pixel circuit of the organic EL display device, typically, a thin-film transistor (TFT) is adopted as a drive transistor for controlling supply of a current to the organic EL element. However, variations are likely to occur in the characteristics of the thin-film transistor. Specifically, variations are likely to occur in threshold voltage. If variations in threshold voltage occur in the drive transistors provided in a display unit, then variations in luminance occur, degrading display quality. Hence, there are proposed various types of processes (compensation processes) for compensating for variations in threshold voltage.
For schemes for compensation processes, there are known an internal compensation scheme in which a compensation process is performed by providing, in a pixel circuit, a capacitor for holding information on a threshold voltage of a drive transistor; and an external compensation scheme in which a compensation process is performed by, for example, measuring, by a circuit provided external to a pixel circuit, the magnitude of a current flowing through a drive transistor under a predetermined condition, and correcting a video signal based on a result of the measurement.
As a pixel circuit of an organic EL display device that adopts the internal compensation scheme for a compensation process, there is known, for example, a pixel circuit 90 including one organic EL element 91, seven thin-film transistors T91 to T97, and one holding capacitor C9, such as that shown in
Now, how to set the voltage value of the low-level power supply voltage ELVSS will be described.
During the turn-off period 901, initialization of a voltage at the second node N2 (initialization of a gate voltage of the thin-film transistor T94 serving as a drive transistor), initialization of the voltage V(N3) at the third node N3 (initialization of the anode voltage of the organic EL element 91), and writing of a data voltage to the holding capacitor C9 are performed. As can be grasped from
During the light-emission period 902, the thin-film transistor T96 goes into on state, by which a current based on a target display gray level flows between the first conductive terminal and second conductive terminal of the thin-film transistor T94. Upon performing black display, the current flowing between the first conductive terminal and second conductive terminal of the thin-film transistor T94 is ideally 0, but in practice, leakage current flows between the first conductive terminal and second conductive terminal of the thin-film transistor T94. Therefore, as shown in
Hence, the voltage value of the low-level power supply voltage ELVSS is set such that the voltage V(N3) at the third node N3 does not become higher than the light-emission threshold voltage Ve of the organic EL element 91 upon performing black display (in other words, such that the voltage V(N3) at the third node N3 is less than or equal to the light-emission threshold voltage Ve of the organic EL element 91 at the end time of the light-emission period 902, as shown in a portion given reference character 93 in
Although in the example shown in
Meanwhile, in recent years, there has been an increasing demand for a reduction in power consumption of display devices. For a technique for achieving a reduction in power consumption, there is known a technique called “pause driving” in which a pause period during which the operation of writing data voltages to pixel circuits is stopped is provided. According to the pause driving, data voltages are written only during one frame period among a plurality of consecutive frame periods, and data voltages are not written during other periods. For example, data voltages are written only during one frame period among four consecutive frame periods.
In a display device developed in recent years that adopts such pause driving, switching is performed between normal driving (driving in which data voltages are written to pixel circuits every frame period) and pause driving. For example, when there is no change to display screen throughout a predetermined period, switching from normal driving to pause driving is performed, and when a user has performed some kind of operation or when data is transmitted from an external source, switching from pause driving to normal driving is performed. Thus, for example, as shown in
Note that in the following description, a period during which a data voltage is written to each pixel circuit regardless of whether it is a normal driving period or a pause driving period is referred to as “data write period” and a portion of a pause driving period during which a data voltage is not written to each pixel circuit is referred to as “pause period”. In addition, when a pause driving period is divided into periods each corresponding to the length of one frame period present during normal driving, a period during which data voltages are written is referred to as “refresh frame” and a period during which data voltages are not written is referred to as “pause frame”.
In a case in which the organic EL display device adopts pause driving, if the voltage value of the low-level power supply voltage ELVSS is set to the same value as that in an example shown in
In relation to this application, Japanese Laid-Open Patent Publication No. 2012-58443 describes that a power supply voltage applied to a power line differs between two modes (a high-voltage output mode and a low-voltage output mode). In the low-voltage output mode, for example, the frame frequency is one tenth of that in the high-voltage output mode. In the high-voltage output mode, a field-effect transistor is driven in a saturation region, and in the low-voltage output mode, the field-effect transistor is driven in a non-saturation region.
According to the above-described pause driving, operation of drive circuits such as a gate driver and a source driver stops throughout a pause period. Thus, power consumption arising from operation of the drive circuits is reduced. However, power that is directly related to light emission of the organic EL element 91 (hereinafter, referred to as “EL power” for the sake of convenience.) is not reduced almost at all even if pause driving is adopted. In this regard, in the organic EL display device, the EL power occupies the majority of power consumed by the entire device. Thus, a reduction in EL power may be a solution to an effective reduction in power consumption in the entire device.
Hence, to reduce the EL power, reducing an EL power supply voltage during a pause driving period to a level lower than that in a normal driving period is considered. More specifically, setting the voltage value of the low-level power supply voltage ELVSS used during a pause driving period to a higher value than the voltage value of the low-level power supply voltage ELVSS used during a normal driving period is considered. However, if the voltage value of the low-level power supply voltage ELVSS is increased, then in a pixel in which black display is performed, the voltage V(N3) at the third node N3 does not sufficiently decrease during the turn-off period 901 as described above. As a result, black floating occurs.
An object of the following disclosure is therefore to implement a display device that can reduce power consumption over a known example while preventing occurrence of black floating.
A drive method (for a display device) according to some embodiments of the present disclosure is a driving method for a display device including a plurality of data signal lines each transmitting a data voltage; a plurality of scanning signal lines that intersect the plurality of data signal lines; a plurality of light-emission control lines that intersect the plurality of data signal lines; and a plurality of pixel circuits to which a high-level power supply voltage and a low-level power supply voltage are provided, the plurality of pixel circuits each including a display element that is driven by a current, wherein
A display device according to some embodiments of the present disclosure is a display device including a plurality of pixel circuits to which a high-level power supply voltage and a low-level power supply voltage are provided, the plurality of pixel circuits each including a display element that is driven by a current, the display device including:
According to some embodiments of the present disclosure, during a pause driving period, the voltage value of a low-level power supply voltage is set to a higher value than that in a normal driving period. The low-level power supply voltage is provided to a second terminal of a display element (e.g., a cathode terminal of an organic EL element). In addition, during pause driving, a first terminal initialization period during which an initialization voltage is provided to a first terminal of the display element (e.g., an anode terminal of the organic EL element) is longer than that during normal driving. That is, the first terminal initialization period in the pause driving period is longer than that of a known example. As a result, during the pause driving period, even if the voltage value of the low-level power supply voltage is set to a higher value than that in the normal driving period, in a pixel in which black display is performed, the voltage at the first terminal of the display element sufficiently decreases in the first terminal initialization period. Therefore, in the pixel in which black display is performed, the voltage at the first terminal of the display element is maintained at a light-emission threshold voltage of the display element or less throughout a period during which pause driving is performed. Thus, black floating does not occur. In addition, by setting the voltage value of the low-level power supply voltage used in the pause driving period to a higher value than the voltage value of the low-level power supply voltage used in the normal driving period, EL power to be consumed is reduced. Therefore, a display device is implemented that can reduce power consumption over the known example while preventing occurrence of black floating.
An embodiment will be described below with reference to the accompanying drawings. Note that in the following description, it is assumed that i and j are integers greater than or equal to 2, n is an integer between 1 and i, inclusive, and m is an integer between 1 and j, inclusive. Note also that the number of writes of a data voltage per second to each pixel circuit during a period (data write period TW) during which data voltages are written to pixel circuits when focusing only on the period is referred to as “write frequency”, and the number of writes of a data voltage per second to each pixel circuit during the entire normal driving period or the entire pause driving period is referred to as “update frequency”.
<1. Overall Configuration>
As will be described later, in the present embodiment, in each pixel circuit 20 in the display unit 200, N-type transistors and P-type transistors coexist. Signals that control the N-type transistors are hereinafter referred to as “N-type control signals” and signals that control P-type transistors are hereinafter referred to as “P-type control signals”.
In the display unit 200 there are disposed i first scanning signal lines NS(1) to NS(i), i second scanning signal lines PS(1) to PS(i), i light-emission control lines EM(1) to EM(i), and j data signal lines D(1) to D(j). Note that depiction of those lines in the display unit 200 of
In addition, in the display unit 200 there are provided i×j pixel circuits 20 at intersecting portions of the i first scanning signal lines NS(1) to NS(i) and the j data signal lines D(1) to D(j). By thus providing the i×j pixel circuits 20, a pixel matrix of i rows×j columns is formed in the display unit 200. Furthermore, in the display unit 200 there are disposed power lines (not shown) that are shared between the pixel circuits 20. More specifically, there are disposed a power line that supplies a low-level power supply voltage ELVSS for driving organic EL elements (hereinafter, referred to as “low-level power line”), a power line that supplies a high-level power supply voltage ELVDD for driving the organic EL elements (hereinafter, referred to as “high-level power line”), and a power line that supplies an initialization voltage Vini (hereinafter, referred to as “initialization power line”).
Operation of each component shown in
The gate driver 300 is connected to the first scanning signal lines NS(1) to NS(i) and the second scanning signal lines PS(1) to PS(i). The gate driver 300 applies first scanning signals to the first scanning signal lines NS(1) to NS(i) and applies second scanning signals to the second scanning signal lines PS(1) to PS(i), based on the gate control signals GCTL outputted from the display control circuit 100. A high-level potential applied to the first scanning signal lines NS(1) to NS(i) is equal to a high-level potential applied to the second scanning signal lines PS(1) to PS(i), and a low-level potential applied to the first scanning signal lines NS(1) to NS(i) is equal to a low-level potential applied to the second scanning signal lines PS(1) to PS(i).
The emission driver 400 is connected to the light-emission control lines EM(1) to EM(i). The emission driver 400 applies light-emission control signals to the light-emission control lines EM(1) to EM(i), based on the emission driver control signals EMCTL outputted from the display control circuit 100.
The source driver 500 includes a j-bit shift register, a sampling circuit, a latch circuit, j D/A converters, and the like, which are not shown. The shift register has j cascade-connected registers. The shift register sequentially transfers a pulse of the source start pulse signal supplied to a register at an initial stage, from an input terminal to an output terminal, based on the source clock signal. In response to the transfer of the pulse, a sampling pulse is outputted from each stage of the shift register. Based on the sampling pulse, the sampling circuit stores a digital video signal DV. The latch circuit captures and holds digital video signals DV for one row that are stored in the sampling circuit, in accordance with the latch strobe signal. The D/A converters are provided so as to correspond to the respective data signal lines D(1) to D(j). The D/A converters convert the digital video signals DV held in the latch circuit into analog voltages. The converted analog voltages are simultaneously applied, as data signals, to all data signal lines D(1) to D(j).
In the above-described manner, the data signals are applied to the data signal lines D(1) to D(j), the first scanning signals are applied to the first scanning signal lines NS(1) to NS(i), the second scanning signals are applied to the second scanning signal lines PS(1) to PS(i), and the light-emission control signals are applied to the light-emission control lines EM(1) to EM(i), by which an image based on the input image signal DIN is displayed on the display unit 200.
Meanwhile, the low-level power supply voltage ELVSS, the high-level power supply voltage ELVDD, and the initialization voltage Vini are supplied from a power supply circuit 700 such as that shown in
<2. Pixel Circuits>
<2.1 Configuration of a Pixel Circuit>
A configuration of a pixel circuit 20 in the display unit 200 will be described. Note that the configuration of the pixel circuit 20 shown here is an example and thus is not limited thereto.
The first initialization transistor T1 is connected at its control terminal to a first scanning signal line NS(n−2) in an (n−2)th row, connected at its first conductive terminal to a second node N2, and connected at its second conductive terminal to an initialization power line. The threshold voltage compensation transistor T2 is connected at its control terminal to a first scanning signal line NS(n) in the nth row, connected at its first conductive terminal to a second conductive terminal of the drive transistor T4 and a first conductive terminal of the light-emission control transistor T6, and connected at its second conductive terminal to the second node N2. The write control transistor T3 is connected at its control terminal to a second scanning signal line PS(n) in the nth row, connected at its first conductive terminal to a data signal line D(m) in the mth column, and connected at its second conductive terminal to a first node N1. The drive transistor T4 is connected at its control terminal to the second node N2, connected at its first conductive terminal to the first node N1, and connected at its second conductive terminal to the first conductive terminal of the threshold voltage compensation transistor T2 and the first conductive terminal of the light-emission control transistor T6.
The power supply control transistor T5 is connected at its control terminal to a light-emission control line EM(n) in the nth row, connected at its first conductive terminal to a high-level power line and the first electrode of the holding capacitor Ca, and connected at its second conductive terminal to the first node N1. The light-emission control transistor T6 is connected at its control terminal to the light-emission control line EM(n) in the nth row, connected at its first conductive terminal to the first conductive terminal of the threshold voltage compensation transistor T2 and the second conductive terminal of the drive transistor T4, and connected at its second conductive terminal to a third node N3. The second initialization transistor T7 is connected at its control terminal to a first scanning signal line NS(n−1) in an (n−1)th row, connected at its first conductive terminal to the third node N3, and connected at second conductive terminal to the its initialization power line. The holding capacitor Ca is connected at its first electrode to the high-level power line and the first conductive terminal of the power supply control transistor T5, and connected at its second electrode to the second node N2. The organic EL element 21 is connected at its anode terminal to the third node N3, and connected at its cathode terminal to a low-level power line.
<2.2 Operation of the Pixel Circuit>
Next, operation of the pixel circuit 20 will be described.
During the period before time t1, a second scanning signal PS(n) is at high level, and a first scanning signal NS(n−2), a first scanning signal NS(n−1), a first scanning signal NS(n), and a light-emission control signal EM(n) are at low level. At this time, the power supply control transistor T5 and the light-emission control transistor T6 are in on state, and the organic EL element 21 emits light depending on the magnitude of a drive current.
At time t1, the light-emission control signal EM(n) changes from low level to high level. By this, the power supply control transistor T5 and the light-emission control transistor T6 go into off state. As a result, the supply of a current to the organic EL element 21 is interrupted, and the organic EL element 21 goes into turn-off state.
At time t2, the first scanning signal NS(n−2) changes from level to high level. By this, the first initialization transistor T1 goes into on state. As a result, the voltage at the second node N2 (the gate voltage of the drive transistor T4) is initialized. That is, the voltage at the second node N2 becomes equal to the initialization voltage Vini.
At time t3, the first scanning signal NS(n−1) changes from low level to high level. By this, the second initialization transistor T7 goes into on state. As a result, the voltage at the third node N3 (the anode voltage of the organic EL element 21) is initialized.
At time t4, the first scanning signal NS(n−2) changes from high level to low level. By this, the first initialization transistor T1 goes into off state. In addition, at time t4, the first scanning signal NS(n) changes from low level to high level. By this, the threshold voltage compensation transistor T2 goes into on state.
At time t5, the first scanning signal NS(n−1) changes from high level to low level. By this, the second initialization transistor T7 goes into off state. In addition, at time t5, the second signal PS(n) changes from high level to low level. By this, the write control transistor T3 goes into on state. Since the threshold voltage compensation transistor T2 is in on state at time t4, by the write control transistor T3 going into on state at time t5, a data signal D(m) is provided to the second node N2 through the write control transistor T3, the drive transistor T4, and the threshold voltage compensation transistor T2. That is, a data voltage is written to the holding capacitor Ca (the holding capacitor Ca is charged).
At time t6, the second scanning signal PS(n) changes from low level to high level. By this, the write control transistor T3 goes into off state. At time t7, the first scanning signal NS(n) changes from high level to low level. By this, the threshold voltage compensation transistor T2 goes into off state.
At time t8, the light-emission control signal EM(n) changes from high level to low level. By this, the power supply control transistor T5 and the light-emission control transistor T6 go into on state, and a drive current based on the charged voltage in the holding capacitor Ca is supplied to the organic EL element 21. As a result, the organic EL element 21 emits light depending on the magnitude of the drive current. Thereafter, the organic EL element 21 emits light throughout a period until the next time the light-emission control signal EM(n) changes from low level to high level.
Regarding the periods shown in
<3. Drive Method>
A drive method of the present embodiment will be described below. As described above, the organic EL display device according to the present embodiment is a display device that adopts pause driving. Thus, during operation of the organic EL display device, as shown in
<3.1 Normal Driving Period>
As shown in
<3.2 Pause Driving Period>
In a known organic EL display device that adopts pause driving, during a pause driving period, for example, as shown in
On the other hand, in the present embodiment, during a pause driving period, as shown in
Note that although here, as an example, a case is described in which a data write period TW with a length corresponding to two frame periods present during normal driving and a pause period TP with a length corresponding to two frame periods present during normal driving are repeated alternately (see
<3.3 Switching Between Normal Driving and Pause Driving>
Next, operation performed upon switching between normal driving and pause driving will be described. In a known organic EL display device that adopts pause driving, as shown in
On the other hand, in the present embodiment, as described above, during a pause driving period, the low-level power supply voltage output unit 72 outputs a low-level power supply voltage ELVSS having a higher voltage value than that in a normal driving period. Thus, upon switching from the normal driving period to the pause driving period, the voltage value of the low-level power supply voltage ELVSS increases as shown in
From the above, in the present embodiment, as shown in
Note that a normal driving step is implemented by the above-described step S10, a low-level power supply voltage increasing step is implemented by the above-described step S20, a pause driving step is implemented by the above-described step S30, and a low-level power supply voltage reducing step is implemented by the above-described step S40.
<4. Specific Example of a Reduction in EL Power>
A specific example of a reduction in EL power will be described.
In a normal driving period, the high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini are set as follows:
In a pause driving period, the high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini are set as follows:
The EL power P consumed during a certain period is proportional to the EL power supply voltage (a difference between the high-level power supply voltage ELVDD and the low-level power supply voltage ELVSS). More specifically, when the drive current flowing during a certain period is I, the EL power P consumed during the certain period is represented by the following equation (1):
P=(ELVDD−ELVSS)×I (1)
Based on the above equation (1), the EL power during the certain period in the normal driving period is “10.1×I”, and the EL power during the certain period in the pause driving period is “9.0×I”. Thus, as can be grasped from the following equation (2), by adopting the drive method of the present embodiment, the EL power during the pause driving period is reduced by about 11% compared to that of the known example.
((10.1−9.0)/10.1)×100=10.89 (2)
<5. Effects>
According to the present embodiment, during the pause driving period, the voltage value of the low-level power supply voltage ELVSS is set to a higher value than that in the normal driving period. In addition, during the normal driving period, the write frequency is 120 Hz, whereas during the pause driving period, the write frequency is 60 Hz. Thus, the length of a data write period TW during pause driving is a length corresponding to two frame periods present during normal driving. Therefore, a turn-off period during pause driving is longer than a turn-off period during normal driving. That is, during pause driving, an anode initialization period is longer than that during normal driving. In other words, the anode initialization period in the pause driving period is longer than that of the known example. As a result, during the pause driving period, even if the voltage value of the low-level power supply voltage ELVSS is set to a higher value than that in the normal driving period, in a pixel in which black display is performed, as shown in a portion given reference character 84 in
Meanwhile, the anode initialization period increases as the write frequency decreases, and thus, as shown in
From the above, according to the present embodiment, an organic EL display device is implemented that can reduce power consumption over the known example while preventing occurrence of black floating.
<6. Variants>
Variants of the above-described embodiment will be described below.
<6.1 First Variant>
According to the above-described embodiment, a data write period TW is longer during pause driving than during normal driving. In a case in which a pixel circuit 20 having the configuration shown in
Hence, in the present variant, during a pause driving period, in addition to setting the voltage value of the low-level power supply voltage ELVSS to a higher value than that in a normal driving period, the voltage value of a high-level power supply voltage DVDD for drivers (the gate driver 300 and the emission driver 400) is set to a lower value than that in the normal driving period. By this, during the pause driving period, the amount of power (analog power) consumption arising from operation of the drivers is reduced over the known example, and an effect of a further reduction in power consumption over the above-described embodiment can be obtained.
A specific example of a reduction in analog power by the present variant will be described below.
In a normal driving period, the high-level power supply voltage DVDD for the drivers and a low-level power supply voltage DVSS for the drivers are set as follows:
In a pause driving period, the high-level power supply voltage DVDD for the drivers and the low-level power supply voltage DVSS for the drivers are set as follows:
Analog power consumed by the drivers is proportional to the square of a difference between the high-level power supply voltage DVDD and the low-level power supply voltage DVSS. When K is the proportionality coefficient, analog power consumed during a certain period in the normal driving period is “(6.5+8.0)2×K”, and analog power consumed during the certain period in the pause driving period is “(6.0+8.0)2×K”. Thus, as can be grasped from the following equation (3), by adopting the technique of the present variant, analog power consumed during the pause driving period is reduced by about 7% compared to the known example.
((14.52−14.02)/14.52)×100=6.78 (3)
Note that the high-level power supply voltage DVDD for the drivers corresponds to a first power supply voltage, and the low-level power supply voltage DVSS for the drivers corresponds to a second power supply voltage.
<6.2 Second Variant>
In the above-described embodiment, in order to prevent occurrence of black floating, during a pause driving period, the write frequency is set to a lower value than that in a normal driving period. However, the same write frequency can be set for the normal driving period and the pause driving period, which will be described below.
In the present variant, too, the anode initialization period in the pause driving period is longer than that of the known example. As a result, even if the voltage value of the low-level power supply voltage ELVSS used during pause driving is set to a higher value than the voltage value of the low-level power supply voltage ELVSS used during normal driving, in a pixel in which black display is performed, the voltage V(N3) at the third node N3 sufficiently decreases during a turn-off period 82 in the pause driving period. Therefore, even at the end time of a light-emission period 83 in the pause driving period, the voltage V(N3) at the third node N3 is maintained at the light-emission threshold voltage Ve of the organic EL element 21 or less. Thus, black floating does not occur. As such, it becomes possible to reduce power consumption over the known example while preventing occurrence of black floating even when the write frequency of the data voltage is set the same for the normal driving period and the pause driving period.
<7. Others>
Although description is made using an organic EL display device as an example in n the above-described embodiment (including the variants), the configuration is not limited thereto, and the present disclosure can also be applied to inorganic EL display devices, QLED display devices, etc.
In addition, although description is made of an example in which the voltage value of the low-level power supply voltage ELVSS and the voltage value of the initialization voltage Vini are identical in the above-described embodiment (including the variants), the voltage value of the low-level power supply voltage ELVSS and the voltage value of the initialization voltage Vini may differ from each other. Also in this case, provided that the voltage value of the initialization voltage Vini is set such that the voltage V(N3) at the third node N3 does not exceed the light-emission threshold voltage Ve of the organic EL element 21 at the end time of the light-emission period 83 (see
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2020/017143 | 4/21/2020 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2021/214855 | 10/28/2021 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20110084958 | Choi | Apr 2011 | A1 |
| 20190340977 | Park | Nov 2019 | A1 |
| 20190362673 | Ueda | Nov 2019 | A1 |
| Number | Date | Country |
|---|---|---|
| 2012-058443 | Mar 2012 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20240203344 A1 | Jun 2024 | US |
