Patent Grant
11996044
The disclosure relates to a display device, and more particularly to a current-driven display device including a display element driven by a current, such as an organic electro luminescence (EL) element, and a driving method for the display device.
The last few years have seen the implementation of organic EL display devices provided with a pixel circuit including organic EL elements (also referred to as organic light-emitting diodes (OLEDs)). The pixel circuit in such an organic EL display device includes a drive transistor, a write control transistor, and a holding capacitor in addition to the organic EL elements. A thin film transistor is used for the drive transistor and the write control transistor. The holding capacitor is connected to a gate terminal that serves as a control terminal of the drive transistor. A voltage corresponding to an image signal representing an image to be displayed (more specifically, a voltage indicating the gradation values of pixels to be formed by the pixel circuit) is applied as data voltage to the holding capacitor from the drive circuit via a data signal line. The organic EL element is a self-luminous display element that emits light with luminance according to an electric current flowing through the organic EL element. The drive transistor is connected to the organic EL element in series and controls the electric current passing through the organic EL element according to a voltage held by the holding capacitor.
Variation and fluctuation occur in characteristics of the organic EL element and the drive transistor. Thus, variation and fluctuation in characteristics of these elements need to be compensated in order to perform higher picture quality display in the organic EL display device. For the organic EL display device, a method for compensating the characteristics of the elements inside the pixel circuits and a method for compensating the characteristics of the elements outside the pixel circuit are known. One known pixel circuit corresponding to the former method is a pixel circuit configured to charge the holding capacitor with the data voltage via the drive transistor in a diode-connected state after initializing voltage at the gate terminal of the drive transistor, that is, the voltage held in the holding capacitor. In such a pixel circuit, variation and fluctuation of the threshold voltage in the drive transistor are compensated for within the pixel circuit (hereinafter, the compensation of variation and fluctuation of such a threshold voltage is referred to as “threshold compensation” and the method of performing threshold compensation within the pixel circuit in this manner is referred to as the “internal compensation method”).
A known pixel circuit of an organic EL display device using the internal compensation method uses a P-channel thin film transistor with a channel layer formed of low-temperature polysilicon (LTPS). Also, a known configuration for a gate driver configured to control the operation of a pixel circuit uses a P-channel thin film transistor (for example, JP 2017-227880 A). Since low-temperature polysilicon has high mobility, when a thin film transistor with a channel layer formed of low-temperature polysilicon (hereinafter referred to as “LTPS-TFT”) is used as a drive transistor, driving capability for an organic EL element in a pixel circuit is improved, and when used as a switching element, on-resistance is reduced.
In recent years, a thin film transistor with a channel layer formed of an oxide semiconductor (hereinafter referred to as an “oxide TFT”) has attracted attention. Since the oxide TFT has a small off-leak current, it is suitable as a switching element in a pixel circuit or the like. As the oxide TFT, typically, a thin film transistor including indium gallium zinc oxide (InGaZnO) (hereinafter referred to as “IGZO-TFT”) is used.
Also, a display device configured to perform pause driving is a known display device with low power consumption. Pause driving is a driving method referred to as “intermittent driving” or “low-frequency driving” with a drive period (refresh period) in which the same image is continuously displayed and a pause period (non-refresh period). In pause driving, a drive circuit is activated in the drive period and operations of the drive circuit are paused in the pause period.
Pause driving can be used when the off-leak current of the transistor in the pixel circuit is small. For this reason, utilizing the advantages of LTPS-TFT and oxide TFT (IGZO-TFT) described above, an organic EL display device has been proposed that is configured to perform pause driving of a display portion constituted by a pixel circuit, wherein in the pixel circuit, LTPS-TFT is used as a drive transistor and IGZO-TFT is used as a switching element (for example, see US 2020/0118487 A).
When the organic EL display device performs pause driving, in the drive period, the organic EL element in each pixel circuit is turned off by a light emission control transistor in a non-light emission period provided in each frame period, and in the pause period, the operations of the drive circuit are stopped, and light is continuously emitted at a luminance corresponding to the data voltage written in the previous drive period. In general, the pause period is much longer than the drive period (the drive period includes 1 or a few frame periods and the pause period includes tens of frame periods), and a pause driving method organic EL display device alternates between the drive period and the pause period when activated. For this reason, when performing pause driving, the organic EL elements of the drive period turning off may be noticeable as a flicker.
Regarding this, in US 2019/0057646 A, a pixel circuit and a driving method for the same are described. To remove noticeable flicker when performing pause driving (low-frequency driving), the pixel circuit is configured such that a decrease in luminance occurs at an appropriate frequency in a pause period (extended blanking period T_blank) in addition to a decrease in luminance being caused by an organic EL element (light-emitting diode 304) turning off in the drive period (data refresh period T_refresh) (see paragraphs [0049] to [0052] and
However, even with a configuration in which a decrease in luminance occurs at an appropriate frequency in the pause period (hereinafter, such a configuration is referred to as a “periodic turn-off configuration”, because the thin film transistor functioning as the drive transistor in the pixel circuit has a hysteresis characteristic, flicker remains noticeable at low-frequency driving (pause driving). That is, in this periodic turn-off configuration, since the voltage stress applied to the thin film transistor functioning as the drive transistor is different between the drive period and the pause period, the turn-off waveform is slightly different between the drive period and the pause period due to the hysteresis characteristic of the drive transistor, which causes a noticeable flicker.
In order to suppress the occurrence of flicker caused by the hysteresis characteristic of such a drive transistor, intentionally applying a bias stress voltage (hereinafter, referred to as a “on-bias stress voltage” or simply as a “bias voltage”) to the drive transistor in the pause period has been considered (for example, see US 2020/0118487 A and JP 2020-112795 A). In order to apply the on-bias stress voltage, an appropriate configuration is needed on the scanning-side drive circuit, leading to an increase in the amount of circuits. This prevents frame narrowing of the display device.
Thus, there is a demand for a current-driven display device such as an organic EL display device with a good display without noticeable flicker even when pause driving is performed. Also, there is a demand for a circuit with a simple configuration for applying an on-bias voltage for suppressing flicker caused by the hysteresis characteristic of a drive transistor in such a current-driven display device.
A display device according to some embodiments of the disclosure, using a display element driven by a current, includes:
In a display device according to some other embodiments of the disclosure based on the display device according to some embodiments described above,
A driving method according to yet other embodiments of the disclosure is a driving method for a display device using a display element driven by a current, the display device including a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of light emission control lines, and a plurality of pixel circuits,
According to some embodiments of the disclosure, in an internal compensation method display device using a pixel circuit including a display element driven by a current, a drive transistor, a write control transistor, a threshold compensation transistor, a light emission control transistor, and a holding capacitor configured to hold data voltage, when pause driving is performed in which a drive period including a refresh frame period and a pause period including a non-refresh frame period alternates between one another, not only in the drive period but also in the pause period, the plurality of light emission control lines are selectively made inactive, providing a non-light emission period. Also, in the pause period, the driving of the first scanning signal lines for controlling the threshold compensation transistor is stopped, and the second scanning signal lines for controlling the write control transistor are driven as in the drive period. Thus, in each pixel circuit, in the non-light emission period in which the light emission control transistor is in the off state, by maintaining the threshold compensation transistor in the off state, without affecting the holding voltage (written data voltage) in the holding capacitor, the voltage of the data signal line corresponding to the pixel circuit is applied to the first conduction terminal of the drive transistor as the bias voltage via the write control transistor. By applying the bias voltage in this manner, a threshold shift caused by the hysteresis characteristic of the drive transistor can be suppressed. When the threshold shift of the drive transistor is suppressed in this manner, the turn-off waveform (waveform portion corresponding to the non-light emission period) included in the luminance waveform of each pixel circuit has a similar shape in the pause period as in the drive period. Accordingly, even when performing pause driving to achieve low power consumption, good display without noticeable flicker is achieved.
According the some embodiments of the disclosure, the unit circuit forming the shift register inside the scanning-side drive circuit includes the first output circuit configured to output a signal to be applied to the first scanning signal line for controlling the threshold compensation transistor inside the pixel circuit and the second output circuit configured to output a signal to be applied to the second scanning signal line for controlling the write control transistor inside the pixel circuit and further includes a first control circuit configured to send the input signal to the first internal node at a timing according to the first control clock signal and a second control circuit configured to generate a logic level inverted to a logic level of the first internal node and sent the logic level generated to the second internal node. When pause driving is performed with the drive period including the refresh frame period and the pause period including the non-refresh frame period alternating between one another, the first output circuit, in the drive period, outputs a signal with a logic level changing according to the logic level of the first internal node to the corresponding first scanning signal line and, in the pause period, outputs a non-active signal to the first scanning signal line. Irrespective of whether it is in the drive period or the pause period, the second output circuit outputs a signal of a logic level based on the logic level of the first internal node and the second internal node to the corresponding second scanning signal line. According to such a configuration, by going through the first internal node where the logic level is controlled by the first control circuit, a large increase in the amount of circuits is avoided and two types of scanning signals to be applied to the first and the second scanning signal lines are generated. That is, when pause driving is performed, in the pixel circuit, in the drive period, the write control transistor and the threshold compensation transistor are controlled as in normal driving, and in the non-light emission period in the pause period, the off state of the threshold compensation transistor is maintained and the write control transistor is turned to an on state so that two types of scanning signals for driving the first and the second scanning signal lines can be achieved with a relatively low amount of circuits.
Embodiments will be described below with reference to the accompanying drawings. Note that in each of the transistors referred to below, the gate terminal corresponds to a control terminal, one of a drain terminal and a source terminal corresponds to a first conduction terminal, and the other corresponds to a second conduction terminal. The transistor according to the following embodiments is, for example, a thin film transistor, but the disclosure is not limited to this. Still further, the term “connection” used herein means “electrical connection” unless otherwise specified, and without departing from the spirit and scope of the disclosure, the term includes not only a case in which direct connection is meant but also a case in which indirect connection with another element therebetween is meant.
As illustrated in
The display portion 11 is provided with m (m is an integer of 2 or greater) data signal lines D1, D2 to Dm, n+2 (n is an integer of 2 or greater) first scanning signal lines NS−1, NS0, NS1 to NSn and n second scanning signal lines PS1, PS2 to PSn that intersect the data signal lines D1, D2 to Dm, and n light emission control lines (emission lines) EM1 to EMn disposed along the n second scanning signal lines PS1, PS2 to PSn, respectively. Also, in the display portion 11, m×n pixel circuits 15 are arranged in a matrix shape along the m data signal lines D1 to Dm and the n second scanning signal lines PS1 to PSn. Each pixel circuit 15 corresponds to one of the m data signal lines D1 to Dm and to one of the n second scanning signal lines PS1 to PSn (hereinafter, when distinguishing between each pixel circuit 15, a pixel circuit corresponding to an i-th second scanning signal line PS1 and a j-th data signal line Dj will also be referred to as an “i-th row, j-th column pixel circuit”, and will be denoted by the reference sign “Pix(i, j)”). Also, each pixel circuit 15 also corresponds to one of the n first scanning signal lines NS1 to NSn and to one of the n light emission control lines EM1 to EMn.
The display portion 11 is also provided with a power source line (not illustrated) common to each pixel circuit 15. In other words, a first power source line (hereinafter, referred to as a “high-level power source line” and designated by the reference sign “ELVDD” similar to the high-level power supply voltage) used for supplying the high-level power supply voltage ELVDD for driving the organic EL element described later, and a second power source line (hereinafter, referred to as a “low-level power source line” and designated by the reference sign “ELVSS” similar to the low-level power supply voltage) used for supplying the low-level power supply voltage ELVSS for driving the organic EL element are provided. More specifically, the low-level power source line ELVSS is a cathode common to the plurality of pixel circuits 15. The display portion 11 also includes a not illustrated initialization voltage line (denoted by the same reference sign “Vini” as that of the initialization voltage) for supplying the initialization voltage Vini used in a reset operation (also referred to as an “initialization operation”) for initializing each pixel circuit 15. The high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini are supplied from the power supply circuit 50.
The display control circuit 20 receives an input signal Sin including image information representing an image to be displayed and timing control information for image display from outside of the display device 10 and, based on the input signal Sin, generates a data-side control signal Scd and a scanning-side control signal Scs, and outputs the data-side control signal Scd to the data-side drive circuit 30 and outputs the scanning-side control signal Scs to the scanning-side drive circuit 40.
The data-side drive circuit 30 drives the data signal lines D1 to Dm based on the data-side control signal Scd output from the display control circuit 20. More specifically, the data-side drive circuit 30 generates m data signals D(1) to D(m) representing the image to be displayed, and applies the data signals D(1) to D(m) to the data signal lines D1 to Dm, respectively, based on the data-side control signal Scd.
The scanning-side drive circuit 40 functions, based on the scanning-side control signal Scs from the display control circuit 20, as a scanning signal line drive circuit that drives the n+2 first scanning signal lines NS−1 to NSn and the n second scanning signal lines PS1 to PSn and a light emission control circuit that drives the light emission control lines EM1 to EMn.
More specifically, the scanning-side drive circuit 40, in the refresh frame period Trf, functioning as the scanning signal line drive circuit, based on the scanning-side control signal Scs, sequentially selects the n+2 first scanning signal lines NS−1 to NSn each predetermined period corresponding to one horizontal period and sequentially selects the n second scanning signal lines PS1 to PSn each predetermined period corresponding to one horizontal period, applies an active signal to the selected first scanning signal line NSs (s is an integer satisfying −1≤s≤n) and applies an active signal to the selected second scanning signal line PSk (k is an integer satisfying 1≤k≤n), and applies a non-active signal to the non-selected first scanning signal lines and applies a non-active signal to the non-selected second scanning signal lines. With this, m pixel circuits Pix(k, 1) to Pix(k, m) corresponding to the selected second scanning signal line PSk are collectively selected. As a result, in the select period of the second scanning signal line PSk (hereinafter referred to as a “kth scanning select period”), the voltages of the m data signals D(1) to D(m) applied to the data signal lines D1 to Dm from the data-side drive circuit 30 (hereinafter also referred to as simply “data voltages” when not distinguished from each other) are written as pixel data to the pixel circuits Pix(k, 1) to Pix(k, m), respectively. Note that as illustrated in
In addition, in the refresh frame period Trf, the scanning-side drive circuit 40 drives the light emission control lines EM1 to EMn so that the light emission control lines EM1 to EMn are selectively inactivated in conjunction with the driving of the first and second scanning signal lines NS−1 to NSn and PS1 to PSn. That is, when functioning as the light emission control circuit, based on the scanning-side control signal Scs, the scanning-side drive circuit 40 applies a light emission control signal (high-level voltage) indicating non-light emission to an i-th light emission control line EM1 in a predetermined period including the i-th horizontal period and applies a light emission control signal (low-level voltage) indicating light emission to the i-th light emission control line EM1 in other periods (i=1 to n). Organic EL elements in pixel circuits (hereinafter also referred to as “i-th row pixel circuits”) Pix(i, 1) to Pix(i, m) corresponding to the i-th second scanning signal line PS1 emit light at a luminance corresponding to the data voltages written to the i-th row pixel circuits Pix(i, 1) to Pix(i, m), respectively, while the voltage of the light emission control line EM1 is at a low level (activated state).
As described above, the display device 10 according to the present embodiment has two operation modes, the normal driving mode and the pause driving mode. First, schematic operations of the display device 10 in the normal driving mode will be described.
In the normal driving mode, by driving, as described above, the first scanning signal lines NS−1 to NSn, the second scanning signal lines PS1 to PSn, the light emission control lines EM1 to EMn, and the data signal lines D1 to Dm via the various signals illustrated in
On the other hand, in the pause driving mode, as illustrated in
The input signal Sin from the outside includes an operation mode signal Sm indicating which operation mode, from among the normal driving mode and the pause driving mode as described above, to drive the display portion 11 with. The operation mode signal Sm is sent to the scanning-side drive circuit 40 as a part of the scanning-side control signal Scs and sent to the data-side drive circuit 30 as a part of the data-side control signal Scd. The scanning-side drive circuit 40 drives the first scanning signal lines NS−1 to NSn according to the operation mode indicated by the operation mode signal Sm, and the data-side drive circuit 30 drives the data signal lines D1 to Dn according to the operation mode indicated by the operation mode signal Sm (see
In the present embodiment, in the drive period TD (RF frame period Trf), at each pixel circuit Pix(i, j), when the corresponding first and second scanning signal lines NSi and PS1 are in a select state, a data write operation is performed, when the second previous first scanning signal line NSi−2 of the first scanning signal line NSi is in a select state, a reset operation is performed, and the light emission control line EM1 is driven such that each pixel circuit Pix(i, j) is put in a non-light emission state in the period in which the data write operation and the reset operation is performed (i=1 to n) (see
Next, the configuration and operations of the pixel circuit 15 in the present embodiment will be described with reference to
To the pixel circuit Pix(i, j), the first scanning signal line NSi corresponding thereto (hereinafter, also referred to as the “corresponding first scanning signal line” in the description focusing on the pixel circuit), the corresponding second scanning signal line (hereinafter also referred to as “corresponding second scanning signal line” in the description focusing on the pixel circuit) PS1 connected to the second previous first scanning signal line (the second previous scanning signal line in the scanning order from among the first scanning signal lines NS−1 to NSn, hereinafter referred to simply as “preceding first scanning signal line” in the description focusing on the pixel circuit) of the corresponding first scanning signal line NSi, in other words the i−2th the first scanning signal line NSi−2, the light emission control line EM corresponding thereto (hereinafter, also referred to as the “corresponding light emission control line” in the description focusing on the pixel circuit), the data signal line Dj corresponding thereto (hereinafter also referred to as the “corresponding data signal line” in the description focusing on the pixel circuit), the initialization voltage line Vini, the high-level power source line ELVDD, and the low-level power source line ELVSS are connected. In another configuration, instead of the preceding first scanning signal line NSi−2, the immediately preceding first scanning signal line NSi−1 may be connected to the pixel circuit Pix(i, j).
The gate terminal of the first initialization transistor T1 is connected to the second previous first scanning signal line, that is the preceding first scanning signal line NSi−2, and the drain terminal is connected to the second electrode of the holding capacitor Cst, the gate terminal of the drive transistor T4, and the source terminal of the threshold compensation transistor T2.
The gate terminal of the threshold compensation transistor T2 is connected to the corresponding first scanning signal line NSi, the drain terminal is connected to the drain terminal of the drive transistor T4 and the source terminal of the second light emission control transistor T6, and the source terminal is connected to the gate terminal of the drive transistor T4.
The gate terminal of the write control transistor T3 is connected to the corresponding second scanning signal line PS1, the source terminal is connected to the corresponding data signal line Dj, and the drain terminal is connected to the source terminal of the drive transistor T4 and the drain terminal of the first light emission control transistor T5. The gate terminal of the drive transistor T4 is connected to the second electrode of the holding capacitor Cst, the source terminal is connected to the drain terminal of the write control transistor T3 and the drain terminal of the first light emission control transistor, and the drain terminal is connected to the source terminal of the second light emission control transistor T6. The gate terminal of the first light emission control transistor T5 is connected to the corresponding light emission control line EM1, the source terminal is connected to the high-level power source line ELVDD, and the drain terminal is connected to the source terminal of the drive transistor T4. The gate terminal of the second light emission control transistor T6 is connected to the corresponding light emission control line EM1, the source terminal is connected to the drain terminal of the drive transistor T4, and the drain terminal is connected to the anode electrode of the organic EL element OL. The gate terminal of the second initialization transistor T7 is connected to the corresponding light emission control line EM1, the source terminal is connected to the initialization voltage line Vini, and the drain terminal is connected to the anode electrode of the organic EL element OL. The first electrode of the holding capacitor Cst is connected to the high-level power source line ELVDD, and the second electrode is connected to the gate terminal of the drive transistor T4. The anode electrode of the organic EL element OL is connected to the drain terminal of the second light emission control transistor T6, and the cathode electrode is connected to the low-level power source line ELVSS.
Next, the operations of the pixel circuit 15 illustrated in
When the light emission control signal EM(i) sent to the pixel circuit Pix(i, j) in
In the non-light emission period t1 to t8, the first scanning signal (hereinafter also referred to as the “preceding first scanning signal”) NS(i−2) sent to the pixel circuit Pix(i, j) via the preceding first scanning signal line NSi−2 is changed at time t2 from L level to H level. Accordingly, the N-type first initialization transistor T1 changes from the off state to the on state and stays in the on state while the first scanning signal NS(i−2) is the H level. In period (hereinafter referred to as the “initialization period”) t2 to t3 in which the first initialization transistor T1 is in the on state, the holding capacitor Cst is initialized, and a voltage (hereinafter referred to as the “gate voltage”) Vg of the gate terminal of the drive transistor T4 becomes the initialization voltage Vini.
In the non-light emission period t1 to t8 of the pixel circuit Pix(i, j) in
In the period t4 to t7 in which the threshold compensation transistor T2 is in the on state, the second scanning signal (hereinafter also referred to as the “corresponding second scanning signal”) PS(i) sent to the pixel circuit Pix(i, j) via the corresponding second scanning signal line PS1 changes from the H level to the L level at time t5. Accordingly, the P-type write control transistor T3 changes from the off state to the on state and stays in the on state while the second scanning signal PS(i) is the L level. In the period (hereinafter referred to as the “data write period”) t5 to t6 in which the write control transistor T3 is in the on state, the voltage of the data signal D(j) sent to the pixel circuit Pix(i, j) via the corresponding data signal line Dj is applied to the holding capacitor Cst via the drive transistor T4 in the diode-connected state as a data voltage Vdata. Accordingly, the data voltage post-threshold compensation is written and held in the holding capacitor Cst, and the voltage (gate voltage) Vg of the gate terminal of the drive transistor T4 is maintained at the voltage of the second electrode of the holding capacitor Cst. At this time, when the threshold value of the drive transistor T4 satisfies Vth (<0), the gate voltage Vg is the value obtained via the following formula.
Vg=Vdata+Vth (1)
In this manner, in the data write period t5 to t6, internal compensation is performed and the data voltage is written.
At time t7 after the data write period t5 to t6, the first scanning signal NS(i) changes from the H level to the L level, and the threshold compensation transistor T2 turns to the off state. Next, at time t8, the light emission control signal EM(i) changes from the H level to the L level. Accordingly, the first and second light emission control transistors T5 and T6 turn to the on state and the light emission period starts.
Next, the operations in the (NRF frame period Tnrf in the) pause period TP of the pixel circuit 15 illustrated in
In the pause period TP according to the comparative example, the light emission control lines EM1 to EMn is driven as in the drive period TD (the same period and the same duty ratio), and the period in which the first and second light emission control transistors T5 and T6 turn to the off state and the duration of the off state are the same, irrespective of whether it is the drive period TD or the pause period TP. However, the driving of the first scanning signal lines NS−1 to NSn and the second scanning signal lines PS1 to PSn both will stop. Thus, as illustrated in
In the pause period TP according to the present embodiment, the light emission control lines EM1 to EMn as well as the second scanning signal lines PS1 to PSn are driven as in the drive period TD (the same period and the same duty ratio), and the driving of the first scanning signal lines NS−1 to NSn is stopped. Thus, as illustrated in
In the present embodiment, in the pause period TP, an on-bias voltage Vob described below is applied to each data signal line Dj from the data-side drive circuit 30 as the data signal D(j). Thus, in the period (hereinafter referred to as the “bias application period”) t5 to t6 in which the corresponding second scanning signal PS(i) is the L level, the on-bias voltage Vob is applied to the source terminal of the drive transistor T4. The on-bias voltage Vob applied at this time is held at the source terminal (by parasitic capacitance) of the drive transistor T4 until time t8 when the light emission control signal EM(i) changes to the L level (activated state). Thus, the period (hereinafter referred to as the “on-bias period”) in which the on-bias voltage Vob is substantially sent to the source terminal of the drive transistor T4 is from time t5 to time t8 as illustrated in
The effects relating to the turn-off operation according to the present embodiment in the pause driving mode will be described below with reference to the turn-off operation according to the comparative example.
In the comparative example, as can be seen from
As can be seen from
In the drive period TD (RF frame period Trf), when the light emission control signal EM(i) changes from the H level to the L level, the pixel circuit Pix(i, j), as illustrated in
VgsW=Vth (2).
Note that a gate voltage VgW at this time is, as per Formula (1) described above,
VgW=Vdata+Vth (3).
When the data write operation state 15(WR) changes to the lighting operation state 15(EM), the threshold compensation transistor T2 changes from the on state to the off state, and a feed-through voltage ΔV (<0) caused by the parasitic capacitance of the threshold compensation transistor T2 occurs at the gate terminal of the drive transistor T4. For this reason, a gate voltage VgE of the drive transistor T4 in the lighting operation state 15(EM) is, as per Formula (3) described above,
VgE=VgW+ΔV=Vdata+Vth+ΔV (4).
The gate-source voltage VgsE of the drive transistor T4 at this time is
VgsE=Vdata+Vth+ΔV−ELVDD (5).
In the pause period TP (NRF frame period Tnrf), when the light emission control signal EM(i) changes from the H level to the L level, the pixel circuit Pix(i, j), as illustrated in
VgNE=Vdata+Vth+ΔV (6)
(leakage current is ignored here). At this time, since the first light emission control transistor T5 is in the off state and the source terminal of the drive transistor T4 is in a floating state, the gate-source voltage Vgs of the drive transistor T4 is indefinite.
However, when the preceding source terminal voltage ELVDD for changing the first light emission control transistor T5 to the off state is held by the parasitic capacitance of the source terminal, a gate-source voltage VgsNE is
VgsNE=Vdata+Vth+ΔV−ELVDD (7).
When the lighting operation state 15(NEM) changes to the lighting operation state 15a(EM), the first light emission control transistor T5 changes from the off state to the on state, and the high-level power supply voltage ELVDD is applied to the source terminal of the drive transistor T4. Accordingly, the gate voltage VgE and the gate-source voltage VgsE of the drive transistor T4 in the lighting operation state 15a(EM) is, as with the lighting operation state 15(EM) in the drive period TD, represented by Formulas (4) and (5) described above.
In the comparative example as described above, as is clear from Formulas (2) and (7) described above, the gate-source voltage VgsW of the drive transistor T4 in the write operation state 15(WR) before the start of the light emitting operation in the drive period TD and the gate-source voltage VgsNE of the drive transistor T4 in the turn-off operation state 15a(NEM) before the start of the light emitting operation in the pause period TP differ greatly. Thus, due to the hysteresis characteristic of the drive transistor T4, the absolute value of the threshold value Vth is less at the start time (time t8 in
However, in the present embodiment, in the drive period TD (RF frame period Trf), though the state of the pixel circuit Pix(i, j) before and after the light emission control signal EM(i) changes from the H level to the L level is as illustrated in
That is, in the pause period TP according to the present embodiment, in the non-light emission period before the light emission control signal EM(i) changes from the H level to the L level, the bias application period t5 to t6 in which the write control transistor T3 is turned to the on state is provided (see
VgOB=Vdata+Vth+ΔV (8).
Thus, a gate-source voltage VgsOB of the drive transistor T4 in the bias application period t5 to t6 illustrated in
VgsOB=Vdata+Vth+ΔV−Vob (9).
When the bias application state 15(OB) ends and the turn-off operation state transitions to the lighting operation state 15(EM), the first light emission control transistor T5 changes from the off state to the on state, and the high-level power supply voltage ELVDD is applied to the source terminal of the drive transistor T4. At this time, the pixel circuit Pix(i, j) changes from the bias application state 15(OB) illustrated in
According to the present embodiment described above, as can be seen from Formulas (2) and (9) described above, in the pause period TP, the value of the on-bias voltage Vob to be output from the data-side drive circuit 30 is appropriately set. Thus, a threshold shift due to the hysteresis characteristic caused by a difference in the voltage stress on the drive transistor T4 in the non-light emission period can be suppressed. Thus, by appropriately setting the on-bias voltage Vob to suppress a threshold shift due to the hysteresis characteristic of the drive transistor T4, a difference between the threshold value Vth of the drive transistor T4 at the start time (time t8 in
As can be seen from the foregoing, to suppress flicker in pause driving, the on-bias voltage Vob for suppressing a threshold shift caused by the hysteresis characteristic of the drive transistor T4 must be appropriately set. Regarding the present embodiment configured as described above, the relationship between the various parameters indicating the operation conditions and the like (hereinafter collectively referred to as “operation condition parameters”) and the appropriate on-bias voltage for suppressing a threshold shift caused by the hysteresis characteristic of the drive transistor T4 has been theoretically studied and computer simulations and experiment have been carried out to ascertain the following results.
Regarding the relationship between the light emission duty and an appropriate on-bias voltage Vob, the appropriate on-bias voltage Vob decreases when the light emission duty decreases. Here, light emission duty refers to the proportion of the period (light emission period) in which the light emission control signal EM(i) is the L level relative to one frame period. The magnitude of the on-bias voltage Vob depends on the magnitude of the voltage difference (absolute value) between the gate and source at the drive transistor T4.
For example,
The relationships between other operation condition parameters including display gray scale, refresh rate, environment temperature, on-bias time and an appropriate on-bias voltage Vob are as follows.
As per (1) to (4) described above, the on-bias voltage should be set according to the display gray scale, the refresh rate, the environment temperature, and the length of the on-bias period Tob such that the relationship between the display device operation condition parameters including the display gray scale, the refresh rate, the environment temperature, and the on-bias time and the on-bias voltage Vob match the relationships illustrated in
Alternatively, instead of this, a configuration can be used in which the on-bias voltage Vob is changed in real time according to the value for one or more of the operation condition parameters.
As described above, the scanning-side drive circuit 40 according to the present embodiment functions as a scanning signal line drive circuit and a light emission control circuit (see
In the present embodiment, as illustrated in
Each unit circuit 3 includes input terminals for receiving the first control clock signal CK1, the second control clock signal CK2, the set signal S, the gate high voltage VGH, and the gate low voltage VGL and output terminals for outputting a first output signal OUT1 and a second output signal OUT2. The first output signal OUT1 is an N-type control signal, and the second output signal OUT2 is a P-type control signal. That is, at each unit circuit 3, an N-type control signal and a P-type control signal is generated.
The unit circuits 3 at even-numbered stages are sent the first gate clock signal GCK1 as the first control clock signal CK1 and are sent the second gate clock signal GCK2 as the second control clock signal CK2. The unit circuits 3 at odd-numbered stages are sent the second gate clock signal GCK2 as the first control clock signal CK1 and are sent the first gate clock signal GCK1 as the second control clock signal CK2. The gate high voltage VGH and the gate low voltage VGL are sent in common to all of the unit circuits 3. Also, the unit circuit 3 at each stage is sent the second output signal OUT2 from the unit circuits 3 of the preceding stages as the set signal S. The first output signal OUT1 from the unit circuit 3 at each stage is sent to the corresponding first scanning signal line NS as the first scanning signal. The second output signal OUT2 from the unit circuit 3 at each stage is sent to the following unit circuit 3 as the set signal S and sent to the corresponding second scanning signal line PS as the second scanning signal. Note that as illustrated in
The first gate clock signal GCK1 and the second gate clock signal GCK2 are periodically repeated two-phase clock signals of a first period in which the gate low voltage VGL (first level voltage) is maintained and a second period in which the gate high voltage VGH (second level voltage) is maintained. Typically, a length P1 of the first period is shorter than a length P2 of the second period. Note that the first gate clock signal GCK1 and the second gate clock signal GCK2 are output from a clock signal output circuit provided inside the display control circuit 20.
1.8.2 Unit Circuit
The second conduction terminal (source terminal) of the transistor M3 and the control terminal (gate terminal) of the transistors M4 to M7 are connected to one another, and the node where each are connected is referred to as the “first internal node”. The first internal node is denoted by the reference sign N1. The voltage of the first internal node N1 indicates the logical value to be transferred in the shift register 301. The control terminal (gate terminal) of the transistor M1 and one end of the capacitor C1 are connected to one another. As illustrated in
The unit circuit 3 includes a first control circuit 311 configured to control the voltage of the first internal node N1, a first output circuit 323 configured to control the output of the first output signal OUT1, a second control circuit 321 configured to control the voltage of the second internal node N2, and a second output circuit 322 configured to control the output of the second output signal OUT2. The first control circuit 311 includes the transistor M3. An output terminal 35 of the first control circuit 311 is connected to the first internal node N1. The second control circuit 321 includes the transistor M6 and the transistor M7. The first output circuit 323 includes the transistor M4 and the transistor M5. The second output circuit 322 includes the transistor M1, the transistor M2, and the capacitor C1. Note that the unit circuit 3 is configured such that a threshold voltage Vtn (>0) of the N-type transistor M5 in the first output circuit 323 is greater than the absolute value of a threshold voltage Vtp (<0) of the P-type transistor M3 in the first control circuit 311. The same applies to other embodiments described later (see
Regarding the transistor M1, the control terminal (gate terminal) is connected to the first internal node N1, the first conduction terminal (drain terminal) is connected to the input terminal 33, and the second conduction terminal (source terminal) is connected to the second output terminal 39. Regarding the transistor M2, the control terminal (gate terminal) is connected to the second internal node N2, the first conduction terminal (source terminal) is connected to the second constant voltage line, and the second conduction terminal (drain terminal) is connected to the second output terminal 39. Regarding the transistor M3, the control terminal (gate terminal) is connected to the input terminal 32, the first conduction terminal (drain terminal) is connected to the input terminal 31, and the second conduction terminal (source terminal) is connected to the first internal node N1. Regarding the transistor M4, the control terminal (gate terminal) is connected to the first internal node N1, the first conduction terminal (source terminal) is connected to the input terminal 34, that is the input terminal for receiving the drive-time gate high signal VGH2, and the second conduction terminal (drain terminal) is connected to the first output terminal 38. Regarding the transistor M5, the control terminal (gate terminal) is connected to the first internal node N1, the first conduction terminal (drain terminal) is connected to the first output terminal 38, and the second conduction terminal (source terminal) is connected to the first constant voltage line. Regarding the transistor M6, the control terminal (gate terminal) is connected to the first internal node N1, the first conduction terminal (source terminal) is connected to the second constant voltage line, and the second conduction terminal (drain terminal) is connected to the second internal node N2. Regarding the transistor M7, the control terminal (gate terminal) is connected to the first internal node N1, the first conduction terminal (drain terminal) is connected to the second internal node N2, and the second conduction terminal (source terminal) is connected to the first constant voltage line. One end of the capacitor C1 is connected to the control terminal (gate terminal) of the transistor M1 and the other end is connected to the second output terminal 39.
The operations of the shift register 301 configured as described above will be described below with reference to
First, the operations of the unit circuit 3 in the drive period TD (RF frame period) will be described with reference to
At time t11, the first control clock signal CK1 changes from the H level to the L level, putting the transistor M3 in the on state. Also, at time t11, the set signal S changes from the H level to the L level. Accordingly, the voltage of the first internal node N1 decreases to the L level, the transistor M1 and the transistor M6 are turned to the on state, and the transistor M5 and transistor M7 are turned to the off state. As a result, the voltage of the second internal node N2 changes from the L level to the H level. Also, since the drive-time gate high signal VGH2 in the drive period TD is maintained at the H level, the transistor M4 is turned to the on state. This causes the first output signal OUT1 to change from the L level to the H level. Note that the L level voltage of the first internal node N1 is, more precisely, set to higher level than the gate low voltage VGL functioning as the first constant voltage by an amount equal to the absolute value of the threshold voltage Vtp of the transistor T3. However, as described above, the threshold voltage Vtn (>0) of the N-type transistor M5 in the first output circuit 323 is greater than the absolute value of the threshold voltage Vtp (<0) of the P-type transistor M3 in the first control circuit 311. Thus, the transistor M5 is reliably turned the off state even in the case of a L level voltage of the first internal node N1. The same applies to other embodiments described later (see
At time t12, the first control clock signal CK1 changes from the L level to the H level. This turns the transistor M3 to the off state. Also, at time t12, the set signal S changes from the L level to the H level.
At time t13, the second control clock signal CK2 changes from the H level to the L level. At this time, since the transistor M1 is in the on state, the voltage of the input terminal 33 decreases and the voltage (voltage of the second output signal OUT2) of the second output terminal 39 decreases. Here, since the capacitor C1 is provided between the second internal node N2 and the second output terminal 39, the voltage of the second output terminal 39 decreases and the voltage of the first internal node N1 decreases (the first internal node N1 is put in a boost state). As a result, a high negative voltage is applied to the control terminal of the transistor M1. Via such a bootstrap operation, the voltage of the second output signal OUT2 decreases to a level sufficient to cause the write control transistor T3, which is the connection destination of the second output terminal 39, to be turned to the on state.
At time t14, the second control clock signal CK2 changes from the L level to the H level. Accordingly, the voltage of the input terminal 33 increases and the voltage (voltage of the second output signal OUT2) of the second output terminal 39 increases. When the voltage of the second output terminal 39 increases, the voltage of the first internal node N1 also increases via the capacitor C1.
At time t15, the first control clock signal CK1 changes from the H level to the L level. This turns the transistor M3 to the on state. At this time, the set signal S is maintained at the H level. Accordingly, the voltage of the first internal node N1 increases to the H level, the transistor M1, the transistor M4, and the transistor M6 are turned to the off state, and the transistor M5 and transistor M7 are turned to the on state. This causes the first output signal OUT1 to change from the H level to the L level and the voltage of the second internal node N2 to also change from the H level to the L level. By the voltage of the second internal node N2 changing to the L level, the transistor M2 is turned to the on state.
As for a period before time t11, for a period after time t15, the voltage of the first internal node N1 is maintained at the H level, the voltage of the second internal node N2 is maintained at the L level, the first output signal OUT1 is maintained at the L level, and the second output signal OUT2 is maintained at the H level.
Next, the operations of the unit circuit 3 in the pause period TP (NRF frame period) will be described with reference to
At time t11, the first control clock signal CK1 changes from the H level to the L level, putting the transistor M3 in the on state. Also, at time t11, the set signal S changes from the H level to the L level. Accordingly, as in the drive period TD, the voltage of the first internal node N1 decreases to the L level, the transistor M1 and the transistor M6 are turned to the on state, and the transistor M7 is turned to the off state. At this time, in the output circuit 1, the transistor M5 is turned to the off state, and in the pause period TP, the drive-time gate high signal VGH2 is the L level. Thus, irrespective of the state of the transistor M4, the first output signal OUT1 is maintained at the L level.
At time t12, the first control clock signal CK1 changes from the L level to the H level. This turns the transistor M3 to the off state. Also, at time t12, the set signal S changes from the L level to the H level.
At time t13, the second control clock signal CK2 changes from the H level to the L level. At this time, since the transistor M1 is in the on state, the voltage of the input terminal 33 decreases and the voltage (voltage of the second output signal OUT2) of the second output terminal 39 decreases. Since the capacitor C1 is provided between the second internal node N2 and the second output terminal 39, at this time in the second output circuit 322, a bootstrap operation is performed as in the drive period TD. In other words, the voltage of the second output terminal 39 decreases and the voltage of the first internal node N1 also decreases. As a result, a large negative voltage is applied to the control terminal of the transistor M1, and the voltage of the second output signal OUT2 decreases to a level sufficient to cause the write control transistor T3, which is the connection destination of the second output terminal 39, to be in an on state. At this time, in the output circuit 1, the transistor M4 is turned to the on state and the transistor M5 is in the off state, and in the pause period TP, the drive-time gate high signal VGH2 is the L level. Thus, the first output signal OUT1 is maintained at the L level.
At time t14, the second control clock signal CK2 changes from the L level to the H level. Accordingly, the voltage of the input terminal 33 increases and the voltage (voltage of the second output signal OUT2) of the second output terminal 39 increases. When the voltage of the second output terminal 39 increases, the voltage of the first internal node N1 also increases via the capacitor C1.
At time t15, the first control clock signal CK1 changes from the H level to the L level. This turns the transistor M3 to the on state. At this time, the set signal S is maintained at the H level. Accordingly, the voltage of the first internal node N1 increases to the H level, the transistor M1, the transistor M4, and the transistor M6 are turned to the off state, and the transistor M5 and transistor M7 are turned to the on state. Thus, as for the drive period TD, the voltage of the second internal node N2 also changes from the H level to the L level and the transistor M2 is turned to the on state. In addition, since the transistor M4 is turned to the off state and the transistor M5 is turned to the on state, the first output signal OUT1 is maintained at the L level.
As for a period before time t11, for a period after time t15, the voltage of the first internal node N1 is maintained at the H level, the voltage of the second internal node N2 is maintained at the L level, the first output signal OUT1 is maintained at the L level, and the second output signal OUT2 is maintained at the H level.
As described above, in the pause period TP, the first control circuit 311, the second control circuit 321, and the second output circuit 322 operate as in the drive period TD (see
In the shift register 301 constituting the gate driver (scanning signal line drive circuit) according to the present embodiment, the unit circuits 3 that operate as described above in the drive period TD and the pause period TP are connected in cascade as illustrated in
According to the present embodiment as described above, when the display device using the pixel circuits 15(Pix(i, j)) of the internal compensation method as illustrated in
Accordingly, in each pixel circuit Pix(i, j), in each non-light emission period within the pause period TP, the on-bias voltage Vob is applied to the source terminal of the drive transistor T4 via the corresponding data signal line Dj and the write control transistor T3 (see pixel circuit 15(OB) illustrated in
According to the pause driving of the present embodiment described above, a turn-off operation is performed not only in the RF frame period Trf of the drive period TD but a similar (the same period and the same duty ratio) turn-off operation is also performed in each NRF frame period Tnrf of the pause period TP (see
Also, according to the present embodiment, by using the configuration of the unit circuit 3 constituting the stages of the shift register 301 in the scanning-side drive circuit 40 as illustrated in
Also, in the present embodiment, in the pixel circuit 15, LTPS-TFTs are used in the drive transistor T4, the first and second light emission control transistors T5 and T6, and the write control transistor T3, and an oxide TFT such as IGZO-TFT is used in the threshold compensation transistor T2, the first initialization transistor T1, and the second initialization transistor T7 (see
Next, an organic EL display device according to the second embodiment will be described with reference to
As in the first embodiment, the display device according to the present embodiment is an organic EL display device configured to perform internal compensation and has two operation modes, the normal driving mode and the pause driving mode. In the present embodiment, the configuration of the unit circuit in the shift register constituting the gate driver functioning as a scanning signal line drive circuit is different from that in the first embodiment described above. However, other configurations are the same as those in the first embodiment (
The schematic configuration of the shift register 301 constituting a scanning signal line drive circuit (gate driver) according to the present embodiment is similar to that of the first embodiment described above and as illustrated in
As illustrated in
As illustrated in
Regarding the transistor M8, the control terminal (gate terminal) is connected to the input terminal 33, the first conduction terminal (source terminal) is connected to the fourth internal node N4, and the second conduction terminal (drain terminal) is connected to the first internal node N1. Regarding the transistor M9, the control terminal (gate terminal) is connected to the second internal node N2, the first conduction terminal (source terminal) is connected to the second constant voltage line, and the second conduction terminal (drain terminal) is connected to the fourth internal node N4. Accordingly, the transistor M8 and the transistor M9 are connected in series between the first internal node N1 and the second constant voltage line. Regarding the transistor M10, the control terminal (gate terminal) is connected to the first constant voltage line, the first conduction terminal (drain terminal) is connected to the third internal node N3, and the second conduction terminal (source terminal) is connected to the first internal node N1.
First, the operations of the unit circuit 3 in the drive period TD (RF frame period Trf) will be described with reference to
At time t11, the first control clock signal CK1 changes from the H level to the L level, putting the transistor M3 in the on state. Also, at time t11, the set signal S changes from the H level to the L level. Accordingly, the voltage of the first internal node N1 decreases to the L level, the transistor M6 is turned to the on state, and the transistor M5 and transistor M7 are turned to the off state. As a result, the voltage of the second internal node N2 changes from the L level to the H level. Also, since the drive-time gate high signal VGH2 in the drive period TD is the H level, the transistor M4 is turned to the on state. This causes the first output signal OUT1 to change from the L level to the H level. Since the transistor M10 is maintained in the on state even when the voltage of the first internal node N1 decreases to the L level, the voltage of the third internal node N3 also decreases to the L level. This turns the transistor M1 to the on state.
At time t12, the first control clock signal CK1 changes from the L level to the H level. This turns the transistor M3 to the off state. Also, at time t12, the set signal S changes from the L level to the H level.
At time t13, the second control clock signal CK2 changes from the H level to the L level. At this time, since the transistor M1 is in the on state, the voltage of the input terminal 33 decreases and the voltage (voltage of the second output signal OUT2) of the second output terminal 39 decreases. Here, since the capacitor C1 is provided between the third internal node N3 and the second output terminal 39, the voltage of the second output terminal 39 decreases and the voltage of the third internal node N3 decreases (the third internal node N3 is put in a boost state). As a result, a high negative voltage is applied to the control terminal of the transistor M1. Via such a bootstrap operation, the voltage of the second output signal OUT2 decreases to a level sufficient to cause the write control transistor T3, which is the connection destination of the second output terminal 39, to be turned to the on state. When the voltage of the third internal node N3 decreases at time t13, the voltage of the first conduction terminal (drain terminal) at the transistor M10 becomes less than the voltage of the control terminal (gate terminal). This turns the transistor M10 to the off state. Thus, the voltage of the first internal node N1 does not change at time t13.
At time t14, the second control clock signal CK2 changes from the L level to the H level. Accordingly, the voltage of the input terminal 33 increases and the voltage (voltage of the second output signal OUT2) of the second output terminal 39 increases. When the voltage of the second output terminal 39 increases, the voltage of the third internal node N3 also increases via the capacitor C1. This turns the transistor M10 to the on state.
At time t15, the first control clock signal CK1 changes from the H level to the L level. This turns the transistor M3 to the on state. At this time, the set signal S is maintained at the H level. Accordingly, the voltage of the first internal node N1 increases to the H level, the transistor M4 and the transistor M6 are turned to the off state, and the transistor M5 and transistor M7 are turned to the on state. This causes the first output signal OUT1 to change from the H level to the L level. Also, the voltage of the second internal node N2 also changes from the H level to the L level. This turns the transistors M2 and M9 to the on state. Since the transistor M10 is maintained in the on state, the voltage of the third internal node N3 also increases to the H level at time t15. This turns the transistor M1 to the off state.
As for a period before time t11, for a period after time t15, the voltage of the first internal node N1 and the voltage of the third internal node N3 is maintained at the H level, the voltage of the second internal node N2 is maintained at the L level, the first output signal OUT1 is maintained at the L level, and the second output signal OUT2 is maintained at the H level.
When the unit circuit 3 operates as described above, the pixel circuit 15 operates as in the first embodiment. That is, the N-type transistor and the P-type transistor in the pixel circuit 15 are reliably turned on and off.
The transistors in the unit circuit 3 have a parasitic capacitance. Thus, in the period before time t11 and in the period after time t15, a variation in the voltage of the first internal node N1 and the third internal node N3 may occur due to a clock operation of the second control clock signal CK2 and the presence of the parasitic capacitance of the transistor M1. Thus, a variation in the voltage of the first output signal OUT1 and the second output signal OUT2 may occur. However, in a period before time t11 and a period after time t15, the transistor M9 is maintained in the on state and the transistor M8 turns to the on state each time the second control clock signal CK2 turns to the L level. When both the transistor M8 and the transistor M9 are in the on state, the first internal node N1 is connected to the second constant voltage line for supplying the gate high voltage VGH. Thus, in the period before time t11 and in the period after time t15, the voltage of the first internal node N1 and the third internal node N3 is reliably maintained at the H level even when noise is caused by the clock operation of the second control clock signal CK2.
Note that since the second control clock signal CK2 is the H level in the period from time t11 to time t13, the transistor M8 is maintained in the off state. Accordingly, maintaining the voltage of the fourth internal node N4 at the H level does not affect the voltage of the first internal node N1 and the third internal node N3. Also, since the transistor M9 is in the off state at time t13, the voltage of the fourth internal node N4 changes from the H level to the L level due to the second control clock signal CK2 changing from the H level to the L level. Thereafter, when the transistor M9 turns to the on state at time t15 as described above, the voltage of the fourth internal node N4 changes from the L level to the H level.
Next, the operations of the unit circuit 3 in the pause period TP (NRF frame period) will be described with reference to
The drive-time gate high signal VGH2 is the L level in the pause period TP while in the H level in the drive period TD (see
According to the present embodiment, since the transistor M10 is provided in the unit circuit 3 as illustrated in
Next, an organic EL display device according to the third embodiment will be described with reference to
As in the first embodiment, the display device according to the present embodiment is an organic EL display device configured to perform internal compensation and has two operation modes, the normal driving mode and the pause driving mode. In the present embodiment, the configuration of the unit circuit in the shift register constituting the gate driver functioning as a scanning signal line drive circuit is different from that in the first embodiment described above. However, other configurations are the same as those in the first embodiment (
The schematic configuration of the shift register 301 constituting a scanning signal line drive circuit (gate driver) according to the present embodiment is also similar to that of the first embodiment described above and as illustrated in
As illustrated in
The second control circuit 321 according to the present embodiment includes as a component a P-type transistor (more specifically, a P-type LTPS-TFT) as the transistor M7. This is different from the second control circuit 321 according to the first embodiment described above that includes an N-type transistor (more specifically, an N-type oxide TFT) as the transistor M7. Also, as illustrated in
First, the operations of the unit circuit 3 in the drive period TD (RF frame period Trf) will be described with reference to
At time t11, the first control clock signal CK1 changes from the H level to the L level, putting the transistor M3 in the on state. Also, at time t11, the set signal S changes from the H level to the L level. Accordingly, the voltage of the first internal node N1 decreases to the L level, the transistor M1 is turned to the on state, and the transistor M5 is turned to the off state. However, the L level voltage of the first internal node N1 at this time is, more precisely, set to higher level than the gate low voltage VGL functioning as the first constant voltage by an amount equal to the absolute value of the threshold voltage Vtp (<0) of the transistor T3 (see
At time t12, the first control clock signal CK1 changes from the L level to the H level. This turns the transistor M3 to the off state. Also, at time t12, the set signal S changes from the L level to the H level, but since the transistor M3 turns to the off state, the voltage of the first internal node N1 is maintained at the L level. Thus, the transistor M6 turns to the on state, and the voltage of the second internal node N2 changes from the L level to the H level.
At time t13, the second control clock signal CK2 changes from the H level to the L level. At this time, since the transistor M1 is in the on state, the voltage of the input terminal 33 decreases and the voltage (voltage of the second output signal OUT2) of the second output terminal 39 decreases. Accordingly, the voltage of the first internal node N1 also decreases (the first internal node N1 is put in a boost state) via the capacitor C1 between the second internal node N2 and the second output terminal 39. As a result, a high negative voltage is applied to the control terminal of the transistor M1. Via such a bootstrap operation, the voltage of the second output signal OUT2 decreases to a level sufficient to cause the write control transistor T3, which is the connection destination of the second output terminal 39, to be turned to the on state.
At time t14, the second control clock signal CK2 changes from the L level to the H level. Accordingly, the voltage of the input terminal 33 increases and the voltage (voltage of the second output signal OUT2) of the second output terminal 39 increases. When the voltage of the second output terminal 39 increases, the voltage of the first internal node N1 also increases via the capacitor C1.
At time t15, the first control clock signal CK1 changes from the H level to the L level. This turns the transistor M3 to the on state. At this time, the set signal S is maintained at the H level. Accordingly, the voltage of the first internal node N1 increases to the H level, the transistor M1, the transistor M4, and the transistor M6 are turned to the off state, and the transistor M5 and transistor M7 are turned to the on state. This causes the first output signal OUT1 to change from the H level to the L level and the voltage of the second internal node N2 to also change from the H level to the L level. This turns the transistor M2 to the on state. Note that, the L level voltage of the second internal node N2 at this time is, more precisely, a higher voltage than the gate low voltage VGL functioning as the first constant voltage by an amount equal to the threshold voltage (absolute value) of the transistor M6 (see
As for a period before time t11, for a period after time t15, the voltage of the first internal node N1 is maintained at the H level, the voltage of the second internal node N2 is maintained at the L level, the first output signal OUT1 is maintained at the L level, and the second output signal OUT2 is maintained at the H level.
As can be seen from the foregoing, the operations (see
Next, the operations in the pause period TP (NRF frame period) of the unit circuit 3 according to the present embodiment will be described.
In the present embodiment also, the drive-time gate high signal VGH2 is the L level in the pause period TP while in the H level in the drive period TD (see
As can be seen from the foregoing, the operations in the pause period TP of the unit circuit 3 according to the present embodiment are essentially the same as the operations in the pause period TP of the unit circuit 3 according to the first embodiment described above, and the first and second output signals generated in both embodiments are the same (see
As described above, the display device according to the present embodiment using the unit circuit 3 as described above also operates substantially in the same manner as the display device according to the first embodiment described above. Accordingly, the present embodiment and the first embodiment described above obtained similar effects.
Also, as illustrated in
Next, an organic EL display device according to the fourth embodiment will be described with reference to
As in the first embodiment, the display device according to the present embodiment is an organic EL display device configured to perform internal compensation and has two operation modes, the normal driving mode and the pause driving mode. In the present embodiment, the configuration of the unit circuit in the shift register constituting the gate driver functioning as a scanning signal line drive circuit is different from that in the first embodiment described above. However, other configurations are the same as those in the first embodiment (
Configurations of the display device according to the present embodiment that are the same as configurations of the first embodiment or including corresponding portions are assigned the same reference sign and detailed descriptions of those components are omitted. The present embodiment will be described below with a focus on the configuration and operations of the unit circuit in the shift register 301.
The schematic configuration of the shift register 301 constituting a scanning signal line drive circuit (gate driver) according to the present embodiment is also similar to that of the first embodiment described above and as illustrated in
As illustrated in
Thus, the unit circuit 3 according to the present embodiment has the configuration of the unit circuit 3 according to the first embodiment, includes the third control circuit 312 according to the second embodiment, and includes the second control circuit 321 according to the third embodiment in place of the second control circuit 321. Herein, portions of the configuration relating to the third control circuit 312 according to the present embodiment that are the same as that in the second control circuit 321 according to the second embodiment described above are given the same reference signs and descriptions thereof are omitted. Also, portions of the configuration relating to the second control circuit 321 according to the present embodiment that are the same as that in the second control circuit 321 according to the third embodiment described above are given the same reference signs and descriptions thereof are omitted (see
First, the operations of the unit circuit 3 in the drive period TD (RF frame period Trf) will be described with reference to
When signals CK1, CK2, S, and VGH2 that change in a similar manner as in the unit circuit 3 according to the first to third embodiments from time t11 to time t15 in the drive period TD are input to the unit circuit 3 according to the present embodiment (
In the present embodiment also, the drive-time gate high signal VGH2 is the L level in the pause period TP while in the H level in the drive period TD (see
As described above, the display device according to the present embodiment using the unit circuit 3 as described above also operates substantially in the same manner as the display device according to the first embodiment described above. Accordingly, the present embodiment and the first embodiment described above obtained similar effects.
As described above, the unit circuit (
Furthermore, the second control circuit 321 provided in the unit circuit (
The disclosure is not limited to each of the embodiments described above, and various modifications may be made without departing from the scope of the disclosure. For example, the following modified example can be considered.
In each of the embodiments described above, the pixel circuit 15 and the unit circuit in the scanning-side drive circuit 40 include both a P-type transistor and an N-type transistor. Typically, LTPS-TFT with high mobility is used for a P-type transistor, and an oxide TFT such as IGZO-TFT with good off-leakage characteristics is used for an N-type transistor. However, the disclosure is not limited to these TFTs, and the channel of the transistor to be used may be changed as appropriate between the P-type and the N-type, with the transistors being configured to operate in a similar manner. For example, in each embodiment, a configuration in which an N-type LTPS-TFT is used instead of the P-type LTPS-TFT may be employed.
In each embodiment described above, the pixel circuit 15 configured as illustrated in
In the above description, an organic EL display device has been described as an example and embodiments have been given. However, the disclosure is not limited to an organic EL display device and may be applied to any display device that employs an internal compensation method using a display element driven by a current and that performs pause driving. The display element that can be used in such a configuration includes, for example, an organic EL element, that is, an organic light-emitting diode (OLED), or an inorganic light-emitting diode, a quantum dot light-emitting diode (QLED) or the like.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2020/037432 | 10/1/2020 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2022/070386 | 4/7/2022 | WO | A |
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| Number | Date | Country |
|---|---|---|
| 2017227880 | Dec 2017 | JP |
| 2020112795 | Jul 2020 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20230368730 A1 | Nov 2023 | US |
