Patent Grant
11398187
The disclosure relates to a display device, and more particularly to a current-driven display device including a display element driven by a current, such as an organic electro luminescence (EL) display device, and a method for driving the display device.
The last few years have seen the implementation of organic EL display devices provided with a pixel circuit including organic EL elements (also referred to as organic light-emitting diodes (OLEDs)). The pixel circuit in such an organic EL display device includes a drive transistor, a write control transistor, and a holding capacitor in addition to the organic EL elements. A thin film transistor is used for the drive transistor and the write control transistor. The holding capacitor is connected to a gate terminal that serves as a control terminal of the drive transistor. A voltage corresponding to an image signal representing an image to be displayed (more specifically, a voltage indicating the gradation values of pixels to be formed by the pixel circuit, hereinafter referred to as “data voltage”) is applied to the holding capacitor from the drive circuit via a data signal line. The organic EL element is a self-luminous display element that emits light with luminance according to an electric current flowing through the organic EL element. The drive transistor is connected to the organic EL element in series and controls the electric current passing through the organic EL element according to a voltage held by the holding capacitor.
Variation and fluctuation occur in characteristics of the organic EL element and the drive transistor. Thus, variation and fluctuation in characteristics of these elements need to be compensated in order to perform higher picture quality display in the organic EL display device. For the organic EL display device, a method for compensating a characteristic of an element inside a pixel circuit and a method for compensating a characteristic of an element outside a pixel circuit are known. One known pixel circuit corresponding to the former method is a pixel circuit configured to charge the holding capacitor with the data voltage via the drive transistor in a diode-connected state after initializing voltage at the gate terminal of the drive transistor, that is, the voltage held in the holding capacitor. In such a pixel circuit, variation and fluctuation of the threshold voltage in the drive transistor are compensated for within the pixel circuit (hereinafter, the compensation of variation and fluctuation of threshold voltage is referred to as “threshold compensation”).
As described above, an item associated with an organic EL display device that employs a method of threshold compensation in a pixel circuit (hereinafter referred to as an “internal compensation method”) is described in PTL 1 and 2. More specifically, in the pixel circuit of the light-emitting apparatus disclosed in PTL 1, the anode of a light-emitting element (organic EL element) is connected to the source of an N-channel drive transistor, the cathode of the light-emitting element is connected to the potential line of a low potential-side potential VCT, and a holding capacitor is interposed between the gate and the source of the drive transistor (
In the organic EL device described in PTL 2, the drain of a P-channel drive transistor is connected to a pixel electrode (anode) of an organic EL element via a light emission control transistor, the potential line of a low-power supply potential VCT is connected to the counter electrode (cathode) of the organic EL element, and a capacitor is interposed between the gate and the source of the drive transistor. Further, a transistor is disposed as a switching element between the gate and the drain of the drive transistor, and a discharge control transistor is disposed between the drain and a supply line 115 (
PTL 1: JP 2011-33678 A
PTL 2: JP 2010-262251 A
In an organic EL display device employing an internal compensation method, when the pixel circuit is configured as described above to write a data voltage to the holding capacitor via the drive transistor in a diode-connected state after initializing the voltage of the gate terminal of the drive transistor (corresponding to the holding voltage of the holding capacitor), a bright dot that is not included in the intended display content in the display image (hereinafter referred to as a “bright dot defect”) may occur.
Because of this, there is a need to display a good-quality image with no bright dot defect in a current-driven display device such as an organic EL display device employing an internal compensation method.
A display device including a plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data signal lines, a plurality of light emission control lines individually corresponding to the plurality of scanning signal lines, and a plurality of pixel circuits arranged in a matrix along the plurality of data signal lines and the plurality of scanning signal lines, the display device including:
first and second power source lines;
an initialization voltage supply circuit;
a data signal line drive circuit configured to drive the plurality of data signal lines;
a scanning signal line drive circuit configured to selectively drive the plurality of scanning signal lines; and
a light emission control circuit configured to drive the plurality of light emission control lines,
each pixel circuit including:
a display element driven by a current;
a holding capacitor configured to hold a voltage used for controlling a drive current of the display element;
a drive transistor configured to control a drive current of the display element according to a voltage held by the holding capacitor;
a write control switching element;
a threshold compensation switching element;
first and second light emission control switching elements; and
first and second initialization switching elements,
in which a first conduction terminal of the drive transistor is connected to any one of the plurality of data signal lines via the write control switching element, and the first power source line via the first light emission control switching element,
a second conduction terminal of the drive transistor is connected to a first terminal of the display element via the second light emission control switching element,
a control terminal of the drive transistor is connected to the first power source line via the holding capacitor, the second conduction terminal via the threshold compensation switching element, and a first conduction terminal of the first initialization switching element,
the first terminal of the display element is connected to a first conduction terminal of the second initialization switching element, and a second terminal of the display element is connected to the second power source line,
the first initialization switching element is controlled to an on state when a holding voltage of the holding capacitor is to be initialized, the second initialization switching element is controlled to an on state when the first terminal of the display element is to be initialized, and the first initialization transistor is controlled to an off state when the display element is to be driven based on the holding voltage of the holding capacitor,
in the initialization voltage supply circuit,
a first initialization voltage is supplied to a second conduction terminal of the first initialization switching element when the holding voltage of the holding capacitor is to be initialized, and
a second initialization voltage is supplied to a second conduction terminal of the second initialization switching element when the first terminal of the display element is to be initialized, and
when the display element is to be driven based on the holding voltage of the holding capacitor, voltage is supplied to the second conduction terminal of the first initialization switching element such that an absolute value of a difference between a voltage of the second conduction terminal of the first initialization switching element and a voltage of the second power source line is larger than an absolute value of a difference between the second initialization voltage and a voltage of the second power source line.
A display device according to several other embodiments of the disclosure is a display device including a plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data signal lines, a plurality of light emission control lines individually corresponding to the plurality of scanning signal lines, and a plurality of pixel circuits arranged in a matrix along the plurality of data signal lines and the plurality of scanning signal lines, the display device including:
first and second power source lines;
first and second initialization voltage lines;
a data signal line drive circuit configured to drive the plurality of data signal lines;
a scanning signal line drive circuit configured to selectively drive the plurality of scanning signal lines; and
a light emission control circuit configured to drive the plurality of light emission control lines,
each pixel circuit comprising:
a display element driven by a current;
a holding capacitor configured to hold a voltage used for controlling a drive current of the display element;
a drive transistor configured to control a drive current of the display element according to a voltage held by the holding capacitor;
a write control switching element;
a threshold compensation switching element;
first and second light emission control switching elements; and
first and second initialization switching elements,
in which a first conduction terminal of the drive transistor is connected to any one of the plurality of data signal lines via the write control switching element, and the first power source line via the first light emission control switching element,
a second conduction terminal of the drive transistor is connected to a first terminal of the display element via the second light emission control switching element,
a control terminal of the drive transistor is connected to the first power source line via the holding capacitor, the second conduction terminal via the threshold compensation switching element, and the first initialization voltage line via the first initialization switching element,
the first terminal of the display element is connected to the second initialization voltage line via the second initialization switching element, and a second terminal of the display element is connected to the second power source line, and
the first initialization switching element is controlled to an on state when the holding voltage of the holding capacitor is to be initialized, and the second initialization switching element is controlled to an on state when the first terminal of the display element is to be initialized.
A method for driving a display device according to several other embodiments of the disclosure is a method for driving a display device including a plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data signal lines, a plurality of light emission control lines individually corresponding to the plurality of scanning signal lines, first and second power source lines, and a plurality of pixel circuits arranged in a matrix along the plurality of data signal lines and the plurality of scanning signal lines, the method for driving a display device including:
supplying a voltage used for initialization to each pixel circuit,
each pixel circuit comprising:
a display element driven by a current;
a holding capacitor configured to hold a voltage used for controlling a drive current of the display element;
a drive transistor configured to control a drive current of the display element according to a voltage held by the holding capacitor;
a write control switching element;
a threshold compensation switching element;
first and second light emission control switching elements; and
first and second initialization switching elements,
in which a first conduction terminal of the drive transistor is connected to any one of the plurality of data signal lines via the write control switching element, and the first power source line via the first light emission control switching element,
a second conduction terminal of the drive transistor is connected to a first terminal of the display element via the second light emission control switching element,
a control terminal of the drive transistor is connected to the first power source line via the holding capacitor, the second conduction terminal via the threshold compensation switching element, and a first conduction terminal of the first initialization switching element,
the first terminal of the display element is connected to a first conduction terminal of the second initialization switching element, and a second terminal of the display element is connected to the second power source line,
the first initialization switching element is controlled to an on state when a holding voltage of the holding capacitor is to be initialized, the second initialization switching element is controlled to an on state when the first terminal of the display element is to be initialized, and the first initialization transistor is controlled to an off state when the display element is to be driven based on the holding voltage of the holding capacitor,
the initialization voltage supply step includes:
supplying a first initialization voltage to a second conduction terminal of the first initialization switching element when the holding voltage of the holding capacitor is to be initialized,
supplying a second initialization voltage to a second conduction terminal of the second initialization switching element when the first terminal of the display element is to be initialized, and
when the display element is to be driven based on the holding voltage of the holding capacitor, supplying voltage to the second conduction terminal of the first initialization switching element such that an absolute value of a difference between a voltage of the second conduction terminal of the first initialization switching element and a voltage of the second power source line is larger than an absolute value of a difference between the second initialization voltage and a voltage of the second power source line.
In some of the above-described embodiments of the disclosure, the pixel circuit is configured such that voltage of the data signal line is applied to the holding capacitor as data voltage via the drive transistor put into a diode-connected state by the threshold compensation switching element, and the holding voltage of the holding capacitor is initialized before the data voltage is written in this way. To perform this initialization, the control terminal of the drive transistor (corresponding to one terminal of the holding capacitor) is connected to the first conduction terminal of the first initialization switching element, and the first initialization voltage is applied to the second conduction terminal. Further, in this pixel circuit, the voltage of the first terminal of the display element is initialized before the display element is driven according to the holding voltage of the holding capacitor (before the lighting operation). For this initialization, the first terminal of the display element is connected to the first conduction terminal of the second initialization switching element, and the second initialization voltage is applied to the second conduction terminal. On the other hand, during the lighting operation in which the display element is driven according to the holding voltage of the holding capacitor, that is, in a light emission period, voltage is supplied to the second conduction terminal of the first initialization switching element such that an absolute value of a difference between the voltage of the second conduction terminal and the voltage of the second power source line is larger than an absolute value of a difference between the second initialization voltage and the voltage of the second power source line. Thus, compared to a known pixel circuit in which a voltage corresponding to the second initialization voltage is fixedly applied to the second conduction terminals of both the first and second initialization switching elements, less voltage is applied between the first conduction terminal and the second conduction terminal of the first initialization switching element in the off state during the light emission period. This reduces leakage current of the first initialization switching element in the off state connected to the control terminal of the drive transistor (one terminal of the holding capacitor). Because of this, it is possible to reduce a voltage drop at the control terminal of the drive transistor caused by leakage current of the transistor in the off state during the light emission period without increasing the size of the first initialization switching element. Thus, it is possible to provide a pixel circuit that has a threshold compensation function and in which no bright dot defect (a bright dot not included in the intended display content) occurs due to leakage current.
In some other embodiments of the disclosure, in a pixel circuit including a threshold compensation function similar to that described above, the control terminal of the drive transistor is connected to the first conduction terminal of the first initialization switching element for initialization of the holding voltage of the holding capacitor (initialization of the voltage of the control terminal of the drive transistor) performed before the data voltage is written. The first terminal of the display element is connected to the first conduction terminal of the second initialization switching element to initialize the voltage of the first terminal of the display element before the display element is to be driven according to the holding voltage of the holding capacitor (prior to the lighting operation). In some other embodiments, the first initialization voltage line is connected to the second conduction terminal of the first initialization switching element, and the second initialization voltage line is connected to the second conduction terminal of the second initialization switching element. Because of this, an initialization voltage different from the initialization voltage to be applied to the first terminal of the display element can be fixedly applied to the control terminal of the drive transistor. Thus, compared to a known pixel circuit in which a voltage corresponding to the second initialization voltage is fixedly applied to the second conduction terminals of both the first and second initialization switching elements, less voltage is applied between the first conduction terminal and the second conduction terminal of the first initialization switching element in the off state during the light emission period. Thus, the other embodiments described above can also achieve a similar effect to the embodiments described above because it is possible to reduce a voltage drop at the control terminal of the drive transistor caused by leakage current of the transistor in the off state during the light emission period without increasing the size of the first initialization switching element.
In the following, each embodiment will be described with reference to the accompanying drawings. Note that in each of the transistors referred to below, the gate terminal corresponds to a control terminal, one of the drain terminal and the source terminal corresponds to a first conduction terminal, and the other corresponds to a second conduction terminal. All the transistors in each embodiment are described as P-channel transistors, but the disclosure is not limited thereto. Furthermore, the transistor in each embodiment is, for example, a thin film transistor, but the disclosure is not limited thereto. Still further, the term “connection” used herein means “electrical connection” unless otherwise specified, and without departing from the spirit and scope of the disclosure, the term includes not only a case in which direct connection is meant but also a case in which indirect connection with another element therebetween is meant.
As illustrated in
The display portion 11 is provided with m (m is an integer of 2 or greater) data signal lines D1 to Dm and n+1 (n is an integer of 2 or greater) scanning signal lines G0 to Gn that intersect the data signal lines D1 to Dm, and n light emission control lines (also referred to as “emission lines”) E1 to En disposed along the n scanning signal lines G1 to Gn, respectively. As illustrated in
The display portion 11 is also provided with a power source line (not illustrated) common to each pixel circuit 15. In other words, a power source line (hereinafter, referred to as a “high-level power source line” and designated by the reference sign “ELVDD” similar to the high-level power supply voltage) used for supplying the high-level power supply voltage ELVDD for driving the organic EL element described later, and a power source line (hereinafter, referred to as a “low-level power source line” and designated by the reference sign “ELVSS” similar to the low-level power supply voltage) used for supplying the low-level power supply voltage ELVSS for driving the organic EL element are provided. The display portion 11 also includes first and second initialization voltage lines (not illustrated and denoted by the reference signs “Vini1” and “Vini2” similar to the first and second initialization voltages, respectively) used for supplying the first and second initialization voltages Vini1 and Vini2, which are two fixed voltages used in a reset operation for initializing each pixel circuit 15 (details described later). The high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the first and second initialization voltages Vini1 and Vini2 are supplied from the power source circuit 50 illustrated in
The display control circuit 20 receives an input signal Sin including image information representing an image to be display and timing control information for image display from outside of the display device 10 and, based on the input signal Sin, generates a data-side control signal Scd and a scanning-side control signal Scs, and outputs the data-side control signal Scd to the data-side drive circuit (data signal line drive circuit) 30 and outputs the scanning-side control signal Scs to the scanning-side drive circuit (scanning signal line drive/light emission control circuit) 40.
The data-side drive circuit 30 drives the data signal lines D1 to Dm based on the data-side control signal Scd output from the display control circuit 20. More specifically, the data-side drive circuit 30 outputs in parallel m data signals D(1) to D(m) representing an image to be displayed, and applies the data signals D(1) to D(m) to the data signal lines D1 to Dm, respectively, based on the data-side control signal Scd.
The scanning-side drive circuit 40 functions as a scanning signal line drive circuit that drives the scanning signal lines G0 to Gn and a light emission control circuit that drives the light emission control lines E1 to En based on the scanning-side control signal Scs output from the display control circuit 20. More specifically, when functioning as the scanning signal line drive circuit, the scanning-side drive circuit 40 sequentially selects the scanning signal lines G0 to Gm in individual frame periods based on the scanning-side control signal Scs, and applies an active signal (low-level voltage) to a selected scanning signal line Gk and an inactive signal (high-level voltage) to the unselected scanning signal lines. With this, m pixel circuits Pix(k, 1) to Pix(k, m) corresponding to the selected scanning signal line Gk (1≤k≤n) are collectively selected. As a result, in the select period of the scanning signal line Gk (hereinafter referred to as a “kth scanning select period”), the voltages of the m data signals D(1) to D(m) applied to the data signal lines D1 to Dm from the data-side drive circuit 30 (hereinafter also referred to as simply “data voltages” when not distinguished from each other) are written as pixel data to the pixel circuits Pix(k, 1) to Pix(k, m), respectively.
When functioning as the light emission control circuit, based on the scanning-side control signal Scs, the scanning-side drive circuit 40 applies a light emission control signal (high-level voltage) indicating non-light emission to an ith light emission control line Ei in an i-1th horizontal period and an ith horizontal period, and applies a light emission control signal (low-level voltage) indicating light emission to the ith light emission control line Ei in other periods. Organic EL elements in pixel circuits (hereinafter also referred to as “ith row pixel circuits”) Pix(i, 1) to Pix(i, m) corresponding to the ith scanning signal line Gi emit light at luminance corresponding to the data voltages written to the ith row pixel circuits Pix(i, 1) to Pix(i, m), respectively, while the voltage of the light emission control line Ei is at a low level.
Prior to describing the configuration and operation of the pixel circuit 15 in the present embodiment, the configuration and operation of a pixel circuit 15a in a known organic EL display device (hereinafter referred to as a “known example”) as a pixel circuit for comparison with the pixel circuit 15 will be described with reference to
In the pixel circuit 15a, a scanning signal line corresponding to the pixel circuit 15a (hereinafter also referred to as a “corresponding scanning signal line” in the description focusing on the pixel circuit) Gi, a scanning signal line immediately before the corresponding scanning signal line Gi (a scanning signal line immediately before the scanning signal lines G1 to Gn in scanning order, hereinafter also referred to as a “preceding scanning signal line” in the description focusing on the pixel circuit) Gi−1, a light emission control line corresponding to the preceding scanning signal line (hereinafter also referred to as a “corresponding light emission control line” in the description focusing on the pixel circuit) Ei, a data signal line corresponding to the corresponding light emission control line Ei (hereinafter also referred to as a “corresponding data signal line” in the description focusing on the pixel circuit) Dj, the initialization voltage line Vini, the high-level power source line ELVDD, and the low-level power source line ELVSS are connected to each other.
As illustrated in
The drive transistor M1 operates in a saturation region. A drive current I1 flowing through the organic EL element OLED in the light emission period is given by Equation (1) below. A gain β of the drive transistor M1 included in Equation (1) is given by Equation (2) below.
I1=(β/2)(|Vgs|−|Vth|)2=(β/2)(|Vg−ELVDD|−|Vth|)2 (1)
β=μ×(W/L)×Cox (2)
In Equations (1) and (2), Vth, μ, W, L, and Cox represent the threshold voltage, mobility, gate width, gate length, and gate insulating film capacitance per unit area of the drive transistor M1, respectively.
In the ith row, jth column pixel circuit Pix(i, j), when the voltage of the light emission control line Ei changes from the low level to the high level at the time t1 as illustrated in
At the time t2, the voltage of the preceding scanning signal line Gi−1 changes from the high level to the low level, which causes the preceding scanning signal line Gi−1 to enter a select state. Due to this change, the first initialization transistor M4 enters an on state. Thus, the voltage of the gate terminal of the drive transistor M1, i.e., the gate voltage Vg is initialized to the initialization voltage Vini. The initialization voltage Vini is such a voltage that the voltage can keep the drive transistor M1 in an on state during the writing of the data voltage to the pixel circuit Pix(i, j). More specifically, the initialization voltage Vini satisfies Equation (3) below.
|Vini−Vdata|>|Vth| (3),
where Vdata represents the data voltage (voltage of the corresponding data signal line Dj), and Vth represents the threshold voltage of the drive transistor M1. Further, because the drive transistor M1 in the present embodiment is a P-channel transistor,
Vini<Vdata (4).
By initializing the gate voltage Vg to the initialization voltage Vini in such a way, the data voltage can be reliably written to the pixel circuit Pix(i, j). Note that the initialization of the gate voltage Vg is also the initialization of the holding voltage of the holding capacitor C1.
The period from the time t2 to the time t3 is a reset period in the ith row pixel circuits Pix(i, 1) to Pix(i, m). In the pixel circuit Pix(i, j), the gate voltage Vg is initialized by the first initialization transistor M4 being in the on state in the reset period as described above.
At the time t3, the voltage of the preceding scanning signal line Gi−1 changes to the high level, which causes the preceding scanning signal line Gi−1 to enter a non-select state. Therefore, the first initialization transistor M4 changes to an off state. During the period from the time t3 to the start time t4 of the ith scanning select period, the data-side drive circuit 30 starts to apply the data signal D(j) to the data signal line Dj as the data voltage of the ith row, jth column pixel, and continues to apply the data signal D(j) at least until the end time t5 of the ith scanning select period.
At the time t4, the voltage of the corresponding scanning signal line Gi changes from the high level to the low level, which causes the corresponding scanning signal line Gi to enter a select state. Because of this, the write control transistor M2 changes to the on state. The threshold compensation transistor M3 also changes to the on state, and hence the drive transistor M1 is in a state in which the gate terminal and the drain terminal of the drive transistor M1 are connected, i.e., in a diode-connected state. As a result, the voltage of the corresponding data signal line Dj, i.e., the voltage of the data signal D(j) is applied to the holding capacitor C1 as the data voltage Vdata via the drive transistor M1 in the diode-connected state. As a result, as illustrated in
Vg(i,j)=Vdata−|Vth| (5)
At the time t4, the voltage of the corresponding scanning signal line Gi changes from the high level to the low level, which causes the second initialization transistor M7 to change to the on state. As a result, accumulated charge in the parasitic capacitance of the organic EL element OLED is discharged and the anode voltage Va of the organic EL element is initialized to the initialization voltage Vini (see
The period from the time t4 to the time t5 is a data write period in the ith row pixel circuits Pix(i, 1) to Pix(i, m). In the pixel circuit Pix(i, j), a data voltage that has undergone threshold compensation is written to the holding capacitor C1 in the data write period, and the gate voltage Vg(i, j) is the value given by Equation (5) above.
Then, at the time t6, the voltage of the light emission control line Ei changes to a low level. Accordingly, the first and second light emission control transistors M5 and M6 change to the on state. Thus, after the time t6, the current I1 flows from the high-level power source line ELVDD to the low-level power source line ELVSS via the first light emission control transistor M5, the drive transistor M1, the second light emission control transistor M6, and the organic EL element OLED. This current I1 is given by Equation (1) above. Considering that the drive transistor M1 is a P-channel transistor and ELVDD>Vg, the current I1 is given by Equations (1) and (5) above.
As described above, after the time t6, the organic EL element OLED emits light at a luminance corresponding to the data voltage Vdata, which is the voltage of the corresponding data signal line Dj in an ith scanning select period, regardless of the threshold voltage Vth of the drive transistor M1.
As described above, a display device such as that in the known example described above, i.e., a display device employing a pixel circuit configured to write a data voltage to a holding capacitor via a drive transistor in a diode-connected state after initializing the gate voltage of the drive transistor has a problem in that a bright dot defect occurs in the display image. The present inventors studied the operation of the pixel circuit 15a in the known example to find the cause of the bright dot defect. Now, the results of this study will be described.
In the pixel circuit 15a (Pix(i, j)) in the known example described above, the voltage of the corresponding data signal line Dj is applied to the holding capacitor C1 as the data voltage Vdata via the drive transistor M1 in the diode-connected state, thereby compensating for variation and fluctuation in the threshold voltage Vth of the drive transistor M1. In a pixel circuit employing such an internal compensation method, initialization of the gate voltage Vg of the drive transistor M1, i.e., initialization of the holding voltage of the holding capacitor C1, needs to be performed before the data write operation. Thus, as illustrated in
When the pixel circuit 15a in the known example is to create a black display, in the data write period, a high voltage near the high-level power supply voltage ELVDD is applied to the gate terminal of the drive transistor M1 as the data voltage Vdata via the drive transistor M1 in the diode-connected state, and, in the light emission period, the gate voltage Vg is maintained at the high voltage by the holding capacitor C1. Thus, in the light emission period, a relatively high voltage (e.g., approximately 8 V) is continuously applied between the source and drain of the first initialization transistor M4 in the off state. As a result, leakage current may occur in the first initialization transistor M4, which may cause the gate voltage Vg to drop. If this occurs, an amount of current that does not correspond to the value of the written data voltage flows to the drive transistor M1 and the organic EL element OLED, and this generates a bright dot (bright dot defect) not included in the intended display content. A bright dot defect is particularly likely to occur when the off resistance of the first initialization transistor M4 decreases or the threshold voltage (absolute value) of the drive transistor M1 decreases due to manufacturing variation.
Using a transistor with a multi-gate structure, a transistor having a long channel length, or two transistors connected to each other in series as the first initialization transistor M4 has also been considered to minimize the occurrence of a bright dot defect. However, using such transistors increases the size of the first initialization transistor M4 and makes it difficult to achieve compact a pixel circuit.
Next, the configuration and operation of the pixel circuit 15 in the present embodiment will be described with reference to
As illustrated in
As illustrated in
Also in the present embodiment, in the ith row, jth column pixel circuit Pix(i, j), when the voltage of the light emission control line Ei changes from the low level to the high level at the time t1 as illustrated in
At the time t2, the voltage of the preceding scanning signal line Gi−1 changes from the high level to the low level, which causes the preceding scanning signal line Gi−1 to enter a select state. Therefore, the first initialization transistor M4 enters an on state.
The period from the time t2 to the time t3 is a reset period in the ith row pixel circuits Pix(i, 1) to Pix(i, m).
However, the initialization of the gate voltage Vg in the present embodiment differs from initialization in the known example in which the same initialization voltage Vini is applied to the gate terminal of the drive transistor M1 and the anode electrode of the organic EL element OLED, in that the voltage Vini1 different to the voltage Vini2 used to initialize the anode electrode of the organic EL element OLED is applied to the gate terminal of the drive transistor M1. In other words, in the present embodiment, initialization of the gate voltage Vg is performed by applying the voltage of the first initialization voltage line Vini1 to the gate terminal of the drive transistor M1 as the first initialization voltage Vini1 via the first initialization transistor M4 (see
Vini1>Vini2 (7)
|Vini1−Vdata|>|Vth| (8)
Vini1<Vdata (9)
Note that Equations (7) to (9) above assume that the drive transistor M1 is a P-channel transistor. More generally, the first initialization voltage Vini1 is selected to satisfy Expressions (10) and (11) below. When the drive transistor M1 is a P-channel transistor, Vini1<Vdata, and when the drive transistor M1 is an N-channel transistor, Vini1>Vdata.
|Vini1−ELVSS|>|Vini2−ELVSS| (10)
|Vini1−Vdata|>|Vth| (11)
Expression (10) above represents the condition that the first initialization voltage Vini1 should satisfy using the low-level power supply voltage ELVSS, but this condition may be indicated using the high-level power supply voltage ELVDD. In other words, Expression (12) below may be used instead of Expression (10), and the first initialization voltage Vini1 may be selected to satisfy Expressions (12) and (11).
|ELVDD−Vini1|<|ELVDD−Vini2| (12)
At the time t3, as illustrated in
At the time t4, as illustrated in
The period from the time t4 to the time t5 is a data write period in the ith pixel circuits Pix(i, 1) to Pix(i, m). In the data write period, the write control transistor M2 and the threshold compensation transistor M3 are in an on state as described above.
At the time t5, which is the end time of the ith scanning select period as the data write period, the voltage of the corresponding scanning signal line Gi changes to the high level. As a result, the write control transistor M2, the threshold compensation transistor M3, and the second initialization transistor M7 change to the off state.
Then, at the time t6, the voltage of the light emission control line Ei changes to a low level. Thus, the first and second light emission control transistors M5 and M6 change to the on state. The time after the time t6 is a light emission period. In this light emission period, in the pixel circuit Pix(i, j), the first and second light emission control transistors M5 and M6 are in an on state as described above, and the write control transistor M2, the threshold compensation transistor M3, the first initialization transistor M4, and the second initialization transistor M7 are in the off state.
In the present embodiment as described above, similar to the known example, in the pixel circuit Pix(i, j), the voltage of the corresponding data signal line Dj is applied to the holding capacitor C1 as the data voltage Vdata via the drive transistor M1 in the diode-connected state, thereby compensating for variations and fluctuations in the threshold voltage of the drive transistor M1. In order to write data along with this threshold compensation, the gate voltage Vg of the drive transistor M1 needs to be initialized (initialization of the holding voltage of the holding capacitor C1) prior to the data write operation. The voltage for initializing the gate voltage Vg is applied to the gate terminal of the drive transistor M1 via the first initialization transistor M4, similar to the known example (see
However, the present embodiment differs from the known example (
According to the present embodiment, the gate voltage Vg of the drive transistor M1 is initialized with the first initialization voltage Vini1 that is higher than the second initialization voltage Vini2 of the anode voltage Va of the organic EL element OLED and the initialization voltage Vini of the gate voltage Vg in the known example (
Note that in the pixel circuit 15, the threshold compensation transistor M3 is connected to the gate terminal of the drive transistor M1 (one terminal of the holding capacitor C1) in addition to the first initialization transistor M4, and hence leakage current of the threshold compensation transistor M3 is also considered as leakage current that may lead to a decrease in the gate voltage Vg during the light emission period. However, in the light emission period, the anode voltage Va of the organic EL element OLED is higher than the voltage of the second initialization voltage line Vini2 by at least several volts, and the second light emission control transistor M6 is in the on state. Because of this, the voltage applied between the source and drain of the threshold compensation transistor M3 in the off state in the light emission period is a relatively small voltage corresponding to the difference between the gate voltage Vg of the drive transistor M1 and the anode voltage Va, and reduction of the gate voltage Vg due to leakage current of the threshold compensation transistor M3 is not a problem.
In the pixel circuit 15 according to the first embodiment, the gate terminal of the second initialization transistor M7 is connected to the corresponding scanning signal line Gi, but may be connected to the preceding scanning signal line Gi−1 instead. A display device including a pixel circuit having such a configuration will be described below as a modification example of the first embodiment.
The present modification example differs from the first embodiment in terms of operation for initializing the anode voltage Va as described above, but other operations are the same as those of the first embodiment (see
Note that in the first embodiment and the modification example, the low-level power supply voltage ELVSS can be selected as the second initialization voltage Vini2. In this case, the low-level power source line ELVSS is preferably shared as the second initialization voltage line Vini2. With this configuration, the wiring area for initializing each pixel circuit Pix(i, j) can be reduced.
Similar to the display portion 11 in the first embodiment (
The display portion 11c also includes, as power source lines (not illustrated) common to each pixel circuit 15c, a power source line for supplying the high-level power supply voltage ELVDD (hereinafter referred to as “high-level power source line” and indicated by the same reference sign as the high-level power supply voltage ELVDD) to drive organic EL elements (described later) and a power source line for supplying the low-level power supply voltage ELVSS (referred to below as “low-level power source lines” and indicated by the same reference sign as the low-level power supply voltage ELVSS) for driving the organic EL element. However, unlike the first embodiment, the display portion 11c does not include the first and second initialization voltage lines Vini1 and Vini2 used for supplying the first and second initialization voltages Vini1 and Vini2 to each pixel circuit 15c. Instead, an initialization signal line INIi corresponding to each pixel circuit is used for the initialization of each pixel circuit 15c (details described later). In the present embodiment, an initialization voltage supply circuit is realized by the n initialization signal lines INI1 to INIn and an initialization signal generation circuit in the scanning-side drive circuit 40c.
The configuration and operation of the display control circuit 20 and the data-side drive circuit 30 are the same as those of the first embodiment, and thus detailed descriptions of these components will be omitted.
Similar to the first embodiment, the scanning-side drive circuit 40c functions as a scanning signal line drive circuit that drives the scanning signal lines G0 to Gn and a light emission control circuit that drives the light emission control lines E1 to En based on the scanning-side control signal Scs output from the display control circuit 20 (see
Next, the configuration and operation of the pixel circuit 15c according to the present embodiment will be described with reference to
As illustrated in
In the present embodiment, turning on/off each of the transistors M2 to M7 as switching elements in the pixel circuit Pix(i, j) is controlled in the same manner as in the first embodiment (see
The period from the time t4 to the time t5 is the data write period of the pixel circuit Pix(i, j). In this data write period, as illustrated in
At the time t5, which is the end time of the ith scanning select period as the data write period, the write control transistor M2, the threshold compensation transistor M3, and the second initialization transistor M7 change to the off state, and the voltage of the ith initialization signal line INIi changes to the first initialization voltage Vini1, similar to the first embodiment. Thereafter, the voltage of the ith initialization signal line INIi is maintained at the first initialization voltage Vini1 until the start time of the ith scanning select period in the next non-light emission period.
Also in the present embodiment and similar to the first embodiment, the time t6 onward is a light emission period. In this light emission period, in the pixel circuit Pix(i, j), the first and second light emission control transistors M5 and M6 are in the on state and the write control transistor M2, the threshold compensation transistor M3, the first initialization transistor M4, and the second initialization transistor M7 are in the off state. As a result, similar to the first embodiment, the current I1 given by Expression (6) flows from the high-level power source line ELVDD to the low-level power source line ELVSS via the first light emission control transistor M5, the drive transistor M1, the second light emission control transistor M6, and the organic EL element OLED. Thus, in the light emission period, the organic EL element OLED emits light at a luminance corresponding to the data voltage Vdata, which is the voltage of the corresponding data signal line Dj in the ith scanning select period, regardless of the threshold voltage Vth of the drive transistor M1. Further, in this light emission period, the voltage of the initialization signal line INIi is maintained at the first initialization voltage Vini1 that is higher than the second initialization voltage Vini2.
As described above, also in the present embodiment, in the pixel circuit Pix(i, j), the gate voltage Vg of the drive transistor M1 needs to be initialized (initialization of the holding voltage of the holding capacitor C1) before the voltage of the corresponding data signal line Dj is applied to the holding capacitor C1 as the data voltage Vdata via the drive transistor M1 in the diode-connected state. In the present embodiment, unlike in the first embodiment, voltage of the same initialization signal line INIi is used in the initialization of both the gate voltage Vg of the drive transistor M1 and the anode voltage Va of the organic EL element OLED. Because the voltage of the initialization signal line INIi is the first initialization voltage Vini1 during the i-1th scanning select period and the second initialization voltage Vini2 in the ith scanning select period, the gate voltage Vg is initialized to the first initialization voltage Vini1 and the anode voltage Va is initialized to the second initialization voltage Vini2 (see
In the pixel circuit 15c according to the second embodiment, the gate terminal of the second initialization transistor M7 is connected to the corresponding scanning signal line Gi, but the gate terminal may be connected to the preceding scanning signal line Gi−1 instead. A display device including a pixel circuit having such a configuration will be described below as a first modification example of the second embodiment.
Operations other than those described above in the display device according to the present modification example are the same as those of the second embodiment. In the light emission period, the voltage of the initialization signal line INIi is maintained at the first initialization voltage Vini1 (>Vini2) (see
In the second embodiment and the first modification example described above, the voltage of the initialization signal line INIi changes synchronously with a signal change of the corresponding scanning signal line Gi or the preceding scanning signal line Gi−1 (
The disclosure is not limited to the embodiments described above, and various modifications may be made without departing from the scope of the disclosure.
In the above description, an organic EL display device has been described as an example and embodiments and modification examples thereof have been given. However, the disclosure is not limited to an organic EL display device and may be applied to any display device employing an internal compensation method using a display element driven by a current. The display element that can be used in such a configuration is a display element in which luminance, transmittance, or other factors are controlled by a current and includes, for example, an organic EL element, i.e., an organic light-emitting diode (OLED), or an inorganic light-emitting diode or a quantum dot light-emitting diode (QLED).
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2018/012756 | 3/28/2018 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2019/186765 | 10/3/2019 | WO | A |
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