Patent Application
20240404453
This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0069534, filed on May 30, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
Embodiments of the present disclosure relate to display devices and methods of driving the display devices, and more particularly, relate to display devices capable of improving the quality of images and methods of driving the same.
A light emitting display device may display an image using light emitting diodes that generate light through the recombination of electrons and holes. Advantages of light emitting display devices include low power consumption and fast response speeds.
A light emitting display device may include pixels connected to data lines and scan lines. Each of the pixels may include, in general, a light emitting diode and a circuit unit for controlling the amount of current flowing to the light emitting diode. In response to a data signal, the circuit unit may particularly control the amount of current that flows from a first driving voltage to a second driving voltage through the light emitting diode. In this case, the light emitting diode generates light having a luminance corresponding to the amount of current flowing through the light emitting diode.
Embodiments of the present disclosure provide display devices capable of improving the quality of images in a variable frequency mode of operation and methods of driving the display devices.
According to an embodiment, a display device may include a display panel that includes a plurality of pixels each emitting light in response to a panel driving signal, a panel driver that provides the panel driving signal to the display panel, and a driving controller that receives an image signal at a current frame rate and controls driving of the panel driver based on the image signal and a control signal.
The driving controller includes a comparing unit that compares a reference frame rate and the current frame rate and outputs a duty control signal when the current frame rate is less than the reference frame rate, a duty control unit that controls a current duty ratio of a current emission period of the display panel based on the duty control signal, and a luminance control unit that controls luminance of each of the pixels based on the current duty ratio.
According to an embodiment, a driving method of a display device includes receiving an image signal at a current frame rate, comparing the current frame rate and a reference frame rate, outputting a duty control signal when the current frame rate is less than the reference frame rate, controlling a current duty ratio of a current emission period of a display panel based on the duty control signal, outputting a luminance control signal based on the current duty ratio, and controlling luminance of each of pixels provided in the display panel in response to the luminance control signal.
The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings.
In the following, a first component (or area, layer, part, portion, etc.) being “on”, “connected with”, or “coupled to” a second component means that the first component may be directly on, connected with, or coupled to the second component or means that a third component is disposed between the first component and the second component.
Like reference numerals refer to like components. Also, in the drawings, the thickness, ratio, and dimension of components may be exaggerated or altered for effectiveness of description of technical contents.
Although the terms “first”, “second”, etc. may be used to describe various components, the components should not be construed as being limited by these terms. The terms are only used to distinguish one component from another component. For example, a first component may be referred to as a “second component”, and similarly, the second component may be referred to as the “first component.” The articles “a,” “an,” and “the” are singular in that they have a single referent, but the use of the singular form in the specification should not preclude the presence of more than one referent.
The term “and/or” includes one or more combinations in each of which associated elements are defined. Also, the terms “under”, “below”, “on”, “above”, etc. may be used to describe the correlation of components illustrated in drawings. The terms are relative and may only be described with reference to a direction indicated in the drawing.
It will be further understood that the terms “comprises”, “includes”, “have”, etc. specify the presence of stated features, numbers, steps, operations, elements, components, or a combination thereof but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or a combination thereof.
Unless otherwise defined, all terms (including technical terms and scientific terms) used in herein have the same meaning as commonly understood by one skilled in the art to which the present disclosure belongs. Furthermore, terms such as terms defined in the dictionaries commonly used should be interpreted as having a meaning consistent with the meaning in the context of the related technology and should not be interpreted in ideal or overly formal meanings unless explicitly defined herein.
Below, embodiments of the present disclosure will be described with reference to drawings.
Referring to
The driving controller 100 may receive an image signal RGB and a control signal CTRL from a host processor (not shown). According to an embodiment of the present disclosure, the host processor may include one or more of a central processing unit (CPU) or an application processor (AP). The host processor may further include one or more of a graphic processing unit (GPU), a communication processor (CP), and an image signal processor (ISP).
The driving controller 100 may include an interface conversion circuit and a timing control circuit. The driving controller 100 generates image data DATA by converting a data format of the image signal RGB to a format suitable or required for an interface with the data driver 200. The control signal CTRL may include a vertical synchronization signal, an input data enable signal, a master clock signal, etc. The driving controller 100 may generate a first driving control signal SCS, a second driving control signal DCS, and a third driving control signal ECS based on the control signal CTRL.
The data driver 200 receives the second driving control signal DCS and the image data DATA from the driving controller 100. The data driver 200 may further receive a gamma reference voltage VG_ref from the voltage generator 400. The data driver 200 converts the image data DATA into data signals based on the gamma reference voltage VG_ref and outputs the data signals to a plurality of data lines DL1 to DLm described further below. The data signals may be analog voltages corresponding to grayscale values of the image data DATA.
The scan driver 300 receives the first driving control signal SCS from the driving controller 100. The scan driver 300 may output scan signals to scan lines in response to the first driving control signal SCS.
The voltage generator 400 generates various voltages necessary for the operation of the display panel DP. In an embodiment, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, a second initialization voltage AINT, and the gamma reference voltage VG_ref.
The display panel DP further includes initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn+1, emission control lines EML1 to EMLn, and the data lines DL1 to DLm. An area of the display panel DP may be partitioned into an effective area AA and a non-effective area NAA. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, the emission control lines EML1 to EMLn, the data lines DL1 to DLm, and the pixels PX may overlap the effective area AA. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, and the emission control lines EML1 to EMLn extend in a first direction DR1. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, and the emission control lines EML1 to EMLn are arranged to be spaced from each other in a second direction DR2. The data lines DL1 to DLm extend in the second direction DR2 and are arranged to be spaced from each other in the first direction DR1.
The plurality of pixels PX are electrically connected to the initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, the emission control lines EML1 to EMLn, and the data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected to four scan lines. For example, as illustrated in
The scan driver 300 and the emission driver 350 may be disposed in the non-effective area NAA of the display panel DP. In response to the first driving control signal SCS, the scan driver 300 may output initialization scan signals to the initialization scan lines SIL1 to SILn, may output compensation scan signals to the compensation scan lines SCL1 to SCLn, and may output write scan signals to the write scan lines SWL1 to SWLn+1.
The emission driver 350 receives the third driving control signal ECS from the driving controller 100. The emission driver 350 may output emission control signals to the emission control lines EML1 to EMLn in response to the third driving control signal ECS. In another embodiment, the scan driver 300 may be connected to the emission control lines EML1 to EMLn. In this case, the scan driver 300 may output the emission control signals to the emission control lines EML1 to EMLn.
Each of the plurality of pixels PX may include a light emitting element ED (refer to
Each of the plurality of pixels PX receives the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT, and the second initialization voltage AINT from the voltage generator 400.
The display device DD may operate in a normal frequency mode (or a first mode) in which a driving frequency is fixed (i.e., is not variable) or may operate in a variable frequency mode (or a second mode) in which the driving frequency is variable. In the variable frequency mode, the driving frequency may vary to correspond to the frame rate. Operation of the display device DD in the variable frequency mode is described in more detail below.
Referring to
According to an embodiment of the present disclosure, a frame rate being the highest from among variable frame rates supported in the variable frequency mode may be referred to as a “reference frame rate.” A period by which the driving controller 100 outputs the image data DATA to the data driver 200 may be defined herein as a driving frame. In the variable frequency mode, the duration of the driving frame may vary depending on the frame rate. For example, when the frame rate is 240 Hz, the duration of the driving frame may be about 4.167 ms; when the frame rate is 60 Hz, the duration of the driving frame may be about 16.7 ms. According to an embodiment of the present disclosure, the reference frame rate may be set to 480 Hz, 360 Hz, 240 Hz, 120 Hz, etc.
The driving controller 100 may receive the image signal RGB at a current frame rate. The current frame rate may be less than or equal to the reference frame rate.
The driving controller 100 includes a comparing unit 110, a duty control unit 120, and a luminance control unit 130. The reference frame rate may be set in advance in the comparing unit 110. The comparing unit 110 may receive information about the current frame rate. The comparing unit 110 may receive the information about the current frame rate from the host processor. However, the present disclosure is not limited thereto. The information about the current frame rate may be generated within the driving controller 100.
The comparing unit 110 may compare the reference frame rate and the current frame rate, and when the current frame rate is less than the reference frame rate, the comparing unit 110 may output a duty control signal Duty_CS. The duty control unit 120 may control a current duty ratio DR_C of a current emission period CEP of the display panel DP based on the duty control signal Duty_CS. The current emission period CEP that is a period included in a current frame C_DF may be a period of the current frame C_DF, in which the display panel DP substantially emits light. The current duty ratio DR_C may be defined as a ratio or a percentage of the current frame C_DF that the current emission period CEP occupies in the current frame C_DF.
The driving controller 100 may receive the image signal RGB at the reference frame rate in a reference frame R_DF. The reference frame R_DF may further indicate a reference emission period REP, and the reference emission period REP may be a period of the reference frame R_DF, in which the display panel DP substantially emits light. The reference emission period REP may have a reference duty ratio, and the reference duty ratio may be defined as a ratio of the reference emission period REP to the duration of the reference frame R_DF. According to an embodiment of the present disclosure, the duration of the reference emission period REP may be equal to the duration of the reference frame R_DF. In this case, the reference duty ratio may be 100%.
When the current frame rate is less than the reference frame rate, the duration of the current frame C_DF may be greater than the duration of the reference frame R_DF.
The duty control unit 120 may receive the duty control signal Duty_CS from the comparing unit 110 and may control the magnitude of the current duty ratio DR_C in response to the duty control signal Duty_CS. According to an embodiment of the present disclosure, when the current frame rate is less than the reference frame rate, the duty control unit 120 may control the magnitude of the current duty ratio DR_C such that the current duty ratio DR_C is greater in magnitude than the reference duty ratio.
When the reference frame rate is p times the current frame rate, the current duty ratio DR_C may be 1/p times the reference duty ratio. Herein, “p” may be a number greater than 1. According to an embodiment of the present disclosure, “p” may be 2, 2.5, 4, 5, etc.
As illustrated in
As illustrated in
According to an embodiment of the present disclosure, when the reference frame rate is p times the current frame rate, the duration of the current frame C_DF or C_DFa may be p times greater than the duration of the reference frame R_DF. In this case, the duration of the reference emission period REP may be equal to the duration of the current emission period CEP or CEPa. That is, even though the duration of the current frame C_DF or C_DFa is different from the duration of the reference frame R_DF, the current emission period CEP or CEPa may be maintained to have the same duration as the reference emission period REP.
An issue or problem in conventional variable-framerate display devices is that the duration of motion blur may vary for each frequency due to a duration difference of emission periods in the variable frequency mode. The difference or variation in motion blur reduces the quality of images and can cause a user in an AR or VR environment to become dizzy. An embodiment of the present disclosure may improve image quality and address issues or problems associated with prior display devices. In other words, the problem of the quality of image being reduced due to a difference between motion blur lengths or the dizziness that may be caused in the AR and VR environment may be solved or improved by an embodiment of the present disclosure.
Referring again to
The driving controller 100 may further include a lookup table 135 in which luminance correction values differently set depending on magnitudes of the duty ratio are stored. The luminance control unit 130 may receive a luminance correction value BCV corresponding to the current duty ratio DR_C from the lookup table 135 and may output a luminance control signal BCS based on the luminance correction value BCV.
The panel driver PDD may adjust the panel driving signal supplied to the display panel DP in response to the luminance control signal BCS, and thus, the luminance of each of the pixels PX may be varied or adjusted.
In an embodiment of the present disclosure, luminance that each pixel has in the current emission period CEP may be referred to as a “current luminance value,” and luminance that each pixel has in the reference emission period REP may be referred to as a “reference luminance value” RBV. When the reference frame rate is p times the current frame rate, the current duty ratio DR_C may be 1/p times the reference duty ratio, and the current luminance value CBV1 may be p times the reference luminance value RBV.
When the reference frame rate is 240 Hz and the current frame rate is 60 Hz, the current duty ratio DR_C may decrease to ¼ times the reference duty ratio. To compensate for the reduction of the power of emitted light due to the decrease in the duty ratio, the luminance control unit 130 may output the luminance control signal BCS such that the luminance of each pixel is higher to compensates for the reduced emission duration. As an embodiment of the present disclosure, when the current duty ratio DR_C decreases to ¼ times the reference duty ratio, the current luminance value CBV1 may be 4 times greater than the reference luminance value RBV.
As illustrated in
As an embodiment of the present disclosure, when a current frame rate is less than a reference frame rate, the current duty ratio DR_C may be adjusted to be less than the reference duty ratio, but the current luminance value CBV1 or CBV1a may be increased to be greater than the reference luminance value RBV so that a drop in average intensity of emitted light is avoided. Accordingly, in the variable frequency mode, the reduction of luminance may be prevented while improving the issue that the quality of image is reduced due to a difference between motion blur lengths for each frequency.
As illustrated in
When the reference frame rate is 240 Hz and the current frame rate is 60 Hz, the current duty ratio DR_C may decrease to ¼ times the reference duty ratio. As an embodiment of the present disclosure, when the current duty ratio DR_C decreases to ¼ times the reference duty ratio, the current luminance value CBV2 may be 2 times greater than the reference luminance value RBV.
As illustrated in
In an embodiment of the present disclosure, when a current frame rate is less than a reference frame rate, the current duty ratio DR_C may be adjusted to be less than the reference duty ratio, but the decrease in luminance in the current frame may be compensated for or prevented by increasing the current luminance value CBV2/CBV2a to be greater than the reference luminance value RBV. Accordingly, in the variable frequency mode, a reduction of luminance may be prevented while reducing or avoiding loss of image quality that might otherwise result from differences between motion blur lengths for each frequency.
Referring to
The voltage generation block 410 may receive an input voltage Vin and may generate various voltages necessary to drive the display device DD (refer to
The voltage control block 420 may receive one or more voltages among the various voltages generated by the voltage generation block 410. An example in which the voltage control block 420 receives the first driving voltage ELVDD is illustrated in
The voltage control block 420 may receive the luminance control signal BCS from the luminance control unit 130 (refer to
Also, the level of the compensation driving voltage ELVDD_a may change depending on the magnitude of the current luminance value CBV1/CBV1a. For example, the level of the compensation driving voltage ELVDD_a generated when the current luminance value CBV1 is 4 times the reference luminance value RBV may be higher than the level of the compensation driving voltage ELVDD_a generated when the current luminance value CBV1 is 2 times the reference luminance value RBV.
Referring to
The gamma reference voltage VG_ref may be provided to the voltage control block 420_a. The voltage control block 420_a may control the voltage level of the gamma reference voltage VG_ref in response to the luminance control signal BCS. As an embodiment of the present disclosure, the gamma reference voltage VG_ref may include a high gamma reference voltage (or a first gamma reference voltage) and a low gamma reference voltage (or a second gamma reference voltage). The voltage control block 420_a may control the voltage level of at least one of the low gamma reference voltage and the high gamma reference voltage. For example, to make the current luminance value CBV1 (refer to
The data driver 200 includes a gamma voltage generation block 210 and a data conversion block 220. The gamma voltage generation block 210 may generate a plurality of gamma voltages VGMA based on the compensation gamma reference voltage VG_ref_a. The gamma voltages VGMA may be supplied to the data conversion block 220. The data conversion block 220 may receive the image data DATA (refer to
As such, the luminance of each pixel PX (refer to
An equivalent circuit diagram of one pixel PXij of the plurality of pixels PX illustrated in
Referring to
The pixel PXij includes the light emitting element ED and the pixel circuit unit PXC. The light emitting element ED may be a light emitting diode. The light emitting diode may include an organic light emitting material, an inorganic light emitting material, a quantum dot, a quantum rod, or the like as an emission layer.
The pixel circuit unit PXC includes first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 and a single capacitor Cst. At least one of the first to seventh transistors T1 to T7 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. Alternatively, at least one of the first to seventh transistors T1 to T7 may be a transistor having an oxide semiconductor layer. Some or all of the first to seventh transistors T1 to T7 may be P-type transistors, and any remaining transistors may be N-type transistors. For example, among the first to seventh transistors T1 to T7, the first, second, and fifth to seventh transistors T1, T2, and T5 to T7 may be P-type transistors, and the third and fourth transistors T3 and T4 may be N-type transistors. However, a configuration of the pixel circuit unit PXC according to the present disclosure is not limited to the embodiment illustrated in
The initialization scan line SILj, the compensation scan line SCLj, the write scan line SWLj, the black scan line SBLj, and the emission control line EMLj may respectively transfer to the pixel PXij a j-th initialization scan signal (hereinafter referred to as an “initialization scan signal”) SIj, a j-th compensation scan signal (hereinafter referred to as a “compensation scan signal”) SCj, a j-th write scan signal (hereinafter referred to as a “write scan signal”) SWj, a j-th black scan signal (hereinafter referred to as a “black scan signal”) SBj, and a j-th emission control signal (hereinafter referred to as an “emission control signal”) EMj. The data line DLi transfers an i-th data signal Di to the pixel PXij. The i-th data signal Di may have a voltage level corresponding to a grayscale of a relevant image signal belonging to the image signal RGB input to the display device DD (refer to
The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 through the fifth transistor T5, a second electrode electrically connected to an anode of the light emitting clement ED through the sixth transistor T6, and a gate electrode connected to a first electrode of the capacitor Cst. The electrode of the first transistor T1 may receive the i-th data signal Di transferred through the data line DLi depending on a switching operation of the second transistor T2 and may supply a driving current Id through the sixth transistor T6 to the light emitting element ED.
The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the write scan line SWLj. The second transistor T2 may be turned on depending on the write scan signal SWj transferred through the write scan line SWLj and then may transfer the i-th data signal Di from the data line DLi to the first electrode of the first transistor T1.
The third transistor T3 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the gate electrode of the first transistor T1, and a gate electrode connected to the compensation scan line SCLj. The third transistor T3 may be turned on depending on the compensation scan signal SCj transferred through the compensation scan line SCLj, and thus, the gate electrode and the second electrode of the first transistor T1 may be connected to each other, that is, the first transistor T1 may be diode-connected.
The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third driving voltage line VL3 through which the first initialization voltage VINT is transferred, and a gate electrode connected to the initialization scan line SILj. The fourth transistor T4 may be turned on depending on the initialization scan signal SIj transferred through the initialization scan line SILj, and thus, the first initialization voltage VINT may be transferred to the gate electrode of the first transistor T1. As such, a voltage of the gate electrode of the first transistor T1 may be initialized. This operation may be referred to as an “an initialization operation”.
The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected with the first electrode of the first transistor T1, and a gate electrode connected to the emission control line EMLj.
The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting element ED, and a gate electrode connected to the emission control line EMLj.
The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the emission control signal EMj transferred through the emission control line EMLj. The first driving voltage ELVDD applied through the turned-on fifth transistor T5 may be transferred to the light emitting element ED after compensated through the diode-connected first transistor T1.
The seventh transistor T7 includes a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the fourth driving voltage line VL4 through which the second initialization voltage AINT is transferred, and a gate electrode connected to the black scan line SBLj.
The first electrode of the capacitor Cst is connected to the gate electrode of the first transistor T1 as described above, and a second electrode of the capacitor Cst is connected to the first driving voltage line VL1. A cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transferring the second driving voltage ELVSS.
Referring to
The plurality of scan signals SIj, SCj, SWj, and SBj may be activated during the first to third write frames WP1, WP2, and WP3. In detail, the initialization scan signal SIj includes a first active period AP1 having the high level in the first to third write frames WP1, WP2, and WP3, and the compensation scan signal SCj includes a second active period AP2 having the high level in the first to third write frames WP1, WP2, and WP3. The write scan signal SW includes a third active period AP3 having the low level in the first to third write frames WP1, WP2, and WP3, and the black scan signal SBj includes a fourth active period AP4 having the low level in the first to third write frames WP1, WP2, and WP3. According to an embodiment of the present disclosure, the black scan signal SBj may further include a fourth active period AP4 having the low level in the holding frames HP and HP1 to HP3 in addition to the first to third write frames WP1, WP2, and WP3. That is, some scan signals SIj, SCj, and SWj among the plurality of scan signals SIj, SCj, SWj, and SBj may have the same frequency as the corresponding driving frame, and the remaining scan signal SBj may have the same frequency as the reference frequency.
When the initialization scan signal SIj of the high level is provided to the initialization scan line SILj during the first active period AP1, the fourth transistor T4 is turned on in response to the initialization scan signal SIj of the high level. The first initialization voltage VINT is transferred to the gate electrode of the first transistor T1 through the turned-on fourth transistor T4, and the gate electrode of the first transistor T1 is initialized by the first initialization voltage VINT.
Next, when the compensation scan signal SCj of the high level is supplied through the compensation scan line SCLj during the second active period AP2, the third transistor T3 is turned on. During the second active period AP2, the first transistor T1 is diode-connected by the third transistor T3 turned on and is forward-biased. The second active period AP2 of the compensation scan signal SCj may not overlap the first active period AP1 of the initialization scan signal SIj. Also, the first active period AP1 of the initialization scan signal SIj may precede the second active period AP2 of the compensation scan signal SCj.
According to an embodiment of the present disclosure, the second active period AP2 of the compensation scan signal SCj is defined as a period where the compensation scan signal SCj has the high level, and the first active period AP1 of the initialization scan signal SIj is defined as a period where the initialization scan signal SIj has the high level. When the third and fourth transistors T3 and T4 are P-type transistors, the second active period AP2 of the compensation scan signal SCj is defined as a period where the compensation scan signal SCj has the low level, and the first active period AP1 of the initialization scan signal SIj is defined as a period where the initialization scan signal SIj has the low level.
The second active period AP2 may overlap the third active period AP3 in which the write scan signal SWj is set to the low level. During the third active period AP3, the second transistor T2 is turned on by the write scan signal SWj of the low level. In this case, the gate of the first transistor T1 and the connected electrode of the capacitor Cst obtain a compensation voltage “Di-Vth” that results from subtracting the threshold voltage Vth of the first transistor T1 from the voltage of the i-th data signal Di supplied from the data line DLi to the gate electrode of the first transistor T1. That is, the potential of the gate electrode of the first transistor T1 may be set to the compensation voltage “Di-Vth”.
The first driving voltage ELVDD and the compensation voltage “Di-Vth” may be respectively applied to opposite ends of the capacitor Cst, and the capacitor Cst may store charges corresponding to a voltage difference of the opposite ends of the capacitor Cst.
Afterwards, during the fourth active period AP4, the seventh transistor T7 is turned by the black scan signal SBj of the low level supplied through the black scan line SBLj. A portion of the driving current Id may be drained through the seventh transistor T7 as a bypass current Ibp.
Assuming the case where the pixel PXij displays a black image, in the case where the light emitting element ED emits light in response to a minimum driving current of the first transistor T1 flowing as the driving current Id, the pixel PXij fails to normally display a black image. Accordingly, the seventh transistor T7 of the pixel PXij according to an embodiment of the present disclosure may drain a portion of the minimum driving current of the first transistor T1 to a current path, which is different from a current path to the light emitting element ED, as the bypass current Ibp. Herein, the minimum driving current of the first transistor T1 means a current flowing to the first transistor T1 under the condition that a gate-source voltage Vgs of the first transistor T1 is less than the threshold voltage Vth, that is, the first transistor T1 is turned off. As the minimum driving current (e.g., a current of about 10 pA or less) flowing to the first transistor T1 is transferred to the light emitting clement ED under the condition that the first transistor T1 is turned off, an image of a black grayscale is displayed. In the case where the pixel PXij displays the black image, the bypass current Ibp has a relatively large influence on the minimum driving current; in contrast, in the case where the pixel PXij displays an image such as a normal image or a white image, the influence of the bypass current Ibp on the driving current Id may be negligible. Accordingly, when the pixel PXij displays a black image, a current (i.e., an emission current led), which is obtained by subtracting the amount of the bypass current Ibp flowing through the seventh transistor T7 from the driving current Id, may be provided to the light emitting clement ED, and thus, the black image may be clearly displayed. Accordingly, the pixel PXij may implement an accurate black grayscale image by using the seventh transistor T7, and thus, a contrast ratio may be improved.
The emission control signal EMj that is supplied from the emission control line EMLj may include an emission period EP and a non-emission period NEP. As an embodiment of the present disclosure, the emission period EP may be a low-level period, and the non-emission period NEP may be a high-level period. The non-emission period NEP of the emission control signal EMj may overlap the first to fourth active periods AP1, AP2, AP3, and AP4 in the first to third write frames WP1, WP2, and WP3. The emission period EP of the emission control signal EMj may not overlap the first to fourth active periods AP1, AP2, AP3, and AP4. When the operation is performed at the second driving frequency, the emission period EP of the emission control signal EMj may overlap the holding frame HP. When the operation is performed at the third driving frequency, the emission period EP of the emission control signal EMj may overlap the first holding frame HP1 among the holding frames HP1, HP2, and HP3.
The fifth transistor T5 and the sixth transistor T6 are turned on by the emission control signal EMj of the low level. In this case, the driving current Id is generated depending on a difference between the gate voltage of the gate electrode of the first transistor T1 and the first driving voltage ELVDD and is then supplied to the light emitting element ED through the sixth transistor T6. Accordingly, the emission current led flows through the light emitting element ED during the emission period EP, and thus, a light luminance that corresponds to the emission current led may be output from the light emitting element ED.
The emission period EP of the emission control signal EMj when the operation is performed at the first driving frequency may have the same duration as the emission period EP of the emission control signal EMj when the operation is performed at the second or third driving frequency. Even though the driving frequency varies in the variable frequency mode, the duration of the emission period EP may be maintained uniformly. That is, even though the driving frequency is variable, the duration of the emission period where light is output from the light emitting element ED may be maintained uniformly. Accordingly, the variable frequency mode can avoid the reduction in the quality of image that might otherwise result from differences in motion blur lengths for each frequency.
Referring to
When the comparison result indicates that the current frame rate is less than the reference frame rate, the comparing unit 110 may output the duty control signal Duty_CS (S130). The duty control unit 120 may control the current duty ratio DR_C of a current emission period of the display panel DP based on the duty control signal Duty_CS (S140).
That is, when the current frame rate is less than the reference frame rate, the duration of the current frame C_DF (refer to
Afterwards, the luminance control unit 130 outputs the luminance control signal BCS based on the current duty ratio DR_C (S150). The luminance control unit 130 may receive the luminance correction value BCV corresponding to the current duty ratio DR_C from the lookup table 140 where luminance correction values differently set depending on magnitudes of the duty ratio are stored and may generate the luminance control signal BCS based on the luminance correction value BCV.
The panel driver PDD may control the luminance of each of the pixels PX provided in the display panel DP in response to the luminance control signal BCS (S160). As an embodiment of the present disclosure, the voltage generator 400 may adjust the voltage level of the first driving voltage ELVDD or the gamma reference voltage VG_ref for the purpose of controlling the luminance of each of the pixels PX provided in the display panel DP in response to the luminance control signal BCS.
According to the present disclosure, when a current frame rate is less than a reference frame rate, a motion blur length may be prevented from varying for each driving frequency by adjusting the current duty ratio to be less than the reference duty ratio. Accordingly, an issue that the quality of image is reduced due to a difference between motion blur lengths for respective frequencies in a variable frequency mode.
Also, when a current duty ratio decreases, luminance may be compensated for, and thus, an issue that the entire luminance of a display panel decreases at a current frame may be improved.
While the present disclosure has been described with reference to embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0069534 | May 2023 | KR | national |
