Patent Grant
10607563
Korean Patent Application No. 10-2016-0106906, filed on Aug. 23, 2016, and entitled, “Display Device and Method of Driving the Same,” is incorporated by reference herein in its entirety.
One or more embodiments described herein relate to a display device and a method for driving a display device.
Various types of displays have been developed. Examples include a liquid crystal displays and an organic light emitting displays. A liquid crystal display includes a liquid crystal layer between substrates that respectively include pixel and common electrodes. When voltages are applied to the electrodes, an electric field is generated to control the alignment of liquid crystal molecules in the liquid crystal layer, This, in turn, controls light emission for displaying an image.
An organic light emitting display generates an image using an organic luminescent material that emits light based on a recombination of electrons and holes in an organic layer. Organic light emitting displays have high response speed, high brightness, a wide viewing angle, and low power consumption.
In accordance with one or more embodiments, a display device includes a timing controller to output a first clock signal having first rising time during an active section and a second clock signal having second rising time during a blank section adjacent to the active section; a driver to generate a data signal based on the first clock signal and the second clock signal and to output the data signal; and a display panel to display an image based on the data signal, wherein the first rising time is shorter than the second rising time. The slew rate of the first clock signal may be greater than the slew rate of the second clock signal.
The first clock signal may have first falling time, the second clock signal may have second falling time, and the first falling time may be shorter than the second falling time. The first clock signal may have a first maximum voltage and a first minimum voltage lower than the first maximum voltage, the second clock signal may have a second maximum voltage and a second minimum voltage lower than the second maximum voltage, the first maximum voltage may have lower than the second maximum voltage, and the first minimum voltage may have lower than the second minimum voltage.
The display panel may include a display area to display an image and a non-display area outside the display area. The display area may include 1st to nth pixel rows (n is a natural number of 2 or more), and the active section may have a vertical active section in which the data signal is input to the 1st to nth pixel rows. The display area may include 1st to nth pixel columns (n is 2 or more), and the active section may include a horizontal active section in which the data signal is input to the 1st to nth pixel columns.
The timing controller may change the first rising time to generate the second clock signal when the active section is converted to the blank section. The timing controller may include a first output and a second output connected with the driver, the first output may provide the first clock signal to the driver during the active section, and the second output may provide the second clock signal to the driver during the blank section.
In accordance with one or more other embodiments, a display device includes a display panel including a display area to display an image and a non-display area outside the display area; a driver connected with the display panel through a plurality of signal lines; and a time controller to provide a first clock signal to the driver during an active section and a second clock signal to the driver during a blank section adjacent to the active section, wherein the driver is to provide a data signal generated based on the first clock signal and the second clock signal to the signal lines during the active section, and wherein the slew rate of the first clock signal is greater than the slew rate of second clock signal.
The rising time of the first clock signal may be shorter than the rising time of the second clock signal. The driver may provide a dummy data signal generated based on the first clock signal and the second clock signal to the non-display area during the blank section. The display area may include 1st to nth pixel rows (n is a natural number of 2 or more), and the active section may be a vertical active section in which the data signal is input to the 1st to nth pixel rows.
The display area may include 1st to nth pixel columns (n is a natural number of 2 or more), and the active section may be a horizontal active section in which the data signal is input to the 1st to nth pixel columns. The timing controller may adjust the slew rate of the first clock signal to generate the second clock signal when the active section is converted to the blank section.
The timing controller may include a first output and a second output connected with the driver, the first output may provide the first clock signal to the driver during the active section, and the second output may provide the second clock signal to the driver during the blank section. The first clock signal may have a first maximum voltage and a first minimum voltage lower than the first maximum voltage, the second clock signal may have a second maximum voltage and a second minimum voltage lower than the second maximum voltage, the first maximum voltage may be lower than the second maximum voltage, and the first minimum voltage may be lower than the second minimum voltage.
In accordance with one or more other embodiments, a method for driving a display device includes providing a first clock signal having a first rising time to a driver during an active section in which a data signal displaying an image is input; and providing a second clock signal having a second rising time to the driver during a blank section located adjacent to the active section, wherein the first rising time is shorter than the second rising time. The slew rate of the first clock signal may be greater than the slew rate of the second clock signal.
The first clock signal may have a first maximum voltage and a first minimum voltage lower than the first maximum voltage, the second clock signal may have a second maximum voltage and a second minimum voltage lower than the second maximum voltage, the first maximum voltage may be lower than the second maximum voltage, and the first minimum voltage may be lower than the second minimum voltage.
Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:
Example embodiments will be described with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art. The embodiments (or portions thereof) may be combined to form additional embodiments.
In the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
When an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the another element or be indirectly connected or coupled to the another element with one or more intervening elements interposed therebetween. In addition, when an element is referred to as “including” a component, this indicates that the element may further include another component instead of excluding another component unless there is different disclosure.
Referring to
The timing controller 100 may externally receive raw video signals (e.g., RGB signals), a vertical synchronization signal Vsync, and a horizontal synchronization signal Hsync. The timing controller 100 may generate transmission data TD based the externally received signals and may output the generated transmission data TD to the drive circuit unit 200.
The first clock signal 110 may have first rising time Tr1 and first falling time Tf1. The rising time may correspond to the time taken for a voltage level to rise from a first (e.g., minimum or other predetermined) voltage to a second (e.g., maximum or another predetermined) voltage in a clock signal having a predetermined section. The falling time may correspond to the time taken for the voltage level to fall from the first voltage to the second voltage in the clock signal having a predetermined section. In one embodiment, the first rising time Tr1 corresponds to the time taken for the first clock signal 110 to rise from the minimum voltage Vbot to the maximum voltage Vtop. Further, the first clock signal 110 may include display data DD.
The second clock signal 120 may have second rising time Tr2 and second falling time T12. The first rising time Tr1 is shorter than the second rising time Tr2. For example, the voltage level of the first clock signal 110 may rapidly change from the minimum voltage Vbot to the maximum voltage Vtop, compared to that of the second clock signal 120.
The first clock signal 110 has a higher slew rate than the second clock signal 120. The slew rate may correspond to the degree to which a pulse waveform increases to a predetermined (e.g., maximum) value over a predetermined time. In one embodiment, slew rate may be represented as the slope or inclination of the waveform as it increases to the maximum value. Slew rate may be determined, for example, as a value obtained by dividing the rising voltage by the rising time.
The slew rate of the first clock signal 110 may be represented, for example, as a value obtained by dividing the voltage change from the minimum voltage Vbot to the maximum voltage Vtop by the first rising time Tr1. The slew rate of the second clock signal 120 may be represented, for example, as a value obtained by dividing the voltage change from the minimum voltage Vbot to the maximum voltage Vtop by the second rising time Tr2. Since the first rising time Tr1 is shorter than the second rising time Tr2, the slew rate of the first clock signal 110 is higher than the slew rate of the second clock signal 120.
The first falling time Tf1 is shorter than the second falling time Tf2. For example, the voltage level from the minimum voltage Vbot to the maximum voltage Vtop is changed so that the first clock signal 110 is rapid compared to the second clock signal 120.
The timing controller 100 may provide the first clock signal 110 to the drive circuit unit 200 during an active section. The timing controller 100 may provide the second clock signal 120 to the drive circuit unit 200 during a blank section. The active section may correspond to a section during which display data DD, for displaying an image in the corresponding frame, is input. The blank section may correspond to a section during which display data DD, for displaying an image in the corresponding frame, is not input. The active section may include, for example, a vertical active section VA and a horizontal active section HA. The blank section may include a vertical blank section VB and a horizontal blank section HB.
The vertical active section VA and horizontal active section HA are adjacent to each other in one frame. Further, one vertical active section VA may include a plurality of horizontal active sections HA and a plurality of horizontal blank section HB.
The timing controller 100 may provide the first clock signal 110 to the drive circuit unit 200 during the vertical active section VA, and may provide the second clock signal 120 to the drive circuit unit 200 during the vertical blank section VB located next the vertical active section VA. In an embodiment, the timing controller 100 may generate the second clock signal 120 having the second rising time Tr2 longer than the first rising time Tr1 by changing the length of the first rising time Tr1 of the first clock signal 110.
The drive circuit unit 200 may be connected with the timing controller 100 through a plurality of first signal lines TL. The drive circuit unit 200 may be connected with the display panel 300 through a plurality of second signal lines SL1 to SLn. The drive circuit unit 200 may provide display signals S1 to Sn to the display panel 300 through the plurality of second signal lines SL1 to SLn.
In an embodiment, the drive circuit unit 200 may be, for example, a data integrated circuit (IC) that provides data signals to the display panel 300. The data signals may be signals including display data DD for display an image for the display panel 300. The second signal lines SL1 to SLn may be data lines receiving the data signals. The display signals S1 to Sn may be the data signals. The drive circuit unit 200 may include a plurality of source drivers SD1 to SDn. Each of the source drivers SD1 to SDn may be connected with the timing controller 100 through the first signal line TL in a point-to-point manner.
In another embodiment, the drive circuit unit 200 may be a scan drive unit providing a plurality of scan signals to the display panel 300. The display panel 300 includes a plurality of pixel units. The pixel units may include a switching element receiving data signals for display an image and a pixel electrode receiving the data signals through the switching operation of the switching element. The plurality of scan signals may be signals provided to a control electrode of the switching element to control the switching operation. The second signal lines SL1 to SLn may be a plurality of scan lines receiving the scan signals. Further, the display signals S1 to Sn may be the scan signals. In an embodiment, the drive circuit unit 200 may include a shift register. Unlike
At least some embodiments are described assuming that the drive circuit unit 200 is a data drive unit and the display signals S1 to Sn output from the drive circuit unit 200 are data signals.
The display panel 300 may display an image based on the display signals S1 to Sn from the drive circuit unit 200. The display panel 300 may be, for example, a liquid crystal display panel, an organic light-emitting display panel, or a plasma display panel.
The pixel units may be arranged in a matrix of 1 to n rows (n is a natural number of 2 or more) and 1 to m columns (m is a natural number of 2 or more). The dummy pixel units may be arranged in one or more rows and one or more columns.
The pixel units in the 1 to n rows may be arranged along a vertical active area VAA. For example, the display signals S1 to Sn provided during the vertical active section VA may be provided to the pixel units composed of 1 to n rows arranged along the vertical active area VAA. The display signals S1 to Sn provided during the vertical active section VA may be signals generated based on the first clock signal 110.
The dummy pixel units in the one or more rows may be arranged along the vertical blank area VBA. The display signals S1 to Sn provided during the vertical blank section VB may be provided to the dummy pixel units in one or more rows arranged along the vertical blank area VBA. The display signals S1 to Sn provided during vertical blank section VB may be generated based on second clock signal 120.
The pixel units in the 1 to m columns may be arranged along a horizontal active area HAA. The display signals S1 to Sn provided during the vertical active section VA may be provided to the pixel units composed of 1 to m columns arranged along the horizontal active area HAA. The display signals S1 to Sn provided during the horizontal active section HA may be generated based on the first clock signal 110.
The dummy pixel units in one or more columns may be arranged along the horizontal blank area HBA. The display signals S1 to Sn provided during the horizontal blank section HB may be provided to the dummy pixel units in one or more columns arranged along the horizontal blank area HBA. The display signals S1 to Sn provided during the horizontal blank section HB may be generated based on the second clock signal 120.
Referring to
The timing controller 100 may receive a vertical synchronization signal Vsync from an external source. The vertical synchronization signal Vsync is transmitted at one frame period. Referring to
The timing controller 100 may provide transmission data TD to the drive circuit unit 200 during the vertical active section VA and the vertical blank section VB. The timing controller 100 may provide the first clock signal 110 of the transmission data TD during the vertical active section VA. Referring to
The data packet 110a may include display data DD and clock codes CC1 and CC2. The display data DD may include a plurality of data bits D1 to Dn corresponding to the number of columns of a pixel unit. The clock codes CC1 and CC2 may be periodically added to the display data DD. In an embodiment, the clock codes CC1 and CC2, as shown in
The drive circuit unit 200 may provide display signals S1 to Sn, generated based on the first clock signal 110, to a plurality of pixel units in the display area DA of the display panel 300 during the vertical active section VA of the 1st frame.
The timing controller 100 may provide the second clock signal 120 to the drive circuit unit 200 during the vertical blank section VB. The rising time Tr1 of the first clock signal 110 is shorter than the rising time Tr2 of the second clock signal 120. The drive circuit unit 200 may provide display signals S1 to Sn, generated based on the second clock signal 120, to a plurality of dummy pixel units in the non-display area NDA of the display panel 300 during the vertical blank section VB of the 1st frame.
The first clock signal 110 may include two signals swinging, such that their phases are symmetrical to each other between the first maximum voltage Vtop and the first minimum voltage Vbot based on the reference voltage r. The two signals may have the same period W1 and swing width SW1 even though they have symmetrical phases. Thus, the timing controller 100 may provide the first clock signal 110 having the two signals to the first signal line TL corresponding to a pair of lines during the vertical active section VA. The first clock signal 110 may have first rising time Tr1 and first falling time Tf1.
Referring to
In an embodiment, the first clock signal 110 and the second clock signal 120 have the same periods W1 and W2 and swing widths SW1 and SW2. The first rising time Tr1 is shorter than the second rising time Tr2. The first falling time Tf1 is shorter than the second falling Tf2. Therefore, the slew rate of the first clock signal 110 is higher than the slew rate of the second clock signal 120. As a result, the slope of first rising edge re1 of the first clock signal 110 is greater than the slope of second rising edge re2 of the second clock signal 120. Further, the slope of first falling edge fe1 of the first clock signal 110 is greater than the slope of second falling edge fe2 of the second clock signal 120.
Referring to
The timing controller 100 may prevent deterioration of signal integrity by providing the second clock signal 120 having a lower slew rate than the first clock signal 110 to the drive circuit unit 200 during the vertical active section VA. Thus, in at least one embodiment of the display device, the vertical active section VA and the vertical blank section VB are separated, and clock signals having different slew rates are provided to the drive circuit unit 200. In one embodiment, the timing controller 100 may provide the first clock signal 110 having a relatively high slew rate to the drive circuit unit 200 during the vertical active section VA, and the timing controller 100 may provide the second clock signal 120 having a relatively low slew rate to the drive circuit unit 200 during the vertical blank section VB.
Thus, according to an embodiment, the display device may reduce RF noise while maintaining signal integrity. Moreover, the display device may reduce power consumption by providing the second clock signal 120 having a relatively low slew rate to the drive circuit unit 200 during the vertical blank section, in which display data DD is not input in the display area DA.
The slew rate of the third clock signal 120a may be lower than the slew rate of the first clock signal 110. Therefore, the change in voltage level from the minimum voltage Vbot′ to the maximum voltage Vtop′ and the third rising time Tr3 may be different from
Referring to
In contrast, the timing controller 100 may change the first falling time Tf1 of the first clock signal 110 into a fifth falling time Tf5, so that the length of the first rising time Tr1 is equal to the length of the fifth falling time Tf5, but the length of the first rising time Tr1 of the first click signal 110 may not change. Referring to
The timing controller 100 may change the lengths of the first rising time Tr1 and first falling time Tf1 of the first clock signal 110, and may generate a clock signal in which the length of the changed first rising time Tr1 and the length of the changed first falling time Tf1 are different from each other.
In one embodiment, the vertical active section VA in the nth frame may include a plurality of horizontal active sections HA and a plurality of horizontal blank sections HB. The horizontal active section HA and the horizontal blank section HB may correspond to a horizontal synchronization signal Hsyn in which one pixel row of the display panel 300 is set to a period. A case of the kth pixel row of the 1st to nth pixel units in the display area DA will be illustratively described.
The timing controller 100 may externally receive a horizontal synchronization signal Hsync. Referring to
The timing controller 100 may provide transmission data TD to the drive circuit unit 200 during the vertical active section VA and the vertical blank section VB. However, the timing controller 100 may provide the first clock signal 110 of the transmission data TD during the vertical active section VA. Referring to
The timing controller 100 may provide the first clock signal 110 to the drive circuit unit 200 during the horizontal active section HA. The timing controller 100 may provide the second clock signal 120 to the drive circuit unit 200 during the horizontal blank section HB. The rising time Tr1 of the first clock signal 110 is shorter than the rising time Tr2 of the second clock signal 120. The period and swing width of the first clock signal may be equal to each other. Therefore, the slew rate of the first clock signal 110 may be higher than the slew rate of the second clock signal 120.
In one embodiment, the horizontal active section HA and the horizontal blank section HB are separated, the timing controller 100 may provide the first clock signal 110 having first rising time Tr1 to the drive circuit unit 200 during the horizontal active section HA, and the timing controller 100 may provide the second clock signal 120 (having second rising time Tr2 longer than the first rising time Tr1) to the drive circuit unit 200 during the horizontal blank section HB. Thus, the display device may reduce RF noise while maintaining signal integrity.
For example, the timing controller 100 may provide the first clock signal 110 to the drive circuit unit 200 only during a section in which the vertical active section VA overlaps the horizontal active section HA. For example, the timing controller 100 provide the second clock signal 120 to the drive circuit unit 200 during the vertical active section VA overlapping the horizontal blank section HB. Thus, the timing controller 100 may divide one vertical active section into a horizontal active section HA and a horizontal blank section HB according to a horizontal synchronization Hsync. The timing controller 100 may provide the first clock signal 110 having relatively short rising time to the drive circuit unit 200 during a section in which the vertical active section VA overlaps the horizontal active section HA. In contrast, the timing controller may provide the second clock signal 120 having relatively long rising time to the drive circuit unit 200 during a section in which the vertical active section VA overlaps the horizontal blank section HB.
Referring to
The first sub-output unit STx1 may output a first clock signal 110 having first rising time Tr1 and first falling time Tf1. The second sub-output unit STx2 may output a second clock signal 120 having second rising time Tr2 and second falling time Tf2. The first rising time Tr1 is shorter than the second rising time Tr2. The first falling time Tf1 is shorter than the second falling time Tf2. Thus, the timing controller 100 may be configured such that one output unit includes two sub-output units, and the sub-output units respectively output clock signals having different rising times (or falling times) from each other.
Referring to
The control unit 101 may control the output of a clock signal from one of the first to third sub-output units STx1, STx2 and STx3. For example, in the case of
The timing controller 100 may provide clock signals different from each other to a source driver through a plurality of sub-output units generating clock signals having rising times different from each other. The number of sub-output units may be different from those in
Referring to
The first output unit Tx1 may be connected with the first source driver SD1 through a first line L1. The kth output unit Txk may be connected with the kth source driver SDk through a kth line Lk. The first line L1 may be longer than the kth line Lk. Thus, the resistance of the first line L1 itself may be greater than the resistance of the kth line Lk itself. As a result, the signal provided through the first line L1 is relatively greatly influenced by noise compared to the signal provided through the kth line Lk.
Therefore, the first output unit Tx1 may provide the second clock signal 120 having the second rising time Tr2 to the first source driver SD1. The kth output unit Txk may provide the first clock signal 110 having the first rising time Tr1 to the kth source driver SDk. The first rising time Tr1 is shorten than the second rising time Tr2. As a result, the second clock signal 120 is strong to noise compared to the first clock signal 110 (e.g., refer to
The methods, processes, and/or operations described herein may be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.
The controllers, drivers, units, and the other processing features of the embodiments described herein may be implemented in logic which, for example, may include hardware, software, or both. When implemented at least partially in hardware, the controllers, drivers, units, and other processing features may be, for example, integrated circuits including but not limited to an application-specific integrated circuit, a field-programmable gate array, a combination of logic gates, a system-on-chip, a microprocessor, or another type of processing or control circuit.
When implemented in at least partially in software, the controllers, drivers, units, and other processing features may include, for example, a memory or other storage device for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2016-0106906 | Aug 2016 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 7948465 | Cho et al. | May 2011 | B2 |
| 9240159 | Na et al. | Jan 2016 | B2 |
| 20100134401 | Shin | Jun 2010 | A1 |
| 20100156885 | Cho | Jun 2010 | A1 |
| 20170285793 | Shamarao | Oct 2017 | A1 |
| Number | Date | Country |
|---|---|---|
| 10-2010-0073718 | Jul 2010 | KR |
| Number | Date | Country | |
|---|---|---|---|
| 20180061362 A1 | Mar 2018 | US |
