DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE

TECHNICAL FIELD

The disclosure relates to display devices and methods of manufacturing display devices.

BACKGROUND ART

The organic EL display device, or the self-luminous display device built around organic electroluminescence elements (hereinafter, may be referred to as “organic EL elements”), has been attracting attention as a promising successor to the liquid crystal display device. The organic EL display device includes a plurality of thin film transistors (hereinafter, may be referred to as “TFTs”) in each subpixel which provides a minimum unit of images. Well-known examples of a semiconductor layer in such a TFT include a semiconductor layer of a polysilicon which exhibits high mobility and a semiconductor layer of an oxide semiconductor such as In—Ga—Zn—O which causes small leakage current.

As an example, JP 2020-17558 A discloses a display device having a hybrid structure in which polysilicon semiconductor-based, first TFTs and oxide semiconductor-based, second TFTs are both formed on a substrate.

CITATION LIST
Patent Literature
SUMMARY
Technical Problem

Meanwhile, in the display device having a hybrid structure disclosed in JP 2020-17558 A mentioned above, contact holes can be collectively formed for electrically connecting to the polysilicon semiconductor and the oxide semiconductor because a metal film is brought into contact with the oxide semiconductor with the contact holes being formed through the metal film. However, it is difficult to simultaneously perform ion doping on the polysilicon semiconductor and the oxide semiconductor in the display device having a hybrid structure disclosed in JP 2020-17558 A mentioned above, because the insulating film on the polysilicon semiconductor and the insulating film on the oxide semiconductor have different thicknesses. There is room for improvement here.

The disclosure has been made in view of these issues and has an object to collectively form contact holes for electrically connecting to polysilicon-based and oxide semiconductor-based semiconductor layers and also to simultaneously perform ion doping on these semiconductor layers.

Solution to Problem

To achieve the object, a display device in accordance with the disclosure includes: a base substrate layer; and a thin film transistor layer on the base substrate layer, the thin film transistor layer including, in each of a plurality of subpixels: a first thin film transistor including a first semiconductor layer of a polysilicon; and a second thin film transistor including a second semiconductor layer of an oxide semiconductor, wherein the first thin film transistor includes: the first semiconductor layer including a first conductive region and a second conductive region at a distance from each other; a first gate insulating film on the first semiconductor layer; a first gate electrode on the first gate insulating film, the first gate electrode being configured to control conduction between the first conductive region and the second conductive region; an interlayer insulating film covering the first gate electrode; and a first terminal electrode and a second terminal electrode on the interlayer insulating film at a distance from each other, the first terminal electrode and the second terminal electrode being electrically connected respectively to the first conductive region and the second conductive region via a first contact hole and a second contact hole formed at least through the interlayer insulating film, the second thin film transistor includes: the second semiconductor layer including a third conductive region and a fourth conductive region at a distance from each other; a first conductive layer and a second conductive layer on a base substrate layer side of the third conductive region and the fourth conductive region respectively, the first conductive layer and the second conductive layer being made of a same material, and provided in a same layer, as the first semiconductor layer; a second gate insulating film on the second semiconductor layer; a second gate electrode on the second gate insulating film, the second gate electrode being configured to control conduction between the third conductive region and the fourth conductive region; the interlayer insulating film covering the second gate electrode; and a third terminal electrode and a fourth terminal electrode on the interlayer insulating film at a distance from each other, the third terminal electrode and the fourth terminal electrode being electrically connected respectively to the first conductive layer and the second conductive layer via a third contact hole and a fourth contact hole formed at least through the interlayer insulating film, and the second gate insulating film is made of a same material, and provided in a same layer, as the first gate insulating film.

In addition, a method of manufacturing a display device in accordance with the disclosure is a method of manufacturing a display device including: a base substrate layer; and a thin film transistor layer on the base substrate layer, the thin film transistor layer including, in each of a plurality of subpixels: a first thin film transistor including a first semiconductor layer of a polysilicon; and a second thin film transistor including a second semiconductor layer of an oxide semiconductor, wherein the first thin film transistor includes: the first semiconductor layer including a first conductive region and a second conductive region at a distance from each other; a first gate insulating film on the first semiconductor layer; a first gate electrode on the first gate insulating film, the first gate electrode being configured to control conduction between the first conductive region and the second conductive region; an interlayer insulating film covering the first gate electrode; and a first terminal electrode and a second terminal electrode on the interlayer insulating film at a distance from each other, the first terminal electrode and the second terminal electrode being electrically connected respectively to the first conductive region and the second conductive region via a first contact hole and a second contact hole formed at least through the interlayer insulating film, and the second thin film transistor includes: the second semiconductor layer including a third conductive region and a fourth conductive region at a distance from each other; a first conductive layer and a second conductive layer on a base substrate layer side of the third conductive region and the fourth conductive region respectively, the first conductive layer and the second conductive layer being made of a same material, and provided in a same layer, as the first semiconductor layer; a second gate insulating film on the second semiconductor layer; a second gate electrode on the second gate insulating film, the second gate electrode being configured to control conduction between the third conductive region and the fourth conductive region; the interlayer insulating film covering the second gate electrode; and a third terminal electrode and a fourth terminal electrode on the interlayer insulating film at a distance from each other, the third terminal electrode and the fourth terminal electrode being electrically connected respectively to the first conductive layer and the second conductive layer via a third contact hole and a fourth contact hole formed at least through the interlayer insulating film, the method including: a first semiconductor layer formation step of forming, on the base substrate layer, the first semiconductor layer, a first polysilicon layer that will be the first conductive layer, and a second polysilicon layer that will be the second conductive layer; a second semiconductor layer formation step of forming the second semiconductor layer on the first polysilicon layer and the second polysilicon layer; a gate insulating film formation step of forming the first gate insulating film and the second gate insulating film so as to cover the first semiconductor layer and the second semiconductor layer respectively; a gate electrode formation step of forming the first gate electrode and the second gate electrode on the first gate insulating film and the second gate insulating film respectively; an ion doping step of forming the first conductive region and the second conductive region in the first semiconductor layer and forming the third conductive region and the fourth conductive region in the second semiconductor layer by doping the first semiconductor layer with impurity ions using the first gate electrode as a mask and also doping the second semiconductor layer, the first polysilicon layer, and the second polysilicon layer with impurity ions using the second gate electrode as a mask and of forming the first conductive layer and the second conductive layer by modifying the first polysilicon layer and the second polysilicon layer into a conductor; an interlayer insulating film formation step of, after the interlayer insulating film is formed so as to cover the first gate electrode and the second gate electrode, forming the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole at least through the interlayer insulating film; and a terminal electrode formation step of forming the first terminal electrode, the second terminal electrode, the third terminal electrode, and the fourth terminal electrode on the interlayer insulating film.

Advantageous Effects of Disclosure

The disclosure enables collectively forming contact holes for electrically connecting to polysilicon-based and oxide semiconductor-based semiconductor layers and also simultaneously performing ion doping on these semiconductor layers.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic plan view of a structure of an organic EL display device in accordance with a first embodiment of the disclosure.

FIG. 2 is a plan view of a display area of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 3 is a cross-sectional view of the display area of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 4 is an equivalent circuit diagram of a TFT layer that is a part of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 5 is a cross-sectional view of an organic EL layer that is a part of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 6 is a cross-sectional view of a first variation example of the TFT layer that is a part of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 7 is a cross-sectional view of a second variation example of the TFT layer that is a part of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 8 is a cross-sectional view of a third variation example of the TFT layer that is a part of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 9 is a first cross-sectional view of a part of the manufacture of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 10 is a second cross-sectional view, which follows FIG. 9, of a part of the manufacture of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 11 is a third cross-sectional view, which follows FIG. 10, of a part of the manufacture of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 12 is a fourth cross-sectional view, which follows FIG. 11, of a part of the manufacture of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 13 is a fifth cross-sectional view, which follows FIG. 12, of a part of the manufacture of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 14 is a sixth cross-sectional view, which follows FIG. 13, of a part of the manufacture of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 15 is a seventh cross-sectional view, which follows FIG. 14, of a part of the manufacture of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 16 is an eighth cross-sectional view, which follows FIG. 15, of a part of the manufacture of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 17 is a ninth cross-sectional view, which follows FIG. 16, of a part of the manufacture of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 18 is a tenth cross-sectional view, which follows FIG. 17, of a part of the manufacture of the organic EL display device in accordance with the first embodiment of the disclosure.

FIG. 19 is a cross-sectional view of a display area of a TFT layer that is a part of an organic EL display device in accordance with a second embodiment of the disclosure.

FIG. 20 is a first cross-sectional view of a part of the manufacture of an organic EL display device in accordance with a third embodiment of the disclosure.

FIG. 21 is a second cross-sectional view, which follows FIG. 20, of a part of the manufacture of the organic EL display device in accordance with the third embodiment of the disclosure.

FIG. 22 is a first cross-sectional view of a part of the manufacture of a variation example of the organic EL display device in accordance with the third embodiment of the disclosure.

FIG. 23 is a second cross-sectional view, which follows FIG. 22, of a part of the manufacture of the variation example of the organic EL display device in accordance with the third embodiment of the disclosure.

DESCRIPTION OF EMBODIMENTS

The following will describe embodiments of the disclosure in detail with reference to drawings. Note that the disclosure is not limited to these embodiments.

First Embodiment

FIGS. 1 to 18 illustrate a first embodiment of a display device and a method of manufacturing a display device, both in accordance with the disclosure. Note that each embodiment below will discuss an organic EL display device including an organic EL element layer as an example of a display device including a light-emitting element layer. Here, FIG. 1 is a schematic plan view of a structure of an organic EL display device 50 in accordance with the present embodiment. In addition, FIGS. 2 and 3 are a plan view and a cross-sectional view, respectively, of a display area D of the organic EL display device 50. In addition, FIG. 4 is an equivalent circuit diagram of a TFT layer 30a that is a part of the organic EL display device 50. In addition, FIG. 5 is a cross-sectional view of an organic EL layer 33 that is a part of the organic EL display device 50. In addition, FIGS. 6, 7, and 8 are cross-sectional views of a TFT layer 30aa, a TFT layer 30ab, and a TFT layer 30ac representing a first, a second, and a third variation example respectively of the TFT layer 30a.

Referring to FIG. 1, the organic EL display device 50 has, for example, the rectangular display area D for producing image displays and a frame area F surrounding the display area D. Note that the present embodiment gives the rectangular display area D as an example. This rectangular shape encompasses, for example, generally rectangular shapes such as those with a curved side(s), those with a round corner(s), and those with a notched side(s).

There is provided a matrix of subpixels P in the display area D as shown in FIG. 2. In addition, in the display area D, for example, subpixels P each including a red-light-emission region Er for a display in red, a subpixel P including a green-light-emission region Eg for a display in green, and a subpixel P including a blue-light-emission region Eb for a display in blue are provided adjacent to each other as shown in FIG. 2. Note that each pixel in the display area D is formed by, for example, three adjacent subpixels P including a red-light-emission region Er, a green-light-emission region Eg, and a blue-light-emission region Eb.

The frame area F includes a terminal section T along the far right side of the frame area F as in FIG. 1. In addition, the frame area F further includes a bending portion B extending in one direction (in the vertical direction in the drawing) between the display area D and the terminal section T as shown in FIG. 1. The bending portion B can be bent 180° around the vertical direction in the drawing (to form a U-shape).

Referring to FIG. 3, the organic EL display device 50 includes: a resin substrate layer 10 as a base-providing substrate (base substrate); the TFT layer 30a on the resin substrate layer 10; an organic EL element layer 40 as a light-emitting element layer on the TFT layer 30a; and a sealing film 45 covering the organic EL element layer 40.

The resin substrate layer 10 is made of, for example, a polyimide resin.

Referring to FIG. 3, the TFT layer 30a includes: a base coat film 11 on the resin substrate layer 10; four first TFTs 9A, three second TFTs 9B, and one capacitor 9h, all on the base coat film 11, in each subpixel P (see FIG. 4); and a planarization film 20 on the first TFTs 9A, the second TFTs 9B, and the capacitor 9h. Here, the TFT layer 30a includes a plurality of gate lines 15g extending parallel to each other in the lateral direction in the drawing as shown in FIG. 2. In addition, the TFT layer 30a includes a plurality of light-emission control lines 15e extending parallel to each other in the lateral direction in the drawing, as shown in FIG. 2. In addition, the TFT layer 30a includes a plurality of second initialization power supply lines 17i extending parallel to each other in the lateral direction in the drawing, as shown in FIG. 2. Note that each light-emission control line 15e is provided adjacent to an associated one of the gate lines 15g and an associated one of the second initialization power supply lines 17i as shown in FIG. 2. In addition, the TFT layer 30a includes a plurality of source lines 19f extending parallel to each other in the vertical direction in the drawing as shown in FIG. 2. In addition, the TFT layer 30a includes a plurality of power supply lines 19g extending parallel to each other in the vertical direction in the drawing as shown in FIG. 2. Note that each power supply line 19g is provided adjacent to an associated one of the source lines 19f as shown in FIG. 2. In addition, the gate lines 15g and the light-emission control lines 15e are provided on a gate insulating film 14 (detailed later), the second initialization power supply lines 17i are provided on a first interlayer insulating film 16 (detailed later), and the source lines 19f and the power supply lines 19g are provided on a second interlayer insulating film 18 (detailed later).

Referring to FIG. 3, each first TFT 9A includes: a first semiconductor layer 12a on the base coat film 11; the gate insulating film 14 on the first semiconductor layer 12a; a first gate electrode 15a on the gate insulating film 14; the first interlayer insulating film 16 and the second interlayer insulating film 18 sequentially provided so as to cover the first gate electrode 15a; and a first terminal electrode 19a and a second terminal electrode 19b on the second interlayer insulating film 18 at a distance from each other.

The base coat film 11, the gate insulating film 14, the first interlayer insulating film 16, and the second interlayer insulating film 18 each include either a monolayer film of, for example, an inorganic insulating film such as silicon nitride, silicon oxide, or silicon oxynitride or a stack of any of these films. Here, at least the base coat film 11 and the gate insulating film 14 include, for example, a silicon oxide film on the second semiconductor layer 13a side thereof (detailed later).

The first gate electrode 15a overlaps a first channel region 12ac (detailed later) of the first semiconductor layer 12a and to control conduction between a first conductive region 12aa and a second conductive region 12ab (both detailed later) of the first semiconductor layer 12a, as shown in FIG. 3.

The first semiconductor layer 12a contains, for example, a polysilicon such as LTPS (low temperature polysilicon) and includes: the first conductive region 12aa and the second conductive region 12ab at a distance from each other; and the first channel region 12ac between the first conductive region 12aa and the second conductive region 12ab, as shown in FIG. 3.

The first terminal electrode 19a and the second terminal electrode 19b are electrically connected respectively to the first conductive region 12aa and the second conductive region 12ab of the first semiconductor layer 12a via a first contact hole Ha and a second contact hole Hb formed through the stack of the gate insulating film 14, the first interlayer insulating film 16, and the second interlayer insulating film 18, as shown in FIG. 3.

Referring to FIG. 3, each second TFT 9B includes: a second semiconductor layer 13a on the base coat film 11; a first conductive layer 12b and a second conductive layer 12c on the resin substrate layer 10 side of a third conductive region 13aa and a fourth conductive region 13ab (both detailed later) of the second semiconductor layer 13a respectively; the gate insulating film 14 on the second semiconductor layer 13a, the first conductive layer 12b, and the second conductive layer 12c; a second gate electrode 15b on the gate insulating film 14; the first interlayer insulating film 16 and the second interlayer insulating film 18 sequentially provided so as to cover the second gate electrode 15b; and a third terminal electrodes 19c and a fourth terminal electrode 19d on the second interlayer insulating film 18 at a distance from each other.

The second semiconductor layer 13a contains, for example, an oxide semiconductor such as an In—Ga—Zn—O-based semiconductor and includes: the third conductive region 13aa and the fourth conductive region 13ab at a distance from each other; and a second channel region 13ac between the third conductive region 13aa and the fourth conductive region 13ab, as shown in FIG. 3. Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportion (composition ratio) of In, Ga, and Zn is not limited in any particular manner. In addition, the In—Ga—Zn—O-based semiconductor may be either amorphous or crystalline. Note that a preferred In—Ga—Zn—O-based crystalline semiconductor is an In—Ga—Zn—O-based crystalline semiconductor in which the c axis is oriented substantially perpendicularly to the layer plane. The second semiconductor layer 13a may contain an alternative oxide semiconductor in place of the In—Ga—Zn—O-based semiconductor. The alternative oxide semiconductor may be, for example, an In—Sn—Zn—O-based semiconductor (e.g., In₂O₃—SnO₂—ZnO; InSnZnO). Here, the In—Sn—Zn—O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). In addition, the second semiconductor layer 13a may contain another oxide semiconductor such as an In—Al—Zn—O-based semiconductor, an In—Al—Sn—Zn—O—based semiconductor, a Zn—O-based semiconductor, an In—Zn—O-based semiconductor, a Zn—Ti—O-based semiconductor, a Cd—Ge—O-based semiconductor, a Cd—Pb—O-based semiconductor, CdO (cadmium oxide), a Mg—Zn—O-based semiconductor, an In—Ga—Sn—O-based semiconductor, an In—Ga—O-based semiconductor, a Zr—In—Zn—O-based semiconductor, a Hf—In—Zn—O-based semiconductor, an Al—Ga—Zn—O-based semiconductor, a Ga—Zn—O-based semiconductor, an In—Ga—Zn—Sn—O-based semiconductor, InGaO₃(ZnO)₅, magnesium zinc oxide (Mg_xZn_1-xO), or cadmium zinc oxide (Cd_xZn_1-xO). Note that the Zn—O-based semiconductor may be ZnO that may or may not be doped with at least one of impurity element species of, for example, Group 1 elements, Group 13 elements, Group 14 elements, Group 15 elements, and Group 17 elements and that may be amorphous, polycrystalline, or microcrystal where a mixed combination of amorphous ZnO and polycrystalline ZnO is present.

The first conductive layer 12b and the second conductive layer 12c are provided in contact with the resin substrate layer 10 side of the third conductive region 13aa and the fourth conductive region 13ab on the ends of the second semiconductor layer 13a respectively, as shown in FIG. 3. Here, the first conductive layer 12b and the second conductive layer 12c contain, for example, a polysilicon doped with impurity ions such as phosphorus and are made of the same material, and provided in the same layer, as the first semiconductor layer 12a.

Referring to FIG. 3, the second gate electrode 15b overlaps the second channel region 13ac of the second semiconductor layer 13a to control conduction between the third conductive region 13aa and the fourth conductive region 13ab of the second semiconductor layer 13a.

The third terminal electrode 19c and the fourth terminal electrode 19d are electrically connected respectively to the first conductive layer 12b and the second conductive layer 12c via a third contact hole Hc and a fourth contact hole Hd formed through the stack of the gate insulating film 14, the first interlayer insulating film 16, and the second interlayer insulating film 18, as shown in FIG. 3.

The present embodiment discusses a write TFT 9c, a drive TFT 9d, a power supply TFT 9e, and a light-emission control TFT 9f (all detailed later) as an example of the four first TFTs 9A including the first semiconductor layer 12a of a polysilicon and also discusses an initialization TFT 9a, a compensation TFT 9b, and an anode discharge TFT 9g (all detailed later) as an example of the three second TFTs 9B including the second semiconductor layer 13a of an oxide semiconductor (see FIG. 4). Note that the equivalent circuit diagram in FIG. 4 denotes a first terminal electrode 20a and a second terminal electrode 20b of each TFT 9c, 9d, 9e, and 9f by a circled 1 and a circled 2 and denotes a third terminal electrode 20c and a fourth terminal electrode 20d of each TFTs 9a, 9b, and 9g by a circled 3 and a circled 4. In addition, the equivalent circuit diagram in FIG. 4 shows a pixel circuit for the subpixel P that is located in row n, column m and also shows a part of a pixel circuit for the subpixel P that is located in row (n-1), column m. In addition, the equivalent circuit diagram in FIG. 4 shows that the power supply line 19g for supplying a high-voltage power supply ELVDD doubles as a first initialization power supply line. Alternatively, the power supply line 19g and the first initialization power supply line may be provided separately. In addition, the second initialization power supply line 17i is fed with the same voltage as a low-voltage power supply ELVSS. This is however not the only possible implementation of the disclosure. Alternatively, the second initialization power supply line 17i may be fed with a voltage that differs from the low-voltage power supply ELVSS and that can turn off an organic EL element 35 (detailed later).

Referring to FIG. 4, the initialization TFT 9a, in each subpixel P, is electrically connected at the gate electrode thereof to a gate line 15g(n-1) of the preceding stage (n-1-th stage), at a third terminal electrode thereof to a lower conductive layer (detailed later) of the capacitor 9h and to the gate electrode of the drive TFT 9d, and at a fourth terminal electrode thereof to the power supply line 19g.

Referring to FIG. 4, the compensation TFT 9b, in each subpixel P, is electrically connected at the gate electrode thereof to a gate line 15g(n) of the current stage (n-th stage), at a third terminal electrode thereof to the gate electrode of the drive TFT 9d, and at a fourth terminal electrode thereof to a first terminal electrode of the drive TFT 9d.

Referring to FIG. 4, the write TFT 9c, in each subpixel P, is electrically connected at the gate electrode thereof to the gate line 15g(n) of the current stage (n-th stage), at the first terminal electrode thereof to an associated one of the source lines 19f, and at a second terminal electrode thereof to a second terminal electrode of the drive TFT 9d.

Referring to FIG. 4, the drive TFT 9d, in each subpixel P, is electrically connected at the gate electrode thereof to the third terminal electrodes of the initialization TFT 9a and the compensation TFT 9b, at the first terminal electrode thereof to the fourth terminal electrode of the compensation TFT 9b and to a second terminal electrode of the power supply TFT 9e, and at the second terminal electrode thereof to the second terminal electrode of the write TFT 9c and to a first terminal electrode of the light-emission control TFT 9f. Here, the drive TFT 9d is configured to control the electric current in the organic EL element 35.

Referring to FIG. 4, the power supply TFT 9e, in each subpixel P, is electrically connected at the gate electrode thereof to the light-emission control line 15e of the current stage (n-th stage), at a first terminal electrode thereof to the power supply line 19g, and at the second terminal electrode thereof to the first terminal electrode of the drive TFT 9d.

Referring to FIG. 4, the light-emission control TFT 9f, in each subpixel P, is electrically connected at the gate electrode thereof to the light-emission control line 15e of the current stage (n-th stage), at the first terminal electrode thereof to the second terminal electrode of the drive TFT 9d, and at a second terminal electrode thereof to a first electrode 31 (detailed later) of the organic EL element 35 (detailed later).

Referring to FIG. 4, the anode discharge TFT 9g, in each subpixel P, is electrically connected at the gate electrode thereof to the gate line 15g(n) of the current stage (n-th stage), at the third terminal electrode thereof to the first electrode 31 of the organic EL element 35, and at a fourth terminal electrode thereof to the second initialization power supply line 17i.

The capacitor 9h includes, for example: a lower conductive layer (not shown) made of the same material, and provided in the same layer, as the first gate electrode 15a and the second gate electrode 15b; the first interlayer insulating film 16 provided so as to cover the lower conductive layer; and an upper conductive layer (not shown) provided on the first interlayer insulating film 16 so as to overlap the lower conductive layer and made of the same material, and provided in the same layer, as the second initialization power supply line 17i. In addition, referring to FIG. 4, the capacitor 9h, in each subpixel P, is electrically connected at the lower conductive layer thereof to the gate electrode of the drive TFT 9d and also to the third terminal electrodes of the initialization TFT 9a and the compensation TFT 9b and at the upper conductive layer thereof to the third terminal electrode of the anode discharge TFT 9g, to the second terminal electrode of the light-emission control TFT 9f, and to the first electrode 31 of the organic EL element 35.

The planarization film 20 has a flat face in the display area D and is made of, for example, either an organic resin material, such as a polyimide resin or an acrylic resin, or a polysiloxane-based SOG (spin on glass) material.

Note that the present embodiment discusses, as an example, the TFT layer 30a in which the first semiconductor layer 12a and the first conductive layer 12b are separated from each other. Alternatively, the first TFT 9A and the second TFT 9B may have, in some parts thereof, a structure of the TFT layer 30aa, the TFT layer 30ab, and the TFT layer 30ac as shown in FIGS. 6, 7, and 8, respectively.

In a portion of the TFT layer 30aa where the second conductive region 12ab of the first TFT 9A and the first conductive layer 12b of the second TFT 9B are electrically connected, the first conductive layer 12b (see FIG. 3) of the second TFT 9B is formed integrally to the second conductive region 12ab of the first TFT 9A and omitted, as shown in FIG. 6. This TFT layer 30aa obviates the need for a space for contact holes, thereby enabling reducing the area occupied by TFTs in each subpixel and hence increasing freedom in designing high definition display devices.

Similarly to the TFT layer 30aa, in a portion of the TFT layer 30ab where the second conductive region 12ab of the first TFT 9A and the first conductive layer 12b of the second TFT 9B are electrically connected, the first conductive layer 12b (see FIG. 3) of the second TFT 9B is formed integrally to the second conductive region 12ab of the first TFT 9A and omitted, as shown in FIG. 7. Then, in the TFT layer 30ab, the second conductive region 12ab is provided longer for utilization ss a wiring line and electrically connected to the source line 19f, which has a lower electrical resistance. This TFT layer 30ab enables utilization of the second conductive region 12ab as a local wiring line, thereby facilitating wiring layout and hence improving the manufacturing yield.

Similarly to the TFT layer 30aa, in a portion of the TFT layer 30ac where the second conductive region 12ab of the first TFT 9A and the first conductive layer 12b of the second TFT 9B are electrically connected, the first conductive layer 12b (see FIG. 3) of the second TFT 9B is formed integrally to the second conductive region 12ab of the first TFT 9A and omitted, as shown in FIG. 8. Then, in the TFT layer 30ac, the third conductive region 13aa is provided longer for utilization as a wiring line and electrically connecting the second conductive region 12ab and the source line 19f that are in contact with the third conductive region 13aa. This TFT layer 30acenables utilization of the third conductive region 13aa as a local wiring line, thereby facilitating wiring layout and improving the manufacturing yield.

Referring to FIG. 3, the organic EL element layer 40 includes: the plurality of organic EL elements 35, as a plurality of light-emitting elements, arranged in a matrix to correspond to the plurality of subpixels P; and an edge cover 32 arranged like a lattice commonly to all the subpixels P so as to cover a peripheral end portion of the first electrode 31 in each organic EL element 35.

Referring to FIG. 3, the organic EL element 35, in each subpixel P, includes: the first electrode 31 on the planarization film 20 of the TFT layer 30a; the organic EL layer 33 on the first electrode 31; and a second electrode 34 on the organic EL layer 33.

The first electrode 31 is electrically connected to the second terminal electrode of the light-emission control TFT 9f in each subpixel P via a contact hole formed through the planarization film 20. In addition, the first electrode 31 has a function of injecting holes to the organic EL layer 33. In addition, the first electrode 31 is more preferably made of a material having a large work function to improve the efficiency of hole injection to the organic EL layer 33. Here, the first electrode 31 may be made of, for example, a metal material such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), or tin (Sn). Alternatively, the first electrode 31 may be made of, for example, an alloy such as an astatine-astatine oxide (At—AtO₂) alloy. Furthermore, the first electrode 31 may be made of, for example, an electrically conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Alternatively, the first electrode 31 may include a stack of a plurality of layers of any of these materials. Note that examples of the compound material having a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).

Referring to FIG. 5, the organic EL layer 33 includes a hole injection layer 1, a hole transport layer 2, a light-emitting layer 3, an electron transport layer 4, and an electron injection layer 5, which are sequentially provided on the first electrode 31.

The hole injection layer 1 is alternatively referred to as the anode buffer layer and has a function of bringing the energy levels of the first electrode 31 and the organic EL layer 33 close to each other, to improve the efficiency of hole injection from the first electrode 31 to the organic EL layer 33. Here, the hole injection layer 1 is made of, for example, a triazole derivative, an oxadiazole derivative, an imidazole derivative, a polyaryl alkane derivative, a pyrazoline derivative, a phenylenediamine derivative, an oxazole derivative, a styrylanthracene derivative, a fluorenone derivative, a hydrazone derivative, or a stilbene derivative.

The hole transport layer 2 has a function of improving the efficiency of hole transport from the first electrode 31 to the organic EL layer 33. Here, the hole transport layer 2 is made of, for example, a porphyrin derivative, an aromatic tertiary amine compound, a styryl amine derivative, polyvinyl carbazole, poly-p-phenylene vinylene, polysilane, a triazole derivative, an oxadiazole derivative, an imidazole derivative, a polyaryl alkane derivative, a pyrazoline derivative, a pyrazolone derivative, a phenylenediamine derivative, an aryl amine derivative, an amine-substituted chalcone derivative, an oxazole derivative, a styrylanthracene derivative, a fluorenone derivative, a hydrazone derivative, a stilbene derivative, a hydrogenated amorphous silicon, a hydrogenated amorphous silicon carbide, zinc sulfide, or zinc selenide.

The light-emitting layer 3 is injected with holes and electrons from the first electrode 31 and the second electrode 34 respectively when the light-emitting layer 3 is under a voltage applied by the first electrode 31 and the second electrode 34. These holes and electrons recombine in the light-emitting layer 3. Here, the light-emitting layer 3 is made of a material that has a high luminous efficiency. Then, the light-emitting layer 3 is made of, for example, a metal oxinoid compound [8-hydroxy quinoline metal complex], a naphthalene derivative, an anthracene derivative, a diphenyl ethylene derivative, a vinyl acetone derivative, a triphenyl amine derivative, a butadiene derivative, a coumarin derivative, a benzoxazole derivative, an oxadiazole derivative, an oxazole derivative, a benzimidazole derivative, a thiadiazole derivative, a benzothiazole derivative, a styryl derivative, a styryl amine derivative, a bis(styryl)benzene derivative, a tris(styryl)benzene derivative, a perylene derivative, a perynone derivative, an amino pyrene derivative, a pyridine derivative, a rhodamine derivative, an acridine derivative, phenoxazone, a quinacridone derivative, rubrene, poly-p-phenylene vinylene, or polysilane.

The electron transport layer 4 has a function of efficiently transporting electrons to the light-emitting layer 3. Here, the electron transport layer 4 is made of, for example, an organic compound such as an oxadiazole derivative, a triazole derivative, a benzoquinone derivative, a naphthoquinone derivative, an anthraquinone derivative, a tetracyanoanthraquinodimethane derivative, a diphenoquinone derivative, a fluorenone derivative, a silole derivative, or a metal oxinoid compound.

The electron injection layer 5 has a function of bringing the energy levels of the second electrode 34 and the organic EL layer 33 clos to each other, to improve the efficiency of electron injection from the second electrode 34 to the organic EL layer 33. This function enables lowering the drive voltage of the organic EL element 35. Note that the electron injection layer 5 is alternatively referred to as the cathode buffer layer. Here, the electron injection layer 5 is made of, for example, an inorganic alkali compound such as lithium fluoride (LiF), magnesium fluoride (MgF₂), calcium fluoride (CaF₂), strontium fluoride (SrF₂), or barium fluoride (BaF₂), aluminum oxide (Al₂O₃), or strontium oxide (SrO).

Referring to FIG. 3, the second electrode 34 is provided commonly to all the subpixels P so as to cover the organic EL layers 33 and the edge cover 32. In addition, the second electrode 34 has a function of injecting electrons to the organic EL layer 33. In addition, the second electrode 34 is more preferably made of a material that has a small work function to improve the efficiency of electron injection to the organic EL layer 33. Here, the second electrode 34 is made of, for example, silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), or lithium fluoride (LiF). Alternatively, the second electrode 34 may be made of, for example, an alloy such as a magnesium-copper (Mg—Cu) alloy, a magnesium-silver (Mg—Ag) alloy, a sodium-potassium (Na—K) alloy, an astatine-astatine oxide (At—AtO₂) alloy, a lithium-aluminum (Li—Al) alloy, a lithium-calcium-aluminum (Li—Ca—Al) alloy, or a lithium fluoride-calcium-aluminum (LiF—Ca—Al) alloy. Alternatively, the second electrode 34 may be made of, for example, an electrically conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). In addition, the second electrode 34 may include a stack of layers of any of these materials. Note that examples of the material that has a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), a magnesium-copper (Mg—Cu) alloy, a magnesium-silver (Mg—Ag) alloy, a sodium-potassium (Na—K) alloy, a lithium-aluminum (Li—Al) alloy, a lithium-calcium-aluminum (Li—Ca—Al) alloy, and a lithium fluoride-calcium-aluminum (LiF—Ca—Al) alloy.

The edge cover 32 is made of, for example, either an organic resin material, such as a polyimide resin or an acrylic resin, or a polysiloxane-based SOG material.

Referring to FIG. 3, the sealing film 45 covers the second electrode 34, includes a first inorganic sealing film 41, an organic sealing film 42, and a second inorganic sealing film 43, which are sequentially stacked on the second electrode 34, and has a function of protecting the organic EL layer 33 in the organic EL element layer 35 from, for example, water and oxygen.

The first inorganic sealing film 41 and the second inorganic sealing film 43 include, for example, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film.

The organic sealing film 42 contains, for example, an organic resin material such as an acrylic resin, an epoxy resin, a silicone resin, a polyurea resin, a parylene resin, a polyimide resin, or a polyamide resin.

In the organic EL display device 50 structured as above, in each subpixel P, first of all, as the light-emission control line 15e is selected and deactivated, the organic EL element 35 is turned into a non-emissive state. In that non-emissive state, the gate line 15g(n-1) of the preceding stage is selected to feed a gate signal to the initialization TFT 9a via the gate line 15g(n-1), which turns on the initialization TFT 9a. Accordingly, the high-voltage power supply ELVDD on the power supply line 19g is applied to the capacitor 9h, and the drive TFT 9d is turned on. Hence, the capacitor 9h discharges, initializing voltage across the gate electrode of the drive TFT 9d. Next, as the gate line 15g(n) of the current stage is selected and activated, the compensation TFT 9b and the write TFT 9c are turned on, and a prescribed voltage corresponding to the source signal transferred via the corresponding source line 19f is written to the capacitor 9h via the diode-connected drive TFT 9d. Furthermore, the anode discharge TFT 9g is turned on, so that an initialization signal is applied to the first electrode 31 of the organic EL element 35 via the second initialization power supply line 17i, thereby resetting the electric charge stored in the first electrode 31. Thereafter, the light-emission control line 15e is selected to turn on the power supply TFT 9e and the light-emission control TFT 9f, thereby feeding a drive current in accordance with a voltage across the gate electrode of the drive TFT 9d from the power supply line 19g to the organic EL element 35. In this manner, in each subpixel P in the organic EL display device 50, the organic EL element 35 emits light with a luminance that is in accordance with the drive current to produce an image display.

Next, a description is given of a method of manufacturing the organic EL display device 50 in accordance with the present embodiment. The method of manufacturing the organic EL display device 50 includes a TFT layer formation step, an organic EL element layer formation step, and a sealing film formation step. Here, FIGS. 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18 are a first, a second, a third, a fourth, a fifth, a sixth, a seventh, an eighth, a ninth, and a tenth cross-sectional view of a successive part of the TFT layer formation step of the method of manufacturing an organic EL display device.

TFT Layer Formation Step

First, the base coat film 11 is formed by sequentially forming a silicon nitride film (approximately 50 nm) and a silicon oxide film (to a thickness of approximately 250 nm) by, for example, plasma CVD (chemical vapor deposition) on, for example, the resin substrate layer 10 formed on a glass substrate.

Subsequently, an amorphous silicon film (having a thickness of approximately 50 nm) is formed by, for example, plasma CVD on the substrate on which the base coat film 11 has been formed, and the amorphous silicon film is then crystallized by, for example, laser annealing to form a polysilicon film 12, as shown in FIG. 9. Thereafter, the polysilicon film 12 is patterned to form the first semiconductor layer 12a, a first polysilicon layer 12bp, and a second polysilicon layer 12cp as shown in FIG. 10 (first semiconductor layer formation step).

Furthermore, referring to FIG. 11, an oxide semiconductor film 13 of, for example, InGaZnO₄is formed (to a thickness of approximately 30 nm) by, for example, sputtering on the surface of the substrate on which the first semiconductor layer 12a, the first polysilicon layer 12bp, and the second polysilicon layer 12cp have been formed. Thereafter, the second semiconductor layer 13a is formed by patterning the oxide semiconductor film 13 as shown in FIG. 12 (second semiconductor layer formation step). Note that the film quality of the oxide semiconductor may be improved by annealing after the second semiconductor layer 13a is formed.

Subsequently, as silicon oxide film is formed (to a thickness of approximately 100 nm) by, for example, plasma CVD on the surface of the substrate on which the second semiconductor layer 13a has been formed, to form the gate insulating film 14, as shown in FIG. 13. Thereafter, a metal film 15 such as a molybdenum film is formed (to a thickness of approximately 200 nm) by, for example, sputtering (gate insulating film formation step). Thereafter, the metal film 15 is patterned to form the first gate electrode 15a and the second gate electrode 15b as shown in FIG. 14 (gate electrode formation step). Note that the gate lines 15g and the light-emission control lines 15e are also formed in forming the first gate electrode 15a and the second gate electrode 15b.

Furthermore, the first conductive region 12aa, the second conductive region 12ab, and the first channel region 12ac are formed in the first semiconductor layer 12a, and the third conductive region 13aa, the fourth conductive region 13ab, and the second channel region 13ac are formed in the second semiconductor layer 13a, by doping with impurity ions Ip of, for example, phosphorus using the first gate electrode 15a and the second gate electrode 15b as a mask as shown in FIG. 15. The first polysilicon layer 12bp and the second polysilicon layer 12cp are then modified into a conductor to form the first conductive layer 12b and the second conductive layer 12c (ion doping step). Note that after the doping with the impurity ions Ip, the polysilicon may be subjected to activation by annealing.

Thereafter, a silicon oxide film is formed (to a thickness of approximately 300 nm) by, for example, plasma CVD on the surface of the substrate on which the first conductive region 12aa, the second conductive region 12ab, the first channel region 12ac, the third conductive region 13aa, the fourth conductive region 13ab, the second channel region 13ac, the first conductive layer 12b, and the second conductive layer 12c have been formed, to form the first interlayer insulating film 16.

Subsequently, a metal film such as a molybdenum film is formed (to a thickness of approximately 200 nm) by, for example, sputtering on the surface of the substrate on which the first interlayer insulating film 16 has been formed. Thereafter, the metal film is patterned to form, for example, the second initialization power supply lines 17i.

Furthermore, the second interlayer insulating film 18 is formed by forming a silicon nitride film (to a thickness of approximately 150 nm) by, for example, plasma CVD on the surface of the substrate on which, for example, the second initialization power supply lines 17i has been formed. Thereafter, a stack of the gate insulating film 14, the first interlayer insulating film 16, and the second interlayer insulating film 18 is patterned by sequentially performing dry etching using, for example, CF₄and SF₆and wet etching using, for example, hydrofluoric acid, to form, for example, the first contact hole Ha, the second contact hole Hb, the third contact hole Hc, and the fourth contact hole Hd, as shown in FIG. 16 (interlayer insulating film formation step).

Thereafter, for example, a titanium film (having a thickness of approximately 50 nm), an aluminum film (having a thickness of approximately 400 nm), and a titanium film (having a thickness of approximately 50 nm) are sequentially formed by, for example, sputtering on the surface of the substrate on which, for example, the first contact hole Ha, the second contact hole Hb, the third contact hole Hc, and the fourth contact hole Hd have been formed. Thereafter, the metal stack-layer film is patterned to form the first terminal electrode 19a, the second terminal electrode 19b, the third terminal electrode 19c, and the fourth terminal electrode 19d as shown in FIG. 17 (terminal electrode formation step). Note that the source lines 19f and the power supply lines 19g are also formed in forming the first terminal electrode 19a, the second terminal electrode 19b, the third terminal electrode 19c, and the fourth terminal electrode 19d.

Finally, a polyimide-based photosensitive resin film (having a thickness of approximately 2 μm) is applied by, for example, spin-coating or slit-coating on the surface of the substrate on which, for example, the first terminal electrode 19a, the second terminal electrode 19b, the third terminal electrode 19c, and the fourth terminal electrode 19d have been formed.

Thereafter, the coating film is pre-baking, exposed to light, developed, and post-baked to form the planarization film 20, as shown in FIG. 18 (planarization film formation step).

The TFT layer 30a is formed as described above.

Organic EL Element Layer Formation Step (Light-emitting Element Layer Formation Step)

The first electrode 31, the edge cover 32, the organic EL layer 33 (the hole injection layer 1, the hole transport layer 2, the light-emitting layer 3, the electron transport layer 4, and the electron injection layer 5), and the second electrode 34 are formed by a well-known method on the planarization film 20 of the TFT layer 30a formed in the aforementioned TFT layer formation step, to form the organic EL element layer 40.

Sealing Film Formation Step

First, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a mask on the surface of the substrate on which the organic EL element layer 40 has been formed in the aforementioned organic EL element layer formation step, to form the first inorganic sealing film 41.

Subsequently, a film is formed of an organic resin material such as an acrylic resin by, for example, inkjet printing technology on the surface of the substrate on which the first inorganic sealing film 41 has been formed, to form the organic sealing film 42.

Thereafter, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a mask on the surface of the substrate on which the organic sealing film 42 has been formed, to form the second inorganic sealing film 43 to form the sealing film 45.

Finally, a protection sheet (not shown) is attached to the surface of the substrate on which the sealing film 45 has been formed, thereafter a laser beam is projected from the glass substrate side of the resin substrate layer 10, to lift off the glass substrate from the bottom face of the resin substrate layer 10, and a protection sheet (not shown) is attached to the bottom face of the resin substrate layer 10 from which the glass substrate has been lifted off.

The organic EL display device 50 in accordance with the present embodiment is manufactured as described above.

As described above, according to the organic EL display device 50 in accordance with the present embodiment and the method of manufacturing the organic EL display device 50, the first semiconductor layer 12a, the first polysilicon layer 12bp, and the second polysilicon layer 12cp are formed of a polysilicon in the first semiconductor layer formation step, and the second semiconductor layer 13a is formed of an oxide semiconductor on the first polysilicon layer 12bpand the second polysilicon layer 12cp in the second semiconductor layer formation step.

Thereafter, in the ion doping step, the first conductive region 12aa and the second conductive region 12ab, both of which are of a n′ type, are formed in the first semiconductor layer 12a by doping the first semiconductor layer 12a, the first polysilicon layer 12bp, and the second polysilicon layer 12cp with the impurity ions Ip, the first conductive layer 12b and the second conductive layer 12c, both of which are of a n⁺type, are formed by modifying the first polysilicon layer 12bp and the second polysilicon layer 12cp into a conductor, and the third conductive region 13aa and the fourth conductive region 13ab are formed in the second semiconductor layer 13a by doping the second semiconductor layer 13a with the impurity ions Ip. Furthermore, in the interlayer insulating film formation step, the first contact hole Ha, the second contact hole Hb, the third contact hole Hc, and the fourth contact hole Hd are formed through a stack of the gate insulating film 14, the first interlayer insulating film 16, and the second interlayer insulating film 18, reaching the first conductive region 12aa, the second conductive region 12ab, the first conductive layer 12b, and the second conductive layer 12c. Here, the third contact hole Hc and the fourth contact hole Hd are formed so as to reach the first conductive layer 12b and the second conductive layer 12c, which are made of a polysilicon that is poorly dissolvable in hydrofluoric acid and which are modified into a conductor, not to reach the third conductive region 13aa and the fourth conductive region 13ab, which are made of an oxide semiconductor that is readily dissolvable in hydrofluoric acid. Therefore, the first contact hole Ha, the second contact hole Hb, the third contact hole Hc, and the fourth contact hole Hd can be collectively formed. In addition, in doping the first semiconductor layer 12a and the second semiconductor layer 13a with the impurity ions Ip using the first gate electrode 15a and the second gate electrode 15b as a mask in the ion doping step, only the gate insulating film 14 is disposed between the first semiconductor layer 12a and the first gate electrode 15a (serving as a mask for the first semiconductor layer 12a) and between the second semiconductor layer 13a and the second gate electrode 15b (serving as a mask for the second semiconductor layer 13a). Therefore, the first semiconductor layer 12a and the second semiconductor layer 13a can be simultaneously doped with the impurity ions Ip. Therefore, it is possible to collectively form the first contact hole Ha and the second contact hole Hb for electrically connecting to the first semiconductor layer 12a of a polysilicon and to form the third contact hole Hc and the fourth contact hole Hd for electrically connecting to the semiconductor layer 13a of an oxide semiconductor and also to simultaneously perform ion doping on the first semiconductor layer 12a and the second semiconductor layer 13a.

Second Embodiment

FIG. 19 illustrates a second embodiment of a display device and a method of manufacturing a display device, both in accordance with the disclosure. Here, FIG. 19 is a cross-sectional view of a display area D of a TFT layer 30b that is a part of an organic EL display device in accordance with the present embodiment. Note that members of this and subsequent embodiments that are the same as those shown in FIGS. 1 to 18 are indicated by the same reference signs or numerals, and detailed description thereof is omitted.

The first embodiment above discusses an example where the organic EL display device 50 includes the TFT layer 30a including the gate insulating film 14 provided as a common layer. Meanwhile, the present embodiment discusses an example where an organic EL display device includes the TFT layer 30b including insular, first gate insulating films 14a and insular, second gate insulating films 14b.

Similarly to the organic EL display device 50 in accordance with the first embodiment above, the organic EL display device in accordance with the present embodiment includes, for example, the rectangular display area D and the frame area F surrounding the display area D.

The organic EL display device in accordance with the present embodiment includes: a resin substrate layer 10; the TFT layer 30b on the resin substrate layer 10; an organic EL element layer 40 on the TFT layer 30b; and a sealing film 45 covering the organic EL element layer 40.

Referring to FIG. 19, similarly to the TFT layer 30a in accordance with the first embodiment above, the TFT layer 30b includes: a base coat film 11 on the resin substrate layer 10; four first TFTs 9A, three second TFTs 9B, and one capacitor 9h (see FIG. 4), all on the base coat film 11, in each subpixel P; and a planarization film 20 on the first TFTs 9A, the second TFTs 9B, and the capacitors 9h. Here, similarly to the TFT layer 30a in accordance with the first embodiment above, the TFT layer 30b includes: a plurality of gate lines 15g; a plurality of light-emission control lines 15e; a plurality of second initialization power supply lines 17i; a plurality of source lines 19f; and a plurality of power supply lines 19g.

Referring to FIG. 19, each first TFT 9A includes: a first semiconductor layer 12a on the base coat film 11; one of the insular, first gate insulating films 14a on the first channel region 12ac of the first semiconductor layer 12a; a first gate electrode 15a on the first gate insulating film 14a; a first interlayer insulating film 16 and a second interlayer insulating film 18 sequentially provided so as to cover the first gate electrode 15a; and a first terminal electrode 19a and a second terminal electrode 19b on the second interlayer insulating film 18 at a distance from each other. Here, referring to FIG. 19, the first terminal electrode 19a and the second terminal electrode 19b are electrically connected respectively to the first conductive region 12aa and the second conductive region 12ab of the first semiconductor layer 12a via a first contact hole Ha and a second contact hole Hb formed through a stack of the first interlayer insulating film 16 and the second interlayer insulating film 18. Note that referring to FIG. 19, the first gate insulating film 14a is provided insularly so as to overlap the first gate electrode 15a.

Referring to FIG. 19, each second TFT 9B includes: a second semiconductor layer 13a on the base coat film 11; a first conductive layer 12b and a second conductive layer 12c on the resin substrate layer 10 side of the third conductive region 13aa and the fourth conductive region 13ab of the second semiconductor layer 13a respectively; the insular, second gate insulating film 14b on the second channel region 13ac of the second semiconductor layer 13a; a second gate electrode 15b on the second gate insulating film 14b; the first interlayer insulating film 16 and the second interlayer insulating film 18 sequentially provided so as to cover the second gate electrode 15b; and the third terminal electrode 19c and the fourth terminal electrode 19d on the second interlayer insulating film 18 at a distance from each other. Here, referring to FIG. 19, the third terminal electrode 19c and the fourth terminal electrode 19d are electrically connected respectively to the first conductive layer 12b and the second conductive layer 12c via a third contact hole Hc and a fourth contact hole Hd formed through the stack of the first interlayer insulating film 16 and the second interlayer insulating film 18. Note that referring to FIG. 19, the second gate insulating film 14b is provided insularly so as to overlap the second gate electrode 15b and made of the same material, and provided in the same layer, as the first gate insulating film 14a.

Similarly to the organic EL display device 50 in accordance with the first embodiment above, in each subpixel P in the organic EL display device in accordance with the present embodiment, the organic EL element 35 emits light with a luminance that is in accordance with the drive current to produce an image display.

The organic EL display device in accordance with the present embodiment can be manufactured by also patterning the gate insulating films 14 underlying the first gate electrode 15a and the second gate electrode 15b simultaneously with the formation of the first gate electrode 15a and the second gate electrode 15b in the gate electrode formation step in the TFT layer formation step in the method of manufacturing the organic EL display device 50 in accordance with the first embodiment above.

As described above, according to the organic EL display device in accordance with the present embodiment and the method of manufacturing the organic EL display device, the first semiconductor layer 12a, the first polysilicon layer 12bp, and the second polysilicon layer 12cp are formed of a polysilicon in the first semiconductor layer formation step, and the second semiconductor layer 13a is formed of an oxide semiconductor on the first polysilicon layer 12bp and the second polysilicon layer 12cp in the second semiconductor layer formation step. Thereafter, in the ion doping step, the first conductive region 12aa and the second conductive region 12ab, both of which are of a n⁺type, are formed in the first semiconductor layer 12a by doping the first semiconductor layer 12a, the first polysilicon layer 12bp, and the second polysilicon layer 12cp with the impurity ions Ip, the first conductive layer 12b and the second conductive layer 12c are formed by modifying the first polysilicon layer 12bp and the second polysilicon layer 12cp into a conductor, and the third conductive region 13aa and the fourth conductive region 13ab are formed in the second semiconductor layer 13a by doping the second semiconductor layer 13a with the impurity ions Ip. Furthermore, in the interlayer insulating film formation step, the first contact hole Ha, the second contact hole Hb, the third contact hole Hc, and the fourth contact hole Hd are formed through a stack of the first interlayer insulating film 16 and the second interlayer insulating film 18, reaching the first conductive region 12aa, the second conductive region 12ab, the first conductive layer 12b, and the second conductive layer 12c. Here, the third contact hole Hc and the fourth contact hole Hd are formed so as to reach the first conductive layer 12b and the second conductive layer 12c, which are made of a polysilicon that is poorly dissolvable in hydrofluoric acid and which are modified into a conductor, not to reach the third conductive region 13aa and the fourth conductive region 13ab, which are made of an oxide semiconductor that is readily dissolvable in hydrofluoric acid. Therefore, the first contact hole Ha, the second contact hole Hb, the third contact hole Hc, and the fourth contact hole Hd can be collectively formed. In addition, in doping the first semiconductor layer 12a and the second semiconductor layer 13a with the impurity ions Ip using the first gate electrode 15a and the second gate electrode 15b as a mask in the ion doping step, only the first gate insulating film 14a and the second gate insulating film 14b are disposed between the first semiconductor layer 12a and the first gate electrode 15a (serving as a mask for the first semiconductor layer 12a) and between the second semiconductor layer 13a and the second gate electrode 15b (serving as a mask for the second gate electrode 15b). Therefore, the first semiconductor layer 12a and the second semiconductor layer 13a can be simultaneously doped with the impurity ions Ip. Therefore, it is possible to collectively form the first contact hole Ha and the second contact hole Hb for electrically connecting to the first semiconductor layer 12a of a polysilicon and to form the third contact hole Hc and the fourth contact hole Hd for electrically connecting to the semiconductor layer 13a of an oxide semiconductor and also to simultaneously perform ion doping on the first semiconductor layer 12a and the second semiconductor layer 13a.

In addition, according to the organic EL display device in accordance with the present embodiment and the method of manufacturing the organic EL display device, doping the first semiconductor layer 12a and the second semiconductor layer 13a with the impurity ions Ip in the ion doping step, since the regions that will become the first conductive region 12aa, the second conductive region 12ab, the first conductive layer 12b, the second conductive layer 12c, the third conductive region 13aa, and the fourth conductive region 13ab are exposed from the first gate insulating film 14a and the second gate insulating film 14b, the doping with the impurity ions Ip can be efficiently done, which enables restraining manufacturing cost.

Third Embodiment

FIGS. 20 to 23 illustrate a third embodiment of a display device and a method of manufacturing a display device, both in accordance with the disclosure. FIG. 20 is a first cross-sectional view of a part of the manufacture of the organic EL display device in accordance with the present embodiment. FIG. 21 is a second cross-sectional view that follows FIG. 20. In addition, FIG. 22 is a first cross-sectional view of a part of the manufacture of a variation example of the organic EL display device in accordance with the present embodiment. FIG. 23 is a second cross-sectional view that follows FIG. 22.

The first embodiment above discusses an example where the method of manufacturing the organic EL display device involves doping with phosphorus as impurity ions. Meanwhile, the present embodiment discusses an example where the method of manufacturing the organic EL display device involves doping with phosphorus and boron as impurity ions.

Specifically, in the ion doping step in the TFT layer formation step described in the first embodiment above, first of all, a resist Ra is formed so as to cover the second gate electrode 15b, and thereafter doping with impurity ions Ib such as boron is performed using the first gate electrode 15a as a mask, to form the first conductive region 12aa, the second conductive region 12ab, and the first channel region 12ac in the first semiconductor layer 12a as shown in FIG. 20. Subsequently, the resist Ra is removed, and a resist Rb is formed so as to cover the first gate electrode 15a as shown in FIG. 21. Thereafter, the third conductive region 13aa, the fourth conductive region 13ab, and the second channel region 13ac are formed in the second semiconductor layer 13a by doping with the impurity ions Ip such as phosphorus using the second gate electrode 15b as a mask, and the first conductive layer 12b and the second conductive layer 12c are formed by modifying the first polysilicon layer 12bp and the second polysilicon layer 12cp into a conductor. Hence, the first TFTs 9A, which are of a P type, and the seconds TFT 9B, which are of a N type, can be formed on the same substrate.

In addition, other than the first semiconductor layer 12a and the second semiconductor layer 13a, a third semiconductor 12d (see FIG. 22) and a third gate electrode 15c that corresponds to the third semiconductor 12d (see FIG. 22) are formed in advance. Then, in the ion doping step in the TFT layer formation step above, first of all, the resist Ra is formed so as to cover the second gate electrode 15b and the third gate electrode 15c, and thereafter the first conductive region 12aa, the second conductive region 12ab, and the first channel region 12ac are formed in the first semiconductor layer 12a by doping with the impurity ions Ib such as boron using the first gate electrode 15a as a mask, as shown in FIG. 22. Subsequently, the resist Ra is removed, and the resist Rb is formed so as to cover the first gate electrode 15a as shown in FIG. 23. Thereafter, by doping with the impurity ions Ip such as phosphorus using the second gate electrode 15b and the third gate electrode 15c as a mask, the third conductive region 13aa, the fourth conductive region 13ab, and the second channel region 13ac are formed in the second semiconductor layer 13a, and a conductive region 12da, a conductive region 12db, and a channel region 12dc are formed in the third semiconductor 12d, and the first conductive layer 12b and the second conductive layer 12c are formed by modifying the first polysilicon layer 12bp and the second polysilicon layer 12cp into a conductor. Hence, first TFTs 9Aa, which are of a P type, first TFTs 9Ab, which are of a N type, and the second TFTs 9B, which are of a N type, can be formed on the same substrate, and a high performance drive circuit can be formed in the frame area F by combining the P-type, first TFT 9Aa and the N-type, first TFT 9Ab to construct a CMOS (complementary metal oxide semiconductor).

In addition, according to the organic EL display device in accordance with the present embodiment and the method of manufacturing the organic EL display device, when the P-type, first TFT 9Aa and the N-type, first TFT 9Ab are formed as the first TFT, a high performance drive circuit can be formed in the frame area F by combining the first TFT 9Aa and the first TFT 9Ab so as to construct a CMOS.

Other Embodiments

The foregoing embodiments have discussed examples where the organic EL layer has a 5-layer structure that includes a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. Alternatively, the organic EL layer may have, for example, a 3-layer structure that includes a hole injection and transport layer, a light-emitting layer, and an electron transport and injection layer.

In addition, the foregoing embodiments have discussed examples where the organic EL display device includes a first electrode as an anode and a second electrode as a cathode. The disclosure is equally applicable to organic EL display devices in which the layered structure of the organic EL layer is reversed, to include a first electrode as a cathode and a second electrode as an anode.

In addition, the forgoing embodiments have discussed organic EL display devices as an example of the display device. The disclosure is equally applicable to display devices including liquid crystal display devices that operate by an active matrix driving scheme.

In addition, the foregoing embodiments have discussed organic EL display devices as an example of the display device. The disclosure is equally applicable to display devices including a plurality of current-driven light-emitting elements, for example, applicable to display devices including QLEDs (quantum-dot light-emitting diodes) which are light-emitting elements using a quantum-dot-containing layer.

INDUSTRIAL APPLICABILITY

As described above, the disclosure is useful in flexible display devices.

DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE

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