Patent Grant
11114008
The present invention relates to an electronic device and a method, and in particular, the present invention relates to a display device and operating method thereof.
With the rapid development of electronic technology, display devices such as mobile phones or computers have been widely used in people's lives.
In general, a display device can include a gate driver, a source driver, and a pixel circuit array. The gate driver can sequentially provide a plurality of gate signals to the pixel circuit, in order to turn on the data switch of the pixel circuit column by column. The source driver can provide a plurality of data voltages to the pixel circuit in which that the data switch is turning on, in order to make the pixel circuit conducting display operations according to the data voltage.
An embodiment of the present invention relates to a display device. According to an embodiment of the present invention, a display device comprises: a plurality of data lines, configured to receive a plurality of data voltages from a source driver, wherein the source driver is disposed in a non-display area of the display device; and a first multiplex switch disposed in a display area of the display device and configured in response to a first multiplex signal, to provide a first data voltage of the data voltages to a first data line of the data lines.
Another embodiment of the present invention is related to an operating method of display device. According to an embodiment of the present invention, the operating method of a display device comprises: providing a plurality of data voltages from a source driver, wherein the source driver is disposed in a non-display area of the display device; and through a first multiplex switch disposed in a display area of the display device, providing a first data voltage of the data voltages to a first data line in response to a first multiplex signal.
Another embodiment of the present invention relates to a display device. According to an embodiment of the present invention, the display device comprises: a plurality of data lines, disposed substantially parallel to each other; a plurality of gate lines disposed substantially parallel to each other; a plurality of data switches, respectively electrically connected between the data lines and a plurality of pixel electrodes, and configured to be turned on according to a plurality of gate signals provided by the gate lines; and a plurality of multiplex switches, disposed in a display area of the display device for respectively providing a plurality of data voltages to different ones of the data lines.
By applying the above embodiment, the multiplex switch can be disposed in the display area to achieve the effect of reducing the frame
In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly and easily understood, the descriptions of the attached figures are as follows.
The spirit of the present invention will be clearly described in the following schematic and detailed description. Any person with ordinary skills in the art who understands the embodiment of the disclosed content can change and modify the technology taught by the present invention, which is not separated from the spirit and scope of the present invention.
Regarding the “first”, “second”, . . . , etc., as used herein, it does not specifically refer to the meaning of order or sequence, nor is it used to define the invention, but only to distinguish elements or operations described in the same technical terms.
As for the “electrical connection” used herein, it can refer to two or more elements making physical or electrical contact with each other directly or indirectly, and “electrical connection” can also refer to two or more elements operating or acting with each other.
The terms “including”, “comprising”, “having”, “containing”, etc., as used herein are all open terms, which is meaning to include but not to limit.
About the “and/or”, as used herein, it is meant to include any or all combinations of the recited things.
About the “substantially”, “approximately”, and so on, as used herein, are used to modify the quantity or error of any slight variation, but such slight variations or errors do not alter the nature.
Unless otherwise specified, the terms used in this paper usually have the common meaning of each word in the art, in the present invention content and the special content. Some terms used to describe the present invention will be discussed below or elsewhere in this specification to provide additional guidance for those skilled in the art on the description of the present invention.
In the present embodiment, the gate driver 110 can generate a plurality of gate signals respectively and provide them to the data switches (e.g., the data switches T11-T36 in
Referring to
In one embodiment, the display device 100 further multiple data lines DR, DG, DB, and a data transmission line DTR (also referred to as a data line DTR). In an embodiment, the data lines DR, DG, DB, and the data transmission line DTR are disposed substantially parallel to each other. In an embodiment, the data transmission line DTR may be one of the aforementioned data lines D(1), . . . , D(M). In another embodiment, the data transmission line DTR is electrically connected to one of the aforementioned data lines D(1), . . . , D(M).
In one embodiment, the display device 100 further includes a multiplex signal line SWR, SWG, and SWB. In one embodiment, the multiplex signal lines SWR, SWG, SWB are substantially parallel to the gate lines G(1), . . . , G(N). In an embodiment, the multiplex signal lines SWR, SWG, and SWB can be disposed between the gate lines G(1), . . . , G(N). From another perspective, the multiplex signal lines SWR, SWG, and SWB can be interleaving disposed with the gate lines G(1), . . . , G(N). In one embodiment, the multiplex signal lines SWR, SWG, SWB can receive multiplex signals that came from a multiplex signal generator (not shown). In one embodiment, the multiplexed signal generator, for example, can be implemented by a circuit or a timing controller, but not limited thereto.
In one embodiment, the multiplex switch M1 is electrically connected between the data transmission line DTR and the data line DR, and the control end of the multiplex switch M1 is electrically connected to the multiplex signal line SWR. The multiplex switch M1 is turned on according to the multiplex signal from the multiplex signal line SWR to provide the data voltage from the data transmission line DTR to the data line DR.
In one embodiment, the multiplex switch M2 is electrically connected between the data transmission line DTR and the data line DG, and the control end of the multiplex switch M2 is electrically connected to the multiplex signal line SWG. The multiplex switch M2 is turned on according to the multiplex signal from the multiplex signal line SWG to provide the data voltage from the data transmission line DTR to the data line DG.
In one embodiment, the multiplex switch M3 is electrically connected between the data transmission line DTR and the data line DB, and the control end of the multiplex switch M3 is electrically connected to the multiplex signal line SWB. The multiplex switch M3 is turned on according to the multiplex signal from the multiplex signal line SWB to provide the data voltage from the data transmission line DTR to the data line DB.
In one embodiment, the multiplex switches M1-M3 are alternatively turned on to provide data voltages that came from the data transmission line DTR to the data lines DR, DG, DB, respectively.
In one embodiment, the data switches T11-T16 are electrically connected between the data lines DR and the pixel electrode PXD, and the control end of the data switches T11-T16 is respectively electrically connected to the gate line G(1)-G(6). The data switches T11-T16 are respectively turned on according to the gate signals from the gate lines G(1)-G(6) to respectively provide the data voltages on the data lines DR to the corresponding pixel electrodes PXD.
In one embodiment, the data switches T21-T26 are electrically connected between the data line DG and the pixel electrode PXD, and the control end of the data switches T21-T26 is electrically connected to the gate line G(1)-G(6). The data switches T21-T26 are respectively turned on according to the gate signals from the gate lines G(1)-G(6) to respectively provide the data voltages on the data lines DG to the corresponding pixel electrodes PXD.
In one embodiment, the data switches T31-T36 are electrically connected between the data line DB and the pixel electrode PXD, and the control end of the data switches T31-T36 is electrically connected to the gate line G(1)-G(6). The data switches T31-T36 are respectively turned on according to the gate signals from the gate lines G(1)-G(6) to respectively provide the data voltages on the data lines DB to the corresponding pixel electrodes PXD.
With the above setting, the multiplex switches M1-M3 can be disposed in the display area DSA, and the multiplex switch can be prevented from being disposed in the non-display area NDA, thereby achieving the effect of reducing the frame.
In one embodiment, the multiplex switches M1-M3 are located substantially between the data switches. For example, the multiplex switch M1 is located substantially between the data switches T11-T23, and the multiplex switch M2 is located substantially between the data switches T13-T25.
In one embodiment, each multiplex switch M1-M3 is located substantially between two adjacent data lines DR, DG, DB. For example, the multiplex switch M1 is located substantially between the data lines DR and DG, the multiplex switch M2 is located substantially between the data lines DR, DG, and the multiplex switch M3 is located substantially between the data lines DG and DB.
In one embodiment, each multiplex switch M1-M3 is located substantially between two adjacent gate lines. For example, the multiplex switch M1 closer to the gate line G(1) is located substantially between the gate lines G(1)-G(2), and the multiplex switch M2 closer to the gate line G(5) is located substantially between the gate lines G(4)-G(5).
In one embodiment, each multiplex switch M1-M3 is substantially surrounded by two adjacent gate lines and two adjacent data lines. For example, the multiplex switch M1 closer to the gate line G(1) is substantially surrounded by the gate lines G(1)-G(2) and the data lines DR, DG, and the multiplex switch M2 closer to the gate line G(5) is substantially surrounded by the gate lines G(4)-G(5) and the data lines DR, DG.
It should be noted that the setting position of the multiplex switch M1-M3 can be adjusted according to actual needs, and are not limited to the above implementation.
The term “between” or “surrounded by” in this context can be understood to mean that the orthographic projection of the component on the substrate SBT is substantially located between the orthographic projection of the other component on the substrate SBT, or the orthographic projection of the component on the substrate SBT is substantially surrounded by the orthographic projection of other elements on the substrate SBT.
In one embodiment, multiple gate lines may be spaced between the multiplex signal lines SWR, SWG and SWB. In one embodiment, the multiplex signal lines SWR, SWG and SWB are approximately evenly arranged in the display area DSA. For example, when the resolution of the display device 100 is 1920*1080, the multiplex signal lines SWR, SWG and SWB can be respectively disposed approximately at the positions of the first gate line, the 361st gate line, and 721st gate line counting from the top.
By evenly distributing the positions of the multiplex signal lines SWR, SWG, and SWB, the problem of uneven aperture ratio can be avoided.
The details in the embodiment of the present invention will be further described below in combination with
In the period TG1, the source driver 120 corresponding to the drive signals SROUT, sequentially provides data voltage DATAR, DATAG, DATAB to the data transmission line DTR. Besides, in the period TG1, the gate driver 110 provides the gate signal with a first voltage level (e.g., high voltage level) to the gate line G (1).
Further, in the period T1, the source driver 120 provides the data voltage DATAR to the data transmission line DTR. At this time, the multiplex switch M1 corresponding to the multiplex signal with the second voltage level (such as the high voltage level) (which may be the same or different from the first voltage level) on the multiplex signal line SWR is turned on to provide the data voltage DATAR on the transmission line DTR to the data line DR. At this time, the data switch T11 corresponding to the gate signal with the first voltage level on the gate line G(1) is turned on to provide the data voltage DATAR on the data line DR to the corresponding pixel electrode PXD.
On the other hand, in the period T1, the multiplex switches M2 and M3 corresponding to the multiplex signal with the third voltage level (such as the low voltage level) (below the second voltage level) on the multiplex signal lines SWG and SWB is turned off to avoid providing the data voltage DATAR on the data transmission line DTR to the data lines DG, DB.
In the period T2, the source driver 120 provides the data voltage DATAG to the data transmission line DTR instead. At this time, the multiplex switch M2 corresponding to the multiplex signal with the second voltage level on the multiplex signal line SWR is turned on to provide the data voltage DATAG on the data transmission line DTR to the data line DG. At this time, the data switch T21 corresponding to the gate signal with the first voltage level on the gate line G(1) is turned on to provide the data voltage DATAG on the data line DG to the corresponding pixel electrode PXD.
On the other hand, in the period T2, the multiplex switches M1 and M3 corresponding to the multiplex signal with the third voltage level on the multiplex signal lines SWR and SWB are turned off to avoid providing the data voltage DATAG on the data transmission line DTR to the data line DR, DB.
In the period T3, the source driver 120 provides the data voltage DATAB to the data transmission line DTR instead. At this time, the multiplex switch M3 corresponding to the multiplex signal with the second voltage level on the multiplex signal line SWR is turned on to provide the data voltage DATAB on the data transmission line DTR to the data line DB. At this time, the data switch T31 corresponding to the gate signal with the first voltage level on the gate line G(1) is turned on to provide the data voltage DATAB on the data line DB to the corresponding pixel electrode PXD.
On the other hand, in the period T3, the multiplex switches M1 and M2 corresponding to the multiplex signal with the third voltage level on the multiplex signal lines SWR and SWG are turned off to avoid providing the data voltage DATAB on the data transmission line DTR to the data line DR, DG.
By the above operation, the display device 100 can update the data voltage on the pixel electrode PXD by the multiplex switches M1-M3 provided in the display area DSA.
The details in another embodiment of the present invention are provided below in combination with
In one embodiment of the present invention, the display device 100 not only comprises a gate driver 110, a source driver 120, and a substrate SBT, but also data switches T11-T36, multiplex switches M1a-M2a, and the pixel electrodes PXD (represented only by inverted triangle symbol). In one embodiment, the data switches T11-T36, the multiplex switches M1-M3, and the pixel electrodes PXD are all disposed in the display area DSA of the display device 100. It should be noted that although in this present invention is taken each two multiplex switches M1a-M2a as an example to explain, in different embodiments, the number of each multiplex switches M1a-M2a can be adjusted according to actual needs (such as one, three, or other numbers), and therefore are not limited to the described in the embodiment. In addition, although the multiplex switches M1a-M2a of two different setting modes is taken as an example to explain in the present invention, in different embodiments, the number of types of the multiplex switch can be adjusted according to actual conditions (for example, 3 types, 4 types, or other number types), and therefore are not limited to the described in the embodiment.
In one embodiment, the display device 100 further comprises multiple data lines DR, DGa, and DB. In one embodiment, the data lines DR, DGa, and DB are disposed substantially parallel to each other. In one embodiment, the data line DGa may be one of the aforementioned data lines D(1), . . . , D(M). In another embodiment, the data line DGa is electrically connected to one of the aforementioned data lines D(1), . . . , D(M).
In one embodiment, the display device 100 further comprises multiplex signal lines SWRa, SWBa. In one embodiment, the multiplex signal lines SWRa, SWBa are substantially parallel to the gate lines G(1), . . . , G(N). In one embodiment, the multiplex signal lines SWRa, SWBa may be disposed between the gate lines G(1), . . . , G(N). From another perspective, the multiplex signal lines SWRa, SWBa can be interleaving disposed with the gate lines G(1), . . . , G(N). In one embodiment, the multiplex signal lines SWRa, SWBa can receive multiplex signals that came from a multiplex signal generator (not shown). In one embodiment, the multiplex signal generator, for example, can be implemented by a circuit or a timing controller, but not limited thereto.
In one embodiment, the multiplex switch M1a is electrically connected between the data line DGa and the data line DR, and the control end of the multiplex switch M1a is electrically connected to the multiplex signal line SWRa. The multiplex switch M1a is turned on according to the multiplex signal from the multiplex signal line SWRa to provide the data voltage from the data line DGa to the data line DR.
In an embodiment, the multiplex switch M2a is electrically connected between the data line DGa and the data line DB, and the control end of the multiplex switch M2a is electrically connected to the multiplex signal line SWBa. The multiplex switch M2a is turned on according to the multiplex signal from the multiplex signal line SWBa to provide the data voltage from the data line DGa to the data line DB.
In one embodiment, the multiplex switches M1a, M2a are alternatively turned on to provide data voltages that came from the data line DGa to the data lines DR, DB, respectively.
With the above setting, the multiplex switches M1a, M2a can be disposed in the display area DSA, and the multiplex switch can be prevented from being disposed in the non-display area NDA, thereby achieving the effect of reducing the frame.
In one embodiment, the multiplex switches M1a, M2a are located substantially between the data switch. For example, the multiplex switch M1a is located substantially between the data switches T11-T23, and the multiplex switch M2a is located substantially between the data switches T33-T35.
In one embodiment, each multiplex switch M1a, M2a is located substantially between two adjacent data lines DR, DGa, DB. For example, the multiplex switch M1a is located substantially between the data lines DR and DGa, and the multiplex switch M2a is located substantially between the data lines DGa and DB.
In one embodiment, each multiplex switch M1a, M2a is located substantially between two adjacent gate lines. For example, the multiplex switch M1a closer to the gate line G(1) is located substantially between the gate lines G(1)-G(2), and the multiplex switch M2a closer to the gate line G(5) is located substantially between the gate lines G(4)-G(5).
In one embodiment, each multiplex switches Mia, M2a is substantially surrounded by two adjacent gate lines and two adjacent data lines. For example, the multiplex switch M1a closer to the gate line G(1) is substantially surrounded by the gate lines G(1)-G(2) and the data lines DR, DGa, and the multiplex switch M2a closer to the gate line G(5) is substantially surrounded by the gate lines G(4)-G(5) and the data lines DR, DGa.
It should be noted that the setting positions of the multiplex switch M1a and M2a can be adjusted according to actual needs, and are not limited to the above implementation.
In one embodiment, multiple gate lines may be spaced between the multiplex signal lines SWRa and SWBb. In one embodiment, the multiplex signal lines SWRa and SWBa are substantially evenly disposed in the display area DSA. For example, when the resolution of the display device 100 is 1920*1080, the multiplex signal lines SWRa, SWBa can be respectively disposed substantially at the position of the first gate line and the 541st gate line counting from the top.
By evenly distributing the positions of the multiplex signal lines SWRa and SWBa, the problem of uneven aperture ratio can be avoided.
The details in the embodiment of the present invention will be further described below in combination with
In the TG1 period, the source driver 120 corresponding to the drive signals SROUT, sequentially provides data voltage DATAR, DATAG, DATAB to the data line DGa. Besides, in the TG1 period, the gate driver 110 provides the gate signal with a first voltage level (e.g., high voltage level) to the gate line G (1).
Further, in the period T1, the source driver 120 provides the data voltage DATAR to the data line DGa. At this time, the multiplex switch M1a corresponding to the multiplex signal with the second voltage level (such as the high voltage level) (which may be the same or different from the first voltage level) on the multiplex signal line SWRa is turned on to provide the data voltage DATAR on the data line DGa to the data line DR. At this time, the data switch T11 corresponding to the gate signal with the first voltage level on the gate line G(1) is turned on to provide the data voltage DATAR on the data line DR to the corresponding pixel electrode PXD.
On the other hand, in the period T1, the multiplex switch M2a corresponding to the multiplex signal with the third voltage level (such as the low voltage level) (below the second voltage level) on the multiplex signal line SWBa is turned off to avoid providing the data voltage DATAR on the data line DGa to the data line DB. In different embodiments, in the period T1, the multiplexer M2a can also be turned on.
In the period T2, the source driver 120 provides the data voltage DATAB to the data line DGa instead. At this time, the multiplex switch M2a corresponding to the multiplex signal with the second voltage level on the multiplex signal line SWBa is turned on to provide the data voltage DATAB on the data line DGa to the data line DB. At this time, the data switch T31 corresponding to the gate signal with the first voltage level on the gate line G(1) is turned on to provide the data voltage DATAB on the data line DB to the corresponding pixel electrode PXD.
On the other hand, in the period T2, the multiplex switch M1a corresponding to the multiplex signal with the third voltage level (such as the low voltage level) (below the second voltage level) on the multiplex signal line SWRa is turned off to avoid providing the data voltage DATAB on the data line DGa to the data line DR.
In the period T3, the source driver 120 provides the data voltage DATAG to the data line DGa instead. At this time, the data switch T21 corresponding gate signal with the first voltage level (1) on the gate line G(1) is turned on to provide the data voltage DATAG on the data line DGa to the corresponding pixel electrode PXD. It should be noted that since the data line DGa is used as the data transmission line in this embodiment, the multiplex signal line SWGa and the multiplex signal thereon can be omitted (indicated by a broken line in
In this time, the multiplex switches M1a and M2a corresponding to the multiplex signal with the third voltage level on the multiplex signal lines SWRa and SWGa are turned off to avoid providing the data voltage DATAG on the data line DGa to the data line DR.
By the above operation, the display device 100 can update the data voltage on the pixel electrode PXD by the multiplex switches M1a-M2a provided in the display area DSA.
In addition, it should be understood that the operation sequence of the operation method 200 mentioned in the present embodiment can be adjusted according to actual needs, except the sequence is specially stated, and can even be performed simultaneously or partially simultaneously.
Moreover, such operations may also be adaptively added, replaced, and/or omitted in various embodiments.
In the present embodiment, the operation method 200 comprises the following operations.
In operation S1, the display device 100 is configured to provide a plurality of data voltages from the source driver 120, wherein the source driver 120 is disposed in the non-display area NDA of the display device 100.
In operation S2, the display device 100 is configured to provide the first data voltage in the previous data voltages to the data line DR through the first multiplex switch M1 disposed in the display area DSA corresponding to the first multiplex signal.
The specific details of the above operations can be referred to the foregoing paragraphs, and thus will not be described herein.
Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any person who is skilled in the art can make various alterations and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the patent application claims attached hereto.
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| 108126280 | Jul 2019 | TW | national |
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| Number | Date | Country | |
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| 20210027687 A1 | Jan 2021 | US |
