Patent Grant
11776463
The present disclosure relates to display technology. More particularly, the present disclosure relates to a display device, a detecting method and a pixel driving circuit.
During manufacturing processes, pixel driving circuits on a substrate of a display device may suffer from metal residue and excessive etching which cause substrate abnormalities. Manufacturing processes of light emitting elements, such as micro light emitting diodes, are complicated, resulting in higher costs. In addition, currents in conventional pixel driving circuits may be affected by the characteristics of switches and/or resistance on current paths which cause non-uniform brightness of a display.
The present disclosure provides a display device. The display device includes pixel driving circuits coupled to each other in series. One of the pixel driving circuits includes a light emitting unit, first and second capacitors, and first and second switches. The light emitting unit emits light according to a voltage level of a first node. A first terminal of the first capacitor is coupled to the first node, and a second terminal of the first capacitor is coupled to a second node. A first terminal of the second capacitor is coupled to the second node, and a second terminal of the first capacitor is coupled to the light emitting unit. A first terminal of the first switch is coupled to the first node, and a second terminal of the first switch is coupled to the light emitting unit. The second switch is configured to be turned on before the first switch is turned on, and a first terminal of the second switch is coupled to the first node.
The present disclosure provides a detecting method. The detecting method includes: writing a first reference signal through a first switch into a control terminal of the first switch at a first node; after writing the first reference signal into the control terminal of the first switch, writing a data signal through a first capacitor into the first node; generating a first current flowing through the first switch; measuring the first current; and determining the first switch being normal, in response to a current level the first current corresponding to the data signal.
The present disclosure provides a pixel driving circuit. The pixel driving circuit includes a first switch, a second switch, a third switch, a fourth switch, a light emitting element and a data writing unit. The first switch is configured to generate a current according to a voltage level of a first node, a control terminal of the first switch is coupled to the first node. A first terminal of the second switch is coupled to the first node, a second terminal of the second switch is coupled to a first terminal of the first switch at a second node. A control terminal of the third switch is configured to receive a light emitting signal, a first terminal of the third switch is coupled to the second node. A control terminal of the fourth switch is configured to receive the light emitting signal, a first terminal of the third switch is coupled to a second terminal of the first switch at a third node. The light emitting element is configured to receive the current to emit light. The data writing unit is coupled to the first node and the third node, and is configured to adjust the voltage level of the first node.
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter.
Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The terms applied throughout the following descriptions and claims generally have their ordinary meanings clearly established in the art or in the specific context where each term is used. Those of ordinary skill in the art will appreciate that a component or process may be referred to by different names. Numerous different embodiments detailed in this specification are illustrative only, and in no way limit the scope and spirit of the disclosure or of any exemplified term.
It is worth noting that terms such as “first” and “second” used herein to describe various elements or processes aim to distinguish one element or process from another. However, the elements, processes and the sequences thereof should not be limited by these terms. For example, a first element could be termed as a second element, and a second element could be similarly termed as a first element without departing from the scope of the present disclosure.
In the following discussion and in the claims, the terms “comprising,” “including,” “containing,” “having,” “involving,” and the like are to be understood to be open-ended, that is, to be construed as including but not limited to. As used herein, instead of being mutually exclusive, the term “and/or” includes any of the associated listed items and all combinations of one or more of the associated listed items.
Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
As illustratively shown in
For example, a pixel driving circuit 200 shown in
In some embodiments, the scan signals S(n−1) and S(n) are transmitted to the pixel driving circuit 112 through the scan lines SL(n−1) and SL(n), respectively. The data signal DT is transmitted to the pixel driving circuit 112 through the data line DL(m). The light emitting signal EM is transmitted to the pixel driving circuit 112 through the light emitting line EL(n). The present disclosure is not limited to the embodiments described above. Various methods of transmitting the scan signals S(n−1), S(n), the data signal DT and the light emitting signal EM are contemplated as being within the scope of the present disclosure.
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In some embodiments, the pixel driving circuit 200 is an nth stage pixel driving circuit DV(n) of the pixel driving circuits in the display 100. Accordingly, the scan signal S(n) is an nth stage scan signal, the scan signal S(n−1) is an (n−1)th stage scan signal, and the scan signal S(n−2) is an (n−2)th stage scan signal. An (n−1)th stage pixel driving circuit DV(n−1) of the pixel driving circuits in the display 100 is configured to perform a data writing operation according to the scan signal S(n−1). An (n−2)th stage pixel driving circuit DV(n−1) in the display 100 is configured to perform a data writing operation according to the scan signal S(n−2).
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In different embodiments, the light emitting element L2 can be implemented by a micro light emitting diode (mLED) or another type of light emitting element. In different embodiments, the switches T21-T28 can be implemented by p-type metal-oxide-semiconductor field-effect transistors (PMOS), n-type metal-oxide-semiconductor field-effect transistors (NMOS), thin film transistors (TFT) or other types of switching elements.
As illustratively shown in
In some embodiments, the voltage level RF1 is an enable voltage level, such that the switch T22 is turned on according to the voltage level RF1 of the node N21. In some embodiments, the capacitor C21 is configured to store charges of the node N21 to maintain the voltage level of the node N21 after the switch T26 is turned off, such that the switch T22 continues to be turned on after the switch T26 is turned off, such as during the period P32.
In some embodiments, during the period P31, the voltage levels of the nodes N21, N22 and N23 are reset by the reference signals VRF1 and VRF2, such that the pixel driving circuit 200 is prepared to receive the data signal DT, and thus the period P31 is referred to as a reset period.
During the period P32, the scan signal S(n−1) and the control signal VC have the enable voltage level VGL, such that the switches T24 and T28 are turned on. The scan signal S(n−2) has a disable voltage level VGH, such that the switches T25 and T26 are turned off. The switch T28 provides the reference signal VRF2 to the node N23, such that the node N23 has the voltage level RF2. Due to the charges stored by the capacitor C21 during the period P31, the node N22 still has an enable voltage level during the period P32, and thus the switch T22 is turned on during the period P32. In some embodiments, the voltage level RF2 of the reference signal VRF2 is higher than the voltage level RF1 of the node N22, such that a current flows from the node N23, through the switches T22 and T24 in order, and to the node N22. At this time, the reference signal VRF2 is written into the node N22 through the switches T28, T22 and T24 in order, such that the voltage level of the node N22 is pulled to (RF2−|VTH|), in which the threshold voltage level VTH is the threshold voltage level of the switch T22. At this time, the voltage level of the node N21 is determined by the voltage level RF2 of the node N23, the voltage level (RF2−|VTH|) of the node N22, and the voltage level RF1 of the node N21 during the period P31.
As illustratively shown in
In some embodiments, during the period P32, the voltage level of the node N22 is adjusted to (RF2−|VTH|) in preparation of compensating for the threshold voltage level VTH of the switch T22 during a light emitting period, such as the period P34. Accordingly, the period P32 is referred to as a compensating period.
In some previous approaches, the voltage signal configured to perform compensation is affected by an internal resistance of the circuit element of the pixel driving circuit, and thus suffers from a voltage drop (IR drop), such that the voltage levels of the nodes in the pixel driving circuit are not stable.
Compared to the above approaches, in some embodiments of the present disclosure, the switch T28 transmits the reference signal VRF2 which is not affected by an IR drop to the node N23, and further stabilizes the voltage level of the node N21 by the capacitor C22.
During the period P33, the scan signal S(n) and the control signal VC have the enable voltage level VGL, such that the switches T21 and T28 are turned on. The scan signal S(n−1) has a disable voltage level VGH, such that the switch T24 is turned off. The switch T28 provides the reference signal VRF2 to the node N23, such that the node N23 has the voltage level RF2. At this time, the switch T21 writes the data signal DT having a voltage level VDT into the node N21, such that the voltage level of the node N21 is pulled to the voltage level VDT. The capacitor C21 writes the voltage level VDT of the node N21 into the node N22, to pull the voltage level of the node N22 to (RF2−|VTH|+(VDT−RF1)). At this time, a voltage level difference VGS between the nodes N22 and N23 is (VDT−RF1−|VTH|).
In some embodiments, during the period P33, the switch T21 and the capacitor C21 write the data signal DT into the node N22. Accordingly, the period P33 is referred to as a data writing period.
During the period P34, the light emitting signal EM has the enable voltage level VGL, such that the switches T23 and T27 are turned on. The scan signal S(n) and the control signal VC have a disable voltage level VGH, such that the switches T21 and T28 are turned off. At this time, the voltage signal VDD having a voltage level DD pulls the voltage level of the node N23 to (DD−VLED−VT27) through the light emitting element L2 and the switch T27. The voltage level differences VLED and VT27 correspond to the voltage level differences generated when the voltage signal VDD passes through the light emitting element L2 and the switch T27, respectively. Accordingly, the voltage level of the node N22 is pulled to (VDT−RF1−|VTH|+(DD−VLED−VT27)) by the capacitors C21 and C22. At this time, the voltage level difference VGS between the nodes N22 and N23 is (VDT−RF1−|VTH|).
During the period P34, the current I2 flows through the light emitting element L2, and the switches T27, T22 and T23 in order, such that the light emitting element L2 emits light according to the current level of the current I2. In some embodiments, the current level of the current I2 determines the brightness of the light emitting element L2.
In some embodiments, the current level of the current I2 is determined by the voltage level difference between a gate terminal and a source terminal of the switch T22, which is the voltage level difference VGS between the nodes N22 and N23. It may be determined utilizing formulas in electronics that the current I2 passing through the switch T22 has a current level K×(VGS+|VTH|){circumflex over ( )}2. During the period P34, the voltage level difference VGS is (VDT−RF1−|VTH|). K is a constant. As a result, the current level of the current I2 is independent from the threshold voltage level VTH, while it is dependent upon the voltage level DT of the data signal DT and the voltage level RF1 of the reference signal VRF1.
In some embodiments, during the period P34, the light emitting element L2 of the pixel driving circuit 200 emits light, and thus the period P34 is referred to as a light emitting period.
In some previous approaches, when the current passes through different paths in the display, different resistance values on the different paths cause different voltage drops. In addition, the threshold voltage levels of the switches also cause voltage drops. The current passing through the light emitting element is hard to control, such that the brightness of the display is not uniform.
Compared to the above approaches, in some embodiments of the present disclosure, the voltage levels VDT and RF1 are determined by users. As a result, the current I2 passing through the light emitting element L2 can be adjusted by the users, and is therefore prevented from being affected by current paths, or element features of the pixel driving circuit, such as the threshold voltage VTH of the switch T22.
In other embodiments, the pixel driving circuit 200 does not perform compensation of the threshold voltage level VTH of the switch T22. As described in relation to the operation of the pixel driving circuit 200 during the period P32, the voltage level RF2 of the reference signal VRF2 is higher than the voltage level RF1 of the node N22, such that the switches T22 and T24 perform the compensating operation by writing the threshold voltage level VTH into the node N22 with the reference signal VRF2. In contrast, when the user adjusts the voltage level of the reference signal VRF2 to be lower than or equal to the voltage level RF1, the threshold voltage level VTH is not written into the node N22, such that compensation of the threshold voltage level VTH of the switch T22 does not occur. As a result, during the following period P34, the voltage level difference VGS is (VDT−RF1), and the current level of the current I2 is K×(VDT−RF1+|VTH|){circumflex over ( )}2. In different embodiments, the compensating function of the pixel driving circuit 200 can be turned on or turned off by different voltage levels of the reference signal VRF2.
Referring to
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During the period P42, the voltage signal SLT, the scan signal S(n−1) and the control signal VC have the enable voltage level VGL, such that the switches T25, T24 and T28 are turned on. The scan signal S(n−2) has a disable voltage level VGH, such that the switch T26 is turned off. The switch T28 provides the reference signal VRF2 to the node N23, such that the node N23 has the voltage level RF2 and the node N22 has a voltage level (RF2−|VTH|). The switch T25 provides the reference signal VRF1 having a voltage level RF1 to the node N21, such that the node N21 has the voltage level RF1.
During the period P43, when the switch T21 writes the data signal DT into the node N21, the capacitor C21 writes a voltage level difference between the voltage levels RF1 and VDT into the node N22 for the data writing operation. At this time, the voltage level of the node N22 is (RF2−|VTH|+(VDT−RF1)).
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During the period P33, when the switch T51 writes the data signal DT into the node N51, the capacitor C51 writes the voltage level difference between the voltage levels RF1 and VDT into the node N52 to perform the data writing operation.
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During the period P72, the scan signal S(n−1) and the control signal VC have the enable voltage level VGL, such that the switches T64 and T68 are turned on. The scan signal S(n−2) has a disable voltage level VGH, such that the switches T65 and T66 are turned off. At this time, the reference signal VRF2 passes through the switches T68, T62 and T64 in order, and is written into the node N62.
During the period P73, the scan signal S(n) and the control signal VC have the enable voltage level VGL, such that the switches T61 and T68 are turned on. The scan signal S(n−1) has a disable voltage level VGH, such that the switch T64 is turned off. The switch T68 provides the reference signal VRF2 to the node N63, and the switch T61 and the capacitor C61 write the data signal DT into the node N62.
During the period P74, the light emitting signal EM and the control signal VC have the enable voltage level VGL, such that the switches T63 and T68 are turned on. At this time, a current I61 flows through the switches T68, T62 and T63 in order, to the node N67. In some embodiments, the user measures the current I61 at the node N67 to detect whether at least one of the switches T61-T68 operates normally.
For example, when each of the switches T61-T68 operates normally, the current level of the current I61 is proportional to the voltage level VDT of the data signal DT. In contrast, when the switch T61 cannot be turned on normally, the data signal DT cannot be written into the pixel driving circuit 600, such that the current level of the current I61 does not correspond to the voltage level VDT. As another example, when at least one of the switches T68, T62 and T63 cannot be turned on normally, the current I61 cannot flow to the node N67, such that the user cannot measure the current I61 at the node N67. In summary, the user can determine that the pixel driving circuit 600 is abnormal when the current I61 is abnormal. The present disclosure is not limited to the embodiments described above. In different embodiments, the user can measure different current flowing through the switches T61-T68 during different period(s) of the periods P71-P74, to detect whether the switches T61-T68 operate normally.
In some embodiments, after the user measures the current I61 to ensure that the pixel driving circuit 600 operates normally, the user couples the light emitting element L6 to the accommodating space SP6. In some embodiments, after the light emitting element L6 is coupled to the pixel driving circuit 600 at the accommodating space SP6, the user can further determine whether the light emitting element L6 operates normally.
For example, after the light emitting element L6 is coupled to the accommodating space SP6, the light emitting signal EM and the control signal VC have the enable voltage level VGL, such that the switches T68 and T67 are turned on. The light emitting element L6 receives the voltage signal VDD at the node N66, and the switch T68 receives the reference signal VRF2 at the node N68. At this time, a current I62 flows through the light emitting element L6, and the switches T67 and T68 in order. When the light emitting element L6, and the switches T67 and T68 operate normally, the brightness of the light emitting element L6 is proportional to a voltage level difference between the voltage signal VDD and the reference signal VRF2. In contrast, when at least one of the light emitting element L6, and the switches T67 and T68 is abnormal, the light emitting element L6 cannot emit light normally.
In some previous approaches, when a determination is made that the pixel driving circuit is abnormal, the light emitting element is already coupled to the pixel driving circuit. Accordingly, the manufacturing cost of the pixel driving circuit includes the manufacturing cost of the light emitting element.
Compared to the above approaches, in some embodiments of the present disclosure, a method of detecting the switches T61-T68 before the light emitting element L6 is coupled to the pixel driving circuit 600 is provided, as illustratively shown in
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Signal operations of the periods P91-P94 are similar to those of the periods P31-P34 shown in
Referring to
During the period P92, the scan signal S(n−1) and the control signal VC have the enable voltage level VGL, such that the switches T84 and T88 are turned on. The scan signal S(n−2) has a disable voltage level VGH, such that the switches T85 and T86 are turned off. At this time, the reference signal VRF2 passes through the switches T88, T82 and T84 in order, and is written into the node N82.
During the period P93, the scan signal S(n) and the control signal VC have the enable voltage level VGL, such that the switches T81 and T88 are turned on. The scan signal S(n−1) has a disable voltage level VGH, such that the switch T84 is turned off. At this time, the switch T88 provides the reference signal VRF2 to the node N83.
During the period P94, the light emitting signal EM and the voltage signal AT have the enable voltage level VGL, such that the switches T87, T83 and T89 are turned on. At this time, a current I81 flows through the switches T87, T82, T83 and T89 in order. In the embodiment corresponding to
In some embodiments, the node N89 is coupled to a data line (not shown) configured to transmit the data signal DT. In some embodiments, the user can measure a current level ILV of the current I81 from the data line, and determine whether the pixel driving circuit 800 is abnormal according to the current level ILV. For example, when at least one of the switches T87, T82, T83 and T89 cannot be turned on normally, the current I81 cannot be transmitted to the node N89, such that the current level ILV measured from the data line is abnormal.
Referring to
In some embodiments, the user can measure a current level ILV of the current I82 from the data line, and determine whether the pixel driving circuit 800 is abnormal according to the current level ILV. For example, when at least one of the switches T87, T82, T83, T89 and T81 cannot be turned on normally, the current I82 cannot be transmitted to the node N89, such that the current level ILV measured from the data line is abnormal.
In some embodiments, during the period P103, the current I82 further flows through the switches T87 and T88 in order, and flows to a node N88. The user can measure a current level ILV of the current I82 at the node N88, and determine whether the pixel driving circuit 800 is abnormal according to the current level ILV. For example, when at least one of the switches T87 and T88 cannot be turned on normally, the current I82 cannot be transmitted to the node N88, such that the current level ILV measured from the node N88 is abnormal.
In some embodiments, after the user measures the current I81 and/or I82 to ensure the pixel driving circuit 800 operates normally, the user couples the light emitting element L8 to the accommodating space SP8, such that a terminal of the light emitting element L8 is coupled to the node N84, and another terminal of the light emitting element L8 receives the voltage signal VSS. In some embodiments, after the light emitting element L8 is coupled to the pixel driving circuit 800, the pixel driving circuit 800 performs the light emitting operation according to the timing diagram shown in the
The detecting method and light emitting method described above are illustrated as examples, and other types of detecting methods and light emitting methods are within the contemplated scope of the present disclosure.
In summary, in the embodiments of the present disclosure, when the light emitting element L2 or L5 emits light, compensation of the threshold voltage level VTH of the switch T22 or T25 is performed, such that the value of the threshold voltage level VTH does not affect the brightness of the light emitting element L2 or L5. The operations of compensating the threshold voltage level VTH can be turned on or turned off by adjusting the voltage level of the reference signal VRF2. Furthermore, the reference signals VRF1 and VRF2 are not affected by the voltage drop (IR drop), such that the brightnesses of the light emitting elements L2 and L5 are not affected by the internal resistance of the pixel driving circuit. In addition, the pixel driving circuits 600 and 800 can perform the detection with respect to the internal elements before coupling of the light emitting elements L6 and L8, such that the manufacturing costs are reduced.
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 109146954 | Dec 2020 | TW | national |
This application is a continuation application of U.S. application Ser. No. 17/203,792, filed on Mar. 17, 2021, which claims priority to Taiwan Application Serial Number 109146954, filed Dec. 30, 2020, which is herein incorporated by reference in its entirety.
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| Number | Date | Country | |
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| Parent | 17203792 | Mar 2021 | US |
| Child | 17717803 | US |
