Patent Application
20180308424
The present disclosure relates to a display device, a display device driving method, a display element, and an electronic apparatus.
A display element provided with a current-driven light-emitting unit, and a display device provided with the display element, are well known. For example, a display element provided with a light-emitting unit that uses electroluminescence of an organic material (hereinafter, may be merely referred to as “organic EL display element”) attracts attention as a display element that is capable of high-luminance light emission by low-voltage DC driving.
As with liquid crystal display devices, in the field of, for example, display devices, each of which is provided with an organic EL display element, as well, a simple matrix method and an active matrix method are well known as driving methods. The active matrix method has a disadvantage that a structure becomes complicated. However, the active matrix method has, for example, an advantage that the brightness of an image can be made high. An organic EL display element driven by the active matrix method is provided with not only a light-emitting unit that includes an organic layer including a light-emitting layer and the like, but also a driving circuit having a driving transistor for driving the light-emitting unit.
A value of a current flowing through the driving transistor is influenced not only by a voltage of a gate electrode with respect to a source region of the driving transistor (so-called a voltage between the gate and the source) but also by a threshold voltage of the driving transistor. The threshold voltage of the driving transistor disperses on a display element basis, and therefore causes uneven brightness. For example, Japanese Patent Application Laid-Open No. 2008-287139 (Patent Document 1) discloses the feature of performing the operation of canceling an influence, which is exerted by the dispersion in threshold voltage of a driving transistor, every time a video signal is written to a display element.
The operation of canceling the influence, which is exerted by the dispersion in threshold voltage of a driving transistor, every time a video signal is written becomes a factor for increasing the power consumption of a display device. In general, the power consumption of an electronic apparatus is desired to be low. Accordingly, a reduction in power consumption of a display device is also expected.
Therefore, an object of the present invention is to provide: a display device that is capable of further reducing the power consumption while canceling an influence exerted by the dispersion in threshold voltage of a driving transistor; a method for driving the display device; a display element; and an electronic apparatus.
In order to achieve the above-described object, a display device according to the present disclosure includes: a display unit in which display elements are arranged; and a drive unit for driving the display unit, in which:
the display elements each include: a current-driven light-emitting unit; a capacitor unit including a first capacitor and a second capacitor; an n-channel driving transistor that causes a current corresponding to a voltage held by the capacitor unit to flow through the light-emitting unit; and a first switching transistor that writes a video signal voltage to the capacitor unit;
in the capacitor unit, one end of the first capacitor is connected to a gate electrode of the driving transistor to form a first node, the other end of the first capacitor is connected to one end of the second capacitor to form a second node, and the other end of the second capacitor is connected to one end of the light-emitting unit, and to the other source/drain region of the driving transistor to form a third node;
in the driving transistor, one source/drain region is connected to an electric supply line, and the other source/drain region is connected to the light-emitting unit;
in the first switching transistor, one source/drain region is connected to a data line, and the other source/drain region is connected to the third node; and
in a state in which the first capacitor holds a voltage corresponding to a threshold voltage of the driving transistor, the drive unit writes a video signal voltage to the second capacitor through the first switching transistor in a conducting state.
In order to achieve the above-described object, there is provided a method for driving a display device according to the present disclosure, the display device including: a display unit in which display elements are arranged; and a drive unit for driving the display unit, in which:
the display elements each include: a current-driven light-emitting unit; a capacitor unit including a first capacitor and a second capacitor; an n-channel driving transistor that causes a current corresponding to a voltage held by the capacitor unit to flow through the light-emitting unit; and a first switching transistor that writes a video signal voltage to the capacitor unit;
in the capacitor unit, one end of the first capacitor is connected to a gate electrode of the driving transistor to form a first node, the other end of the first capacitor is connected to one end of the second capacitor to form a second node, and the other end of the second capacitor is connected to one end of the light-emitting unit, and to the other source/drain region of the driving transistor to form a third node;
in the driving transistor, one source/drain region is connected to an electric supply line, and the other source/drain region is connected to the light-emitting unit;
in the first switching transistor, one source/drain region is connected to a data line, and the other source/drain region is connected to the third node; and
in a state in which the first capacitor holds a voltage corresponding to a threshold voltage of the driving transistor, the drive unit writes a video signal voltage to the second capacitor through the first switching transistor in a conducting state.
In order to achieve the above-described object, a display element according to the present disclosure includes:
a current-driven light-emitting unit; a capacitor unit including a first capacitor and a second capacitor; an n-channel driving transistor that causes a current corresponding to a voltage held by the capacitor unit to flow through the light-emitting unit; and a first switching transistor that writes a video signal voltage to the capacitor unit;
in which:
in the capacitor unit, one end of the first capacitor is connected to a gate electrode of the driving transistor to form a first node, the other end of the first capacitor is connected to one end of the second capacitor to form a second node, and the other end of the second capacitor is connected to one end of the light-emitting unit, and to the other source/drain region of the driving transistor to form a third node;
in the driving transistor, one source/drain region is connected to an electric supply line, and the other source/drain region is connected to the light-emitting unit;
in the first switching transistor, one source/drain region is connected to a data line, and the other source/drain region is connected to the third node; and
in a state in which the first capacitor holds a voltage corresponding to a threshold voltage of the driving transistor, a video signal voltage is written to the second capacitor through the first switching transistor in a conducting state.
In order to achieve the above-described object, an electronic apparatus according to the present disclosure includes a display device, in which:
the display device includes: a display unit in which display elements are arranged; and a drive unit for driving the display unit;
the display elements each include: a current-driven light-emitting unit; a capacitor unit including a first capacitor and a second capacitor; an n-channel driving transistor that causes a current corresponding to a voltage held by the capacitor unit to flow through the light-emitting unit; and a first switching transistor that writes a video signal voltage to the capacitor unit;
in the capacitor unit, one end of the first capacitor is connected to a gate electrode of the driving transistor to form a first node, the other end of the first capacitor is connected to one end of the second capacitor to form a second node, and the other end of the second capacitor is connected to one end of the light-emitting unit, and to the other source/drain region of the driving transistor to form a third node;
in the driving transistor, one source/drain region is connected to an electric supply line, and the other source/drain region is connected to the light-emitting unit;
in the first switching transistor, one source/drain region is connected to a data line, and the other source/drain region is connected to the third node; and
in a state in which the first capacitor holds a voltage corresponding to a threshold voltage of the driving transistor, the drive unit writes a video signal voltage to the second capacitor through the first switching transistor in a conducting state.
In the display device, the display device driving method, the display element, and the electronic apparatus according to the present disclosure, in a state in which the first capacitor holds a voltage corresponding to a threshold voltage of the driving transistor, a video signal voltage is written to the second capacitor through the first switching transistor in a conducting state. This enables a frequency of operations of holding, in the first capacitor, a voltage corresponding to a threshold voltage of the driving transistor to be reduced. Therefore, the power consumption can be further reduced while canceling an influence exerted by the dispersion in threshold voltage of the driving transistor. It should be noted that the effects described herein are not necessarily limited, and may be any one of the effects described in the present disclosure.
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The present disclosure will be described below on the basis of embodiments with reference to the accompanying drawings. The present disclosure is not limited to the embodiments, and various numerical values and materials in the embodiments are merely examples. In the following explanations, the same element, or an element having the same function, uses the same reference numeral, and overlapping explanation will be omitted. It should be noted that explanations are made in the following order.
1. Overall explanation about a display device, a display device driving method, a display element, and an electronic apparatus according to the present disclosure
2. First Embodiment
3. Second Embodiment
4. Third Embodiment
5. Fourth Embodiment
6. Fifth Embodiment
7. Sixth Embodiment
8. Seventh Embodiment
9. Eighth Embodiment
10. Display device according to modified examples
11. Explanation of electronic apparatus, and others
In a display device, a display device driving method, and an electronic apparatus according to the present disclosure, a drive unit can be configured to scan display elements of a display unit consecutively, and to perform the operation of holding, in a first capacitor, a voltage corresponding to a threshold voltage of a driving transistor in a part of a plurality of consecutive frames.
The above-described operation may be performed, for example, once every two frames, or once every five or ten frames. From the viewpoint of reducing the power consumption, it is preferable to reduce a frequency of frames in which the operation of holding a voltage corresponding to the threshold voltage of the driving transistor in the first capacitor is performed. Meanwhile, the voltage held in the first capacitor changes due to leakage or the like. Therefore, from the viewpoint of, for example, reducing uneven brightness, it is preferable to maintain a certain level of frequency. A level of frequency may be set as appropriate according to, for example, specifications of the display device.
The operation of holding a voltage corresponding to the threshold voltage of the driving transistor in the first capacitor, and the operation of writing a video signal may be performed in some specific frame.
Alternatively, the following operation may be performed: in some specific frame, for all display elements, performing only the operation of holding a voltage corresponding to the threshold voltage of the driving transistor in the first capacitor; and in the subsequent frame, performing the operation of writing a video signal.
There is also a possibility that the voltage held by the first capacitor will change due to leakage or the like after the operation of holding the voltage corresponding to the threshold voltage of the driving transistor in the first capacitor has been performed until similar operation is performed next time. In such a case, a video signal voltage that has been corrected to compensate for a change in voltage of the first capacitor may be written to a second capacitor, for example.
In the present disclosure including the above-described preferable configuration,
the drive unit applies a reference voltage to the first node, and applies an initialization voltage to the second node and the third node, to set a voltage held by the capacitor unit so as to exceed the threshold voltage of the driving transistor, and subsequently applies the reference voltage to the first node, and applies the driving voltage to one source/drain region of the driving transistor in a state in which the second node and the third node electrically conduct with each other, so as to cause electric potentials of the second node and the third node to get close to a voltage obtained by subtracting the threshold voltage of the driving transistor from the reference voltage, consequently causing a voltage corresponding to the threshold voltage of the driving transistor to be held in the first capacitor.
In this case, the display elements each further include a second switching transistor, a third switching transistor, and a fourth switching transistor;
in the second switching transistor, the reference voltage is applied to one source/drain region, and the other source/drain region is connected to the second node;
in the third switching transistor, one source/drain region is connected to the second node, and the other source/drain region is connected to the third node;
in the fourth switching transistor, the reference voltage is applied to one source/drain region, and the other source/drain region is connected to the first node;
the reference voltage is applied to the first node by bringing the fourth switching transistor into the conducting state; and
the second node and the third node are brought into the conducting state by bringing the third switching transistor into the conducting state.
The initialization voltage is supplied from the data line through the first switching transistor. Alternatively, the initialization voltage may be supplied from the electric supply line through the driving transistor.
The display elements each further include a fifth switching transistor, and
the other source/drain region of the driving transistor may be connected to one end of the light-emitting unit through the fifth switching transistor.
Alternatively, the display elements each further include a second switching transistor, a third switching transistor, and a fourth switching transistor;
in the second switching transistor, the initialization voltage is applied to one source/drain region, and the other source/drain region is connected to the second node;
in the third switching transistor, the reference voltage is applied to one source/drain region, and the other source/drain region is connected to the first node;
the other source/drain region of the driving transistor is connected to one end of the light-emitting unit through the fourth switching transistor;
the reference voltage is applied to the first node by bringing the third switching transistor into the conducting state;
the initialization voltage is applied to the first node by bringing the second switching transistor into the conducting state; and
a conducting state/a non-conducting state of the second switching transistor are controlled by a control line in common with the first switching transistor.
In the present disclosure including the above-described preferable configuration,
the drive unit applies a reference voltage to the first node, and applies an initialization voltage to the second node and the third node, to set a voltage held by the capacitor unit so as to exceed the threshold voltage of the driving transistor, and subsequently applies the reference voltage to the first node, and applies the driving voltage to one source/drain region of the driving transistor in a state in which the second node and the third node electrically conduct with each other, so as to cause electric potentials of the second node and the third node to get close to a voltage obtained by subtracting the threshold voltage of the driving transistor from the reference voltage, consequently causing a voltage corresponding to the threshold voltage of the driving transistor to be held in the first capacitor.
In this case, the display elements each further include a second switching transistor, a third switching transistor, and a fourth switching transistor;
in the second switching transistor, the initialization voltage is applied to one source/drain region, and the other source/drain region is connected to the second node;
in the third switching transistor, the reference voltage is applied to one source/drain region, and the other source/drain region is connected to the first node;
the other source/drain region of the driving transistor is connected to one end of the light-emitting unit through the fourth switching transistor;
the reference voltage is applied to the first node by bringing the third switching transistor into the conducting state;
the initialization voltage is applied to the second node by bringing the second switching transistor into the conducting state; and
a conducting state/a non-conducting state of the second switching transistor are controlled by a control line in common with the first switching transistor.
Alternatively, in the present disclosure including the above-described preferable configuration, the drive unit applies a reference voltage to the second node and the third node, and supplies a driving voltage from the electric supply line in a state in which the first node and one source/drain region of the driving transistor electrically conduct with each other, to set a voltage held by the capacitor unit so as to exceed a threshold voltage of the driving transistor, and subsequently
interrupts a connection between the electric supply line and the driving transistor in a state in which the reference voltage is applied to the second node and the third node, so as to cause an electric potential of the first node to get close to an electric potential obtained by adding the threshold voltage of the driving transistor to the reference voltage, consequently causing a voltage corresponding to the threshold voltage of the driving transistor to be held in the first capacitor.
In this case, the display elements each further include a second switching transistor, a third switching transistor, a fourth switching transistor, and a fifth switching transistor;
in the second switching transistor, the reference voltage is applied to one source/drain region, and the other source/drain region is connected to the second node;
in the third switching transistor, one source/drain region is connected to the second node, and the other source/drain region is connected to the third node;
a connection between the first node and one source/drain region of the driving transistor is made through the fourth switching transistor;
a connection between the electric supply line and one source/drain region of the driving transistor is made through the fifth switching transistor;
the reference voltage is applied to the second node and the third node by bringing the second switching transistor and the third switching transistor into the conducting state;
the first node and one source/drain region of the driving transistor are brought into the conducting state by bringing the fourth switching transistor into the conducting state; and
the connection between the electric supply line and the driving transistor is interrupted by bringing the fifth switching transistor into the non-conducting state.
In this case, the display elements each further include a sixth switching transistor; and
the other source/drain region of the driving transistor is connected to one end of the light-emitting unit through the sixth switching transistor.
Alternatively, the display elements each further include a second switching transistor, a third switching transistor, and a fourth switching transistor;
in the second switching transistor, the reference voltage is applied to one source/drain region, and the other source/drain region is connected to the second node;
a connection between the first node and one source/drain region of the driving transistor is made through the third switching transistor;
a connection between the electric supply line and one source/drain region of the driving transistor is made through the fourth switching transistor;
the reference voltage is supplied from the data line through the first switching transistor, and is applied to the first node, and the reference voltage is applied to the second node by bringing the second switching transistor into the conducting state;
the first node and one source/drain region of the driving transistor are brought into the conducting state by bringing the third switching transistor into the conducting state; and
the connection between the electric supply line and the driving transistor is interrupted by bringing the fourth switching transistor into the non-conducting state.
In the above-described various preferable configurations, a voltage in which the threshold voltage of the driving transistor is reflected suffices as the voltage held in the first capacitor. Therefore, it is not always required that the voltage held in the first capacitor agrees with the threshold voltage.
In the display device, the display device driving method, the display element, and the electronic apparatus according to the present disclosure including the above-described various preferable configurations (hereinafter, may be merely referred to as “the present disclosure”), the light-emitting unit may include a current-driven electro-optic element, the light emission brightness of which changes according to a value of a flowing current. An organic electroluminescent light-emitting unit, an LED light-emitting unit, a semiconductor laser light-emitting unit, and the like can be mentioned as the current-driven light-emitting unit. These light-emitting units can be configured by using a well-known material or method. From the viewpoint of configuring a flat-type display device, it is preferable that the light-emitting unit includes, above all, an organic electroluminescent light-emitting unit.
The drive unit used in the present disclosure including the above-described various preferable configurations includes, for example, a circuit such as a data-line drive unit, a power supply unit, and a control-line drive unit. These can be configured by using a well-known circuit element or the like.
The display device may be a so-called monochrome display configuration, or a color display configuration. In the case of the color display configuration, one pixel may include a plurality of sub-pixels. More specifically, one pixel may include three sub-pixels that are a red light-emitting sub-pixel, a green light-emitting sub-pixel, and a blue light-emitting sub-pixel. Moreover, one pixel may include a set of sub-pixels obtained by further adding one kind of or two or more kinds of sub-pixels to the above three kinds of sub-pixels (for example, a set of sub-pixels obtained by adding a sub-pixel that emits white light for improving brightness, a set of sub-pixels obtained by adding a sub-pixel that emits a complementary color for magnifying a color reproduction range, a set of sub-pixels obtained by adding a sub-pixel that emits yellow for magnifying a color reproduction range, and a set of sub-pixels obtained by adding sub-pixels that emit yellow and cyan for magnifying a color reproduction range).
As values of pixels (pixels) of the display device, other than VGA (640, 480), S-VGA (800, 600), XGA (1024, 768), APRC (1152, 900), S-XGA (1280, 1024), U-XGA (1600, 1200), HD-TV (1920, 1080), and Q-XGA (2048, 1536), some image display resolutions such as (1920, 1035), (720, 480) and (1280, 960) can be presented. However, image display resolutions are not limited to these values.
The display element that is included in the display unit is formed in a certain plane (for example, the display element is formed on a support base). For example, through the interlayer insulating layer, the light-emitting unit is formed above the driving circuit that drives the light-emitting unit.
The driving circuit that drives the light-emitting unit can be configured as a circuit that includes a transistor and a capacitor unit. As the transistor that is included in the driving circuit, for example, a thin film transistor (TFT) can be mentioned. The transistor may be an enhancement type transistor or a depletion type transistor. An n-channel transistor may be formed with a Lightly Doped Drain (LDD) structure. In some cases, the LDD structure may be unsymmetrically formed. For example, a large current flows through the driving transistor when the display element emits light. Therefore, the LDD structure may be formed only in one source/drain region that becomes a drain region at the time of light emission.
With respect to two source/drain regions of one transistor, there is a case where the term “one source/drain region” is used to mean a source/drain region connected to the power supply side. In addition, when a transistor is in a conducting state, this means a state in which a channel is formed between the source/drain regions. It does not matter whether or not a current flows from one source/drain region of the transistor to the other source/drain region. Meanwhile, when the transistor is in a non-conducting state, this means a state in which a channel is not formed between the source/drain regions. Moreover, the source/drain regions can be configured not only from a conductive material such as polysilicon and amorphous silicon containing impurities, but also from a layer that includes metal, alloy, conductive particles, a layered structure thereof, and an organic material (conductive polymer).
Each capacitor that is included in the capacitor unit can be configured from a pair of electrodes, and a dielectric layer that is put between these electrodes. The transistor and the capacitor unit that are included in the driving circuit are formed in a certain plane (for example, the transistor and the capacitor unit are formed on the support base). For example, through the interlayer insulating layer, the light-emitting unit is formed above the transistor and the capacitor unit that are included in the driving circuit. It should be noted that a configuration in which a transistor is formed on a semiconductor substrate or the like may be employed.
Various kinds of wiring lines such as a control line and a data line or an electric supply line are formed on a certain plane (for example, on the support base). These wiring lines can be regarded as a well-known configuration or structure.
As a constituent material of the support base or a constituent material of a substrate as described later, other than a glass material such as high-strain point glass, soda glass (Na2O.CaO.SiO2), borosilicate glass (Na2O.B2O3.SiO2), forsterite (2MgO.SiO2), and lead glass (Na2O.PbO.SiO2), it is possible to present a flexible polymeric material, for example, a polymeric material, typified by polyether sulfone (PES), polyimide, polycarbonate (PC), and polyethylene terephthalate (PET). It should be noted that a surface of the support base or a surface of the substrate may be provided with various coatings. The constituent material of the support base and the constituent material of the substrate may be the same, or may differ. If the support base and the substrate each including a flexible polymeric material are used, a flexible display device can be configured.
Conditions represented by various equations in the present description are fulfilled not only in a case where the equations mathematically and strictly hold, but also in a case where the equations substantially hold. With respect to whether or not the equations hold, various dispersions that occur while designing or producing a display element and a display device are allowed.
In timing charts used in the explanations below, a length (time length) of the horizontal axis indicating each time period is merely schematic, and thus does not indicate a ratio of the time length of each time period. The same applies to the vertical axis. In addition, waveform shapes in the timing chart are also schematic.
The first embodiment relates to a display device, a display device driving method, and a display element according to the present disclosure.
In the display unit 10, the display elements 11 are arranged in a two-dimensional matrix form in a state in which the display elements 11 are connected to first to fifth control lines WS1 to WS5 each extending in a row direction (X direction in
For convenience of illustration,
The display device 1 is provided with a data-line drive unit 21, a power supply unit 22, and a control-line drive unit 23. The data-line drive unit 21, the power supply unit 22, and the control-line drive unit 23 constitute the drive unit 20 for driving the display unit 10.
Various signals are supplied from the control-line drive unit 23 to the first to fifth control lines WS1 to WS5. For example, a video signal voltage corresponding to the brightness of an image to be displayed is supplied to the data lines DTL. A driving voltage or the like is supplied from the power supply unit 22 to electric supply lines DS. Incidentally, there is a case where the first to fifth control lines WS1 to WS5 are merely collectively referred to as “control lines”.
Although not illustrated in
The numbers of the first to fifth control lines WS1 to WS5, and the number of the electric supply lines DS, are each M. The display elements 11 in the m-th row (where m=1, 2, . . . , M) are each connected to the first to fifth control lines WS1m to WS5m corresponding to the m-th, and are each connected to the m-th electric supply line DSm, thereby constituting one display element row. It should be noted that
In addition, the number of data lines DTL is N. The display elements 11 in the n-th column (where n=1, 2, . . . , N) are each connected to the n-th data line DTLn. It should be noted that
The display element 11 includes: a current-driven light-emitting unit ELP; a capacitor unit CP including a first capacitor CS1 and a second capacitor CS2; an n-channel driving transistor TRDrv that causes a current corresponding to a voltage held by the capacitor unit CP to flow through the light-emitting unit ELP; and a first switching transistor TR1 that writes a video signal voltage to the capacitor unit CP. The driving transistor TRDrv includes an n-channel TFT. The same applies to the other transistors.
In the capacitor unit CP, one end of the first capacitor CS1 is connected to a gate electrode of the driving transistor TRDrv to form a first node ND1_G, the other end of the first capacitor CS1 is connected to one end of the second capacitor CS2 to form a second node ND2, and the other end of the second capacitor CS2 is connected to one end (anode electrode with which the light-emitting unit is provided) of the light-emitting unit ELP, and to the other source/drain region of the driving transistor TRDrv, to form a third node ND3_S. In the driving transistor TRDrv, one source/drain region is connected to the electric supply line DS, and the other source/drain region is connected to the light-emitting unit ELP through a fifth switching transistor TR5 as described later. In the first switching transistor TR1, one source/drain region is connected to the data line DTL, and the other source/drain region is connected to the third node ND3_S.
The display elements 11 are each further provided with a second switching transistor TR2, a third switching transistor TR3, and a fourth switching transistor TR4. In the second switching transistor TR2, a reference voltage Vofs is applied to one source/drain region, and the other source/drain region is connected to the second node ND2. In the third switching transistor TR3, one source/drain region is connected to the second node ND2, and the other source/drain region is connected to the third node ND3_S. In the fourth switching transistor TR4, the reference voltage Vofs is applied to one source/drain region, and the other source/drain region is connected to the first node ND1_G.
The display elements 11 are each further provided with a fifth switching transistor TR5. The other source/drain region of the driving transistor TRDrv is connected to one end of the light-emitting unit ELP through the fifth switching transistor TR5.
The driving transistor TRDrv, the capacitor unit CP, and the first to fifth switching transistors TR1 to TR5 described above constitute a driving circuit 12 for driving the light-emitting unit ELP.
Gate electrodes of the first to fifth switching transistors TR1 to TR5 are connected to the first to fifth control lines WS1 to WS5 respectively. Conducting state/non-conducting state of the first to fifth switching transistors TR1 to TR5 are controlled by a signal from the control-line drive unit 23.
The capacitor unit CP is used to hold a voltage of the gate electrode (so-called a voltage between a gate and a source) with respect to a source region of the driving transistor TRDrv. In this case, the “source region” means a source/drain region on the side that functions as a “source region” when the light-emitting unit ELP emits light. In a light emitting state of the display element 11, one source/drain region (the side connected to the electric supply line DS in
The display device 1 is, for example, a monochrome display device, and one display element 11 forms one pixel. The display device 1 is line-sequentially scanned on a row basis by a control signal from the control-line drive unit 23. Hereinafter, the display element 11 located at the m-th row and the n-th column is referred to as the (n, m)th display element 11 or the (n, m)th pixel. In addition, a scanning period (horizontal scanning period) that is assigned to the display elements 11 in the m-th row is represented by reference numeral Hm. Moreover, when considering a frame with reference to the scanning period Hm, a scanning period in a frame immediately before a frame to which the scanning period Hm belongs is represented by reference numeral H′, and a scanning period in a frame immediately after a frame to which the scanning period Hm belongs is represented by reference numeral H″.
In the display device 1, the display elements 11 that form respective N pieces of pixels arranged in the m-th row are concurrently driven. In other words, with respect to the N pieces of the display elements 11 arranged along a row direction, the timing of light-emission/non-light emission is controlled for each row to which the display elements 11 belong. If a display frame rate of the display device 1 is represented as FR (times/sec), a scanning period per row (so-called a horizontal scanning period) obtained when the display device 1 is line-sequentially scanned on a row basis is less than (1/FR)×(1/M) seconds.
A video signal DSig representing gradation, and corresponding to an image to be displayed, is input into the display device 1 from, for example, a device that is not illustrated. The video signal DSig is a digital signal based on the number of gradation bits such as 8 bits, 16 bits and 24 bits. There is a case where among the video signals DSig that are input, a video signal corresponding to the (n, m)th display element 11 is represented as DSig(n, m).
The data-line drive unit 21 generates a voltage corresponding to a value of the video signal DSig, and supplies the voltage to the data line DTL. A video signal voltage corresponding to the video signal DSig is represented as VSig. In addition, in a case where the video signal voltage VSig indicates corresponding to, for example, the (n, m)th display element 11, there is a case where the video signal voltage VSig is represented as a video signal voltage VSig(n, m) or a video signal voltage VSig_m.
In the first embodiment, the data-line drive unit 21 supplies an initialization voltage Vini and the video signal voltage VSig to the data line DTL. The power supply unit 22 supplies a driving voltage Vccp to the electric supply line DS.
The light-emitting unit ELP is a current-driven electro-optic element, the light emission brightness of which changes according to a value of a flowing current. More specifically, the light-emitting unit ELP includes an organic electroluminescent element. The light-emitting unit ELP has a well-known configuration or structure, and includes an anode electrode, a positive hole transport layer, a light-emitting layer, an electron transport layer, a cathode electrode, and the like.
A voltage Vcath (for example, 0 [V]) is applied to the other end (more specifically, the cathode electrode) of the light-emitting unit ELP from a common electric supply line. It is assumed that a threshold voltage required for light emission of the light-emitting unit ELP is Vth-EL. When a voltage that is higher than or equal to Vth-EL is applied between the anode electrode and the cathode electrode of the light-emitting unit ELP, the light-emitting unit ELP emits light.
Reference numeral CEL represents a capacitance of the light-emitting unit ELP. Incidentally, in a case where the capacitance of the light-emitting unit ELP is small, and consequently, for example, interferes with the driving of the display element 11, an auxiliary capacitor CSub that is connected to the light-emitting unit ELP in parallel has only to be provided. The explanation below is made on the assumption that the auxiliary capacitor CSub is provided. However, the explanation is merely an example. The auxiliary capacitor CSub may be omitted.
Here, an arrangement relationship among the light-emitting unit ELP, the transistors, and the like will be described.
The transistors and the capacitor units are formed on a support base 31, and the light-emitting unit ELP is formed above the transistors and the capacitor units through, for example, an interlayer insulating layer 50. In addition, through the unillustrated fifth switching transistor TR5 and contact holes, the other source/drain region of the driving transistor TRDrv is connected to the anode electrode with which the light-emitting unit ELP is provided. It should be noted that
The driving transistor TRD, includes a gate electrode 41, a gate insulating layer 42, one source/drain region 45A that is provided in a semiconductor layer 43, the other source/drain region 45B, and a channel-forming region 44 that corresponds to a part of the semiconductor layer 43 between the one source/drain region 45A and the other source/drain region 45B. Meanwhile, the first capacitor CS1 and the second capacitor CS2 that constitute the capacitor unit CP each include a pair of electrodes that sandwiches a dielectric layer including an extending part of the gate insulating layer 42. For example, the second capacitor CS2 includes one electrode 46, the dielectric layer including the extending part of the gate insulating layer 42, and the other electrode 47. The second capacitor CS2 is hidden and does not appear.
The gate electrode 41, a part of the gate insulating layer 42, and the one electrode 46 that constitutes the capacitor unit CP are formed on the support base 31. The one source/drain region 45A of the driving transistor TRDrv is connected to a wiring line 48 (corresponding to the electric supply line DS). The driving transistor TRDrv, the capacitor unit CP, and the like are covered with the interlayer insulating layer 50. The light-emitting unit ELP that includes the anode electrode 61, the positive hole transport layer, the light-emitting layer, the electron transport layer, and the cathode electrode 63 is provided on the interlayer insulating layer 50. It should be noted that the positive hole transport layer, the light-emitting layer, and the electron transport layer are illustrated as one layer 62 in the figure. A second interlayer insulating layer 64 is provided on a part of the interlayer insulating layer 50, the part not being provided with the light-emitting unit ELP. A transparent substrate 32 is arranged on the second interlayer insulating layer 64 and on the cathode electrode 63. Light emitted in the light-emitting layer passes through the substrate 32, and is then emitted to the outside. In addition, through contact holes 66 and 65 with which the second interlayer insulating layer 64 and the interlayer insulating layer 50 are provided respectively, the cathode electrode 63 is connected to a wiring line 49 (corresponding to the common electric supply line that supplies the voltage Vcath) provided on the extending part of the gate insulating layer 42.
A voltage of the driving transistor TRDrv shown in
μ: Effective mobility
L: Channel length
W: Channel width
Vgs: Gate electrode voltage (voltage between the gate and the source) for the source region
Vth: Threshold voltage
Cox: (Relative permittivity of gate insulating layer)×(vacuum permittivity)/(thickness of gate insulating layer)
k≅(½)·(W/L)·Cox
I
ds
=k·μ·(Vgs−Vth)2 (1)
This drain current Ids flows through the light-emitting unit ELP, which causes the light-emitting unit ELP of the display element 11 to emit light. Moreover, light intensity of the light-emitting unit ELP while the drain current Ids flows is controlled on the basis of a value of this drain current Ids.
The display device 1 has been outlined as above. The above explanation is basically similar to those of the display devices in the other embodiments as described later. It should be noted that, for example, a difference in circuit configuration between the display elements will be described in detail in the explanation of each embodiment.
Next, the operation of the display device 1 will be described with reference to the accompanying drawings.
The operation of the display device 1 will be outlined as below. In the present disclosure, in a state in which a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv is held by the first capacitor CS1, the drive unit 20 writes the video signal voltage VSig to the second capacitor CS2 through the first switching transistor TR1 in a conducting state. The drive unit 20 successively scans the display elements 11 of the display unit 10, and in a part of a plurality of consecutive frames, performs the operation of causing a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv to be held in the first capacitor CS1.
In the first embodiment, the drive unit 20 applies the reference voltage Vofs to the first node ND1_G, and applies the initialization voltage Vini to the second node ND2 and the third node ND3_S, thereby setting the voltage held by the capacitor unit CP so as to exceed the threshold voltage Vth of the driving transistor TRDrv. Subsequently, the drive unit 20 applies the reference voltage Vofs to the first node ND1_G, and applies the driving voltage Vccp to one source/drain region of the driving transistor TRDrv in a state in which the second node ND2 and the third node ND3_S electrically conduct with each other, so as to cause electric potentials of the second node ND2 and the third node ND3_S to get close to a voltage obtained by subtracting the threshold voltage Vth of the driving transistor TRDrv from the reference voltage Vofs, thereby causing a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv to be held in the first capacitor CS1. In the first embodiment, the initialization voltage Vini is supplied from the data line DTL through the first switching transistor TR1.
In the following explanations, voltage values or electric potential values are given as follows. However, the values are strictly given for the purpose of explanation, and voltages or electric potentials are not limited to these values.
Vini: Initialization voltage . . . −3 V
Vofs: Reference voltage . . . 0 V
Vccp: Driving voltage for causing a current to flow through the light-emitting unit ELP . . . 15 V
VSig: Video signal voltage . . . -2 V to 0 V
Vth: Threshold voltage of the driving transistor TRD, . . . 1 V
Vcath: Voltage applied to the cathode electrode of the light-emitting unit ELP . . . 0 V
Vth-EL: Threshold voltage of the light-emitting unit ELP . . . 2 V
[Time Period: Before H′m−4] (Refer to
This time period is before the [time period H′m−3] shown in
[Time Period: H′m−3] (Refer to
Initialization processing is performed during this time period. In other words, by applying the reference voltage Vofs to the first node ND1_G, and by applying the initialization voltage Vini to the second node ND2 and the third node ND3_S, the voltage held by the capacitor unit CP is set so as to exceed the threshold voltage Vth of the driving transistor TRDrv.
More specifically, the fifth control line WS5m is switched to a low level. The fifth switching transistor TR5 is in a non-conducting state. The driving transistor TRDrv and the light-emitting unit ELP are electrically separated from each other, and therefore the light-emitting unit ELP switches off the light. In addition, the first control line WS1m, the third control line WS3m, and the fourth control line WS4m are switched to a high level. The first switching transistor TR1, the third switching transistor TR3, and the fourth switching transistor TR4 are in a conducting state. The second control line WS2m maintains a previous state, and therefore the second switching transistor TR2 is in a non-conducting state.
The reference voltage Vofs is applied to the first node ND1_G through the fourth switching transistor TR4 in the conducting state. In addition, the initialization voltage Vini is applied to the third node ND3_S from the data line DTL through the first switching transistor TR1 in the conducting state. The third switching transistor TR3 is in the conducting state, and therefore the initialization voltage Vini is also applied to the second node ND2 from the data line DTL. The voltage held by the capacitor unit CP becomes (Vofs−Vini), and exceeds the threshold voltage Vth of the driving transistor TRDrv.
[Time Period: H′m−2] (Refer to
Threshold voltage cancel processing is performed during this time period. In other words, by applying the reference voltage Vofs to the first node ND1_G, and by applying the driving voltage Vccp to one source/drain region of the driving transistor TRDrv in a state in which the second node ND2 and the third node ND3_S electrically conduct with each other, electric potentials of the second node ND2 and the third node ND3_S are caused to get close to a voltage obtained by subtracting the threshold voltage Vth of the driving transistor TRDrv from the reference voltage Vofs.
More specifically, the first control line WS1m is switched to a low level, and the fifth control line WS5m is switched to a high level. The other control lines maintain the previous state. The reference voltage Vofs is applied to the first node ND1_G through the fourth switching transistor TR4. In addition, the second node ND2 and the third node ND3_S are in a conducting state through the third switching transistor TR3.
The voltage held by the capacitor unit CP exceeds the threshold voltage Vth of the driving transistor TRDrv, and therefore, through the driving transistor TRDrv, a current from the electric supply line DS flows through the third node ND3_S. As the result, the electric potential of the third node ND3_S increases toward an electric potential obtained by subtracting the threshold voltage Vth of the driving transistor TRDrv from the reference voltage Vofs. The electric potential of the second node ND2 that is in a conducting state with the third node ND3_S also similarly increases (refer to
If this time period is sufficiently long, an electric potential difference between the gate electrode of the driving transistor TRDrv, and the other source/drain region reaches Vth, and the driving transistor TRdrv enters the non-conducting state (refer to
Incidentally, for convenience of explanation, the explanation is made on the assumption that the driving transistor TRDrv is already in the non-conducting state during this time period. However, the present disclosure is not limited to this. A mode may be employed in which the time period ends before the electric potential difference between the gate electrode of the driving transistor TRDrv and the other source/drain region reaches Vth.
[Time Period: H′m−1] (Refer to
This time period is a time period immediately before performing the next write processing, and a time period for waiting for writing. The third control line WS3m, the fourth control line WS4m, and the fifth control line WS5m are switched to a low level. The third switching transistor TR3, the fourth switching transistor TR4, and the fifth switching transistor TR5 enter the non-conducting state. In addition, the first control line WS1m and the second control line WS2m maintain the previous state. The first to fifth switching transistors TR1 to TR5 are in the non-conducting state. If the driving transistor TRDrv is already in the non-conducting state in the [time period: H′m−2], electric potentials of the first node ND1_G, the second node ND2 and the third node ND3_S do not substantially change (refer to
[Time Period: Hm] (Refer to
A video signal voltage VSig_m is supplied to the data line DTLn in accordance with this time period. In addition, during this time period, in a state in which a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv is held by the first capacitor CS1, the video signal voltage VSig_m is written to the second capacitor CS2 through the first switching transistor TR1 in the conducting state.
More specifically, the first control line WS1m and the second control line WS2m are switched to a high level. The other control lines maintain the previous state. The first switching transistor TR1 and the second switching transistor TR2 enter the conducting state. The other switching transistors are in the non-conducting state.
In the immediately preceding [time period: H′m−1], an electric potential of the first node ND1_G is Vofs, an electric potential of the second node ND2 is (Vofs−Vth), and the voltage Vth is held in the first capacitor CS1. When the second switching transistor TR2 enters the conducting state, the reference voltage Vofs is applied to the second node ND2. Therefore, the electric potential of the second node ND2 changes from (Vofs−Vth) to Vofs. Here, the fourth switching transistor TR4 is in the non-conducting state. Therefore, if an influence exerted by parasitic capacitance or the like can be ignored, the first capacitor CS1 maintains the previous state in which the voltage Vth is held. Therefore, the electric potential of the first node ND1_G becomes (Vofs+Vth) from Vofs. In addition, the video signal voltage VSig_m is applied to the third node ND3_S through the first switching transistor TR1 in the conducting state. The reference voltage Vofs is applied to the second node ND2, and therefore a voltage, for example, (Vofs−VSig_m), is held in the second capacitor CS2. As the result, the capacitor unit CP that includes the first capacitor CS1 and the second capacitor CS2 holds a voltage, for example, (Vth+Vofs−VSig_m).
[Time Period: Hm+1] (Refer to
A light emission period ranges from this time period until the starting period of a scanning period [time period: Hm−1] immediately before the scanning period H″m in the m-th row in the next frame.
More specifically, the first control line WS1m and the second control line WS2m are switched to a low level, and the fifth control line WS5m is switched to a high level. The fifth switching transistor TR5 is in the conducting state, and the other switching transistors are in the non-conducting state.
The fifth switching transistor TR5 is in the conducting state, and therefore the voltage Vgs between the gate and the source of the driving transistor TRDrv becomes a voltage (Vth+Vofs−VSig_m) held by the capacitor unit CP. In addition, the driving voltage Vccp is applied to the source/drain region of one end of the driving transistor TRDrv, and therefore a current flows towards the light-emitting unit ELP through the driving transistor TRDrv and the fifth switching transistor TR5, which causes an electric potential of the third node ND3_S to increase. At this point of time, a phenomenon similar to that of so-called a bootstrap circuit occurs in the gate electrode of the driving transistor TRDrv. Basically, the electric potential of the first node ND1_G increases so as to maintain the voltage Vgs between the gate and the source.
In addition, the electric potential of the third node ND3_S increases, and exceeds (Vth-EL+Vcath), and therefore the light-emitting unit ELP starts light emission. At this point of time, a current flowing through the light-emitting unit ELP is the drain current Ids that flows from the drain region of the driving transistor TRDrv to the source region, and thus can be represented by equation (1). Here, Vgs is (Vth+Vofs−VSig_m), and therefore the drain current Ids can be represented as the following equation (2).
I
ds
=k·μ·(Vofs−VSig_m)2 (2)
Therefore, the current Ids flowing through the light-emitting unit ELP does not depend on the threshold voltage Vth of the driving transistor TRDrv. In other words, since the influence exerted by the dispersion in threshold voltage Vth of the driving transistor TRDrv of the display element 11 is canceled, the uneven brightness is reduced.
[Time Period: Hm−1] (Refer to
This time period is a time period immediately before performing the next write processing. The voltage Vth is already held in the first capacitor CS1, and thus the operation corresponding to the above-described [time period: H′m−3] and [time period: H′m−2] is omitted.
More specifically, the second control line WS2m is switched to a high level, and the fifth control line WS5m is switched to a low level. The second switching transistor TR2 is in the conducting state, and the other switching transistors are in the non-conducting state.
The fifth switching transistor TR5 is in the non-conducting state, and therefore a current does not flow through the light-emitting unit ELP. Therefore, the light-emitting unit ELP switches off the light. In addition, the reference voltage Vofs is applied to the second node ND2, and therefore the electric potential of the second node ND2 decreases to become Vofs. The first node ND1_G is in a floating state, and therefore the electric potential of the first node ND1_G decreases according to the change in potential of the second node ND2. The first capacitor CS1 maintains a state in which the voltage Vth is held. Incidentally, the electric potential of the third node ND3_S further decreases from (Vth-EL+Vcath) to some extent.
[Time Period: H″m] (Refer to
The next frame starts from this time period. A video signal voltage VSig_m is supplied to the data line DTLn in accordance with this time period. In addition, during this time period, in a state in which a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv is held by the first capacitor CS1, the video signal voltage VSig_m is written to the second capacitor CS2 through the first switching transistor TR1 in the conducting state.
More specifically, the first control line WS1m is switched to the high level. The other control lines maintain the previous state. The first switching transistor TR1 and the second switching transistor TR2 enter the conducting state. The other switching transistors are in the non-conducting state.
In the immediately preceding [time period: H′m−1], the voltage Vth is held in the first capacitor CS1 in a state in which the electric potential of the second node ND2 is Vofs. Further, the video signal voltage VSig_m is applied to the third node ND3_S through the first switching transistor TR1 in the conducting state. The reference voltage Vofs is applied to the second node ND2, and therefore a voltage, for example, (Vofs−VSig_m), is held in the second capacitor CS2. As the result, the capacitor unit CP that includes the first capacitor CS1 and the second capacitor CS2 holds a voltage, for example, (Vth+Vofs−VSig_m)
[Time Period: H″m−1+] (Refer to
The next frame light emission period starts from this time period.
More specifically, the first control line WS1m and the second control line WS2m are switched to a low level, and the fifth control line WS5m is switched to a high level. The fifth switching transistor TR5 is in the conducting state, and the other switching transistors are in the non-conducting state. The specific operation is similar to the operation described in the above-described [time period: Hm+1], and therefore the description thereof will be omitted.
As described above, if the operation of holding the threshold voltage Vth in the first capacitor CS1 is performed in a certain frame, this operation can be omitted in a subsequent frame. Therefore, the power consumption can be further reduced while canceling the influence exerted by the dispersion in threshold voltage Vth of the driving transistor TRDrv.
It should be noted that the operation described in the [time period: H′m−3] to the [time period: H′m−1] may be performed, for example, once every two frames, or once every five to ten frames. From the viewpoint of reducing the power consumption, it is preferable to reduce a frequency of frames in which the operation of holding a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv in the first capacitor CS1 is performed. Meanwhile, the voltage held in the first capacitor CS1 changes due to leakage or the like. Therefore, from the viewpoint of, for example, reducing uneven brightness, it is preferable to maintain a certain level of frequency. A level of frequency may be set as appropriate according to, for example, specifications of the display device. The same applies to the other embodiments as described later.
The second embodiment also relates to the display device, the display device driving method, and the display element according to the present disclosure.
In the first embodiment, the initialization voltage Vini is supplied from the data line DTLn through the first switching transistor TR1. In contrast to this, in the second embodiment, the initialization voltage Vini is supplied from the electric supply line DS through the driving transistor TRDrv. The second embodiment mainly differs from the first embodiment in the above point.
With respect to a schematic diagram of a display device 2 according to the second embodiment, the display device 1 has only to be replaced with the display device 2 in
In the second embodiment, the data-line drive unit 21 supplies the video signal voltage Vsig to the data line DTLn. The power supply unit 22 supplies the initialization voltage Vini and the driving voltage Vccp to the electric supply line DS.
[Time Period: Before H′m−4] (Refer to
This time period is before the [time period H′m−3] shown in
[Time Period: H′m−3] (Refer to
Initialization processing is performed during this time period. In other words, by applying the reference voltage Vofs to the first node ND1_G, and by applying the initialization voltage Vini to the second node ND2 and the third node ND3_S, the voltage held by the capacitor unit CP is set so as to exceed the threshold voltage Vth of the driving transistor TRDrv.
More specifically, the voltage supplied to the electric supply line DSm is switched to the initialization voltage Vini. In addition, the third control line WS3m and the fourth control line WS4m are switched to a high level. The other control lines maintain the previous state. The third to fifth switching transistors TR3 to TR5 are in the conducting state. The first switching transistor TR1 and the second switching transistor TR2 are in the non-conducting state.
The second node ND2 and the third node ND3_S are in the conducting state through the third switching transistor TR3. The reference voltage Vofs is applied to the first node ND1_G through the fourth switching transistor TR4. The fifth switching transistor TR5 is in the conducting state.
The voltage Vgs between the gate and the source of the driving transistor TRDrv exceeds the threshold voltage Vth. Therefore, the initialization voltage Vini is applied from the electric supply line DSm to the third node ND3_S, and to the second node ND2 that is in the conducting state with the third node ND3_S, through the driving transistor TRDrv and the fifth switching transistor TR5. The voltage held by the capacitor unit CP becomes (Vofs−Vini), and exceeds the threshold voltage Vth of the driving transistor TRDrv. In addition, the electric potential of the third node ND3_S does not exceed (Vth-EL+Vcath), and therefore the light-emitting unit ELP switches off the light.
The operation after the [time period: H′m−2] shown in
The third embodiment also relates to the display device, the display device driving method, and the display element according to the present disclosure.
In the first and second embodiments described above, the driving transistor TRDrv and the light-emitting unit ELP are connected through the switching transistor. The electric power is also consumed by a current flowing through the switching transistor, and therefore, from the viewpoint of attempting to achieve the electric power saving of the display device, it is preferable to directly connect the driving transistor TRDrv to the light-emitting unit ELP. In the third embodiment, the driving transistor TRDrv and the light-emitting unit ELP are configured to be directly connected to each other.
A display device 3 is also provided with: the display unit 10 in which the display elements 11 are arranged; and the drive unit 20 for driving the display unit 10. In the second embodiment, the data-line drive unit 21 supplies the video signal voltage VSig to the data line DTL. The power supply unit 22 supplies the initialization voltage Vini and the driving voltage Vccp to the electric supply line DS.
The capacitor unit CP, the driving transistor TRDrv, and the first switching transistor TR1 in the display element 11 are configured in a similar manner to that described in the first embodiment, and therefore the description thereof will be omitted.
In the third embodiment as well, the drive unit 20 applies the reference voltage Vofs to the first node ND1_G, and applies the initialization voltage Vini to the second node ND2 and the third node ND3_S, thereby setting the voltage held by the capacitor unit CP so as to exceed the threshold voltage Vth of the driving transistor TRDrv. Subsequently, the drive unit 20 applies the reference voltage Vofs to the first node ND1_G, and applies the driving voltage Vccp to one source/drain region of the driving transistor TRDrv in a state in which the second node ND2 and the third node ND3_S electrically conduct with each other, so as to cause electric potentials of the second node ND2 and the third node ND3_S to get close to a voltage obtained by subtracting the threshold voltage Vth of the driving transistor TRDrv from the reference voltage Vofs, thereby causing a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv to be held in the first capacitor CS1.
In the third embodiment, the display element 11 is further provided with the second switching transistor TR2, the third switching transistor TR3, the fourth switching transistor TR4, and the fifth switching transistor TR5. In the second switching transistor TR2, a reference voltage Vofs is applied to one source/drain region, and the other source/drain region is connected to the second node ND2. In the third switching transistor TR3, the reference voltage Vofs is applied to one source/drain region, and the other source/drain region is connected to the first node ND1_G. The second node ND2 is connected to the other source/drain region of the driving transistor TRDrv and one end of the light-emitting unit ELP through the fourth switching transistor TR4. The third node ND3_S is connected to the other source/drain region of the driving transistor TRDrv and one end of the light-emitting unit ELP through the fifth switching transistor TR5. The third switching transistor TR3 is brought into the conducting state, which causes the reference voltage Vofs to be applied to the first node ND1_G. The initialization voltage Vini is supplied from the electric supply line DS, and is applied to the second node ND2 and the third node ND3_S through the fourth switching transistor TR4 and the fifth switching transistor TR5 that are in the conducting state.
Next, the operation of the display device 3 will be described with reference to the accompanying drawings.
[Time Period: Before H′m−4] (Refer to
This time period is before the [time period H′m−3] shown in
[Time Period: H′m−3] (Refer to
Initialization processing is performed during this time period. In other words, by applying the reference voltage Vofs to the first node ND1_G, and by applying the initialization voltage Vini to the second node ND2 and the third node ND3_S, the voltage held by the capacitor unit CP is set so as to exceed the threshold voltage Vth of the driving transistor TRDrv.
More specifically, the voltage supplied to the electric supply line DSm is switched to the initialization voltage Vini. In addition, the third to fourth control lines WS3m to WS4m are switched to a high level. The other control lines maintain the previous state. The third to fifth switching transistors TR3 to TR5 are in the conducting state. The first switching transistor TR1 and the second switching transistor TR2 are in the non-conducting state.
The reference voltage Vofs is applied to the first node ND1_G through the third switching transistor TR3. The voltage Vgs between the gate and the source of the driving transistor TRDrv exceeds the threshold voltage Vth. Therefore, the initialization voltage Vini is applied from the electric supply line DSm to the second node ND2 through the fourth switching transistor TR4. Similarly, the initialization voltage Vini is applied from the electric supply line DSm to the third node ND3_S through the fifth switching transistor TR5. The voltage held by the capacitor unit CP becomes (Vofs−Vini), and exceeds the threshold voltage Vth of the driving transistor TRDrv. In addition, the electric potential of the third node ND3_S does not exceed (Vth-EL+Vcath), and therefore the light-emitting unit ELP switches off the light.
[Time Period: H′m−2] (Refer to
Threshold voltage cancel processing is performed during this time period. In other words, by applying the reference voltage Vofs to the first node ND1_G, and by applying the driving voltage Vccp to one source/drain region of the driving transistor TRDrv in a state in which the second node ND2 and the third node ND3_S electrically conduct with each other, electric potentials of the second node ND2 and the third node ND3_S are caused to get close to a voltage obtained by subtracting the threshold voltage Vth of the driving transistor TRDrv from the reference voltage Vofs.
More specifically, the voltage supplied to the electric supply line DSm is switched to the driving voltage Vccp. The control lines maintain the previous state.
The reference voltage Vofs is applied to the first node ND1_G through the third switching transistor TR3. The voltage held by the capacitor unit CP exceeds the threshold voltage Vth of the driving transistor TRDrv, and therefore, through the driving transistor TRDrv, a current from the electric supply line DSm flows through the third node ND3_S. As the result, the electric potential of the third node ND3_S increases toward an electric potential obtained by subtracting the threshold voltage Vth of the driving transistor TRDrv from the reference voltage Vofs. The electric potential of the second node ND2 that is in the conducting state with the third node ND3_S also similarly increases (refer to
If this time period is sufficiently long, an electric potential difference between the gate electrode of the driving transistor TRDrv and the other source/drain region reaches Vth, and the driving transistor TRDrv enters the non-conducting state (refer to
Incidentally, for convenience of explanation, the explanation is made on the assumption that the driving transistor TRDrv is already in the non-conducting state during this time period. However, the present disclosure is not limited to this. A mode may be employed in which the time period ends before the electric potential difference between the gate electrode of the driving transistor TRDrv and the other source/drain region reaches Vth.
[Time Period: H′m−1] (Refer to
This time period is a time period immediately before performing the next write processing, and a time period for waiting for writing. The third control line WS3m and the fifth control line WS5m are switched to a low level. The other control lines maintain the previous state. The fourth switching transistor TR4 is in the conducting state, and the other switching transistors are in the non-conducting state. If the driving transistor TRDrv is already in the non-conducting state in the [time period: H′m−2], electric potentials of the first node ND1_G, the second node ND2 and the third node ND3_S do not substantially change (refer to
[Time Period: Hm] (Refer to
A video signal voltage VSig_m is supplied to the data line DTLn in accordance with this time period. In addition, during this time period, in a state in which a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv is held by the first capacitor CS1, the video signal voltage VSig_m is written to the second capacitor CS2 through the first switching transistor TR1 in the conducting state.
More specifically, the first control line WS1m and the second control line WS2m are switched to a high level. The other control lines maintain the previous state. The first switching transistor TR1 and the second switching transistor TR2 enter the conducting state. The other switching transistors are in the non-conducting state.
In the immediately preceding [time period: H′m−1], an electric potential of the first node ND1_G is Vofs, an electric potential of the second node ND2 is (Vofs−Vth), and the voltage Vth is held in the first capacitor CS1. When the second switching transistor TR2 enters the conducting state, the reference voltage Vofs is applied to the second node ND2. Therefore, the electric potential of the second node ND2 changes from (Vofs−Vth) to Vofs. Here, the third switching transistor TR3 is in the non-conducting state. Therefore, if an influence exerted by parasitic capacitance or the like can be ignored, the first capacitor CS1 maintains the previous state in which the voltage Vth is held. Therefore, the electric potential of the first node ND1_G becomes (Vofs+Vth) from Vofs. In addition, the video signal voltage VSig_m is applied to the third node ND3_S through the first switching transistor TR1 in the conducting state. The reference voltage Vofs is applied to the second node ND2, and therefore a voltage, for example, (Vofs−VSig_m), is held in the second capacitor CS2. As the result, the capacitor unit CP that includes the first capacitor CS1 and the second capacitor CS2 holds a voltage, for example, (Vth+Vofs−VSig_m).
[Time Period: Hm+1] (Refer to
A light emission period ranges from this time period until the starting period of a scanning period [time period: Hm−1] immediately before the scanning period H″m in the m-th row in the next frame.
More specifically, the first control line WS1m, the second control line WS2m, and the fourth control line WS4m are switched to a low level, and the fifth control line WS5m is switched to a high level. The third control line WS3m maintains the previous state. The fifth switching transistor TR5 is in the conducting state, and the other switching transistors are in the non-conducting state.
The fifth switching transistor TR5 is in the conducting state, and therefore the voltage Vgs between the gate and the source of the driving transistor TRDrv becomes a voltage (Vth+Vofs−VSig_m) held by the capacitor unit CP. In addition, the driving voltage Vccp is applied to the source/drain region of one end of the driving transistor TRDrv, and therefore a current flows towards the light-emitting unit ELP through the driving transistor TRDrv, which causes an electric potential of the third node ND3_S to increase. At this point of time, a phenomenon similar to that of so-called a bootstrap circuit occurs in the gate electrode of the driving transistor TRDrv. Basically, the electric potential of the first node ND1_G increases so as to maintain the voltage Vgs between the gate and the source.
In addition, the electric potential of the third node ND3_S increases, and exceeds (Vth-EL+Vcath), and therefore the light-emitting unit ELP starts light emission. As described in the first embodiment, the current Ids flowing through the light-emitting unit ELP is represented by the above-described equation (2), and therefore does not depend on the threshold voltage Vth of the driving transistor TRDrv. In other words, since the influence exerted by the dispersion in threshold voltage Vth of the driving transistor TRDrv of the display element 11 is canceled, the uneven brightness is reduced.
[Time Period: Hm−1] (Refer to
This time period is a time period immediately before performing the next write processing. The voltage Vth is already held in the first capacitor CS1, and thus the operation corresponding to the above-described [time period: H′m−3] and [time period: H′m−2] is omitted.
More specifically, the second control line WS2m is switched to a high level, and the fifth control line WS5m is switched to a low level. The second switching transistor TR2 is in the conducting state, and the other switching transistors are in the non-conducting state.
The reference voltage Vofs is applied to the second node ND2, and therefore the electric potential of the second node ND2 decreases to become Vofs. The first node ND1_G and the third node ND3_S are in the floating state, and therefore these electric potentials also decrease according to the change in potential of the second node ND2. The first capacitor CS1 maintains a state in which the voltage Vth is held.
[Time Period: H″m] (Refer to
The next frame starts from this time period. A video signal voltage VSig_m is supplied to the data line DTLn in accordance with this time period. In addition, during this time period, in a state in which a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv is held by the first capacitor CS1, the video signal voltage VSig_m is written to the second capacitor CS2 through the first switching transistor TR1 in the conducting state.
More specifically, the first control line WS1m is switched to the high level. The other control lines maintain the previous state. The first switching transistor TR1 and the second switching transistor TR2 are in the conducting state. The other switching transistors are in the non-conducting state.
In the immediately preceding [time period: H′m−1], the voltage Vth is held in the first capacitor CS1 in a state in which the electric potential of the second node ND2 is Vofs. Further, the video signal voltage VSig_m is applied to the third node ND3_S through the first switching transistor TR1 in the conducting state. The reference voltage Vofs is applied to the second node ND2, and therefore a voltage, for example, (Vofs−VSig_m), is held in the second capacitor CS2. As the result, the capacitor unit CP that includes the first capacitor CS1 and the second capacitor CS2 holds a voltage, for example, (Vth+Vofs−VSig_m)
[Time Period: H″m+1] (Refer to
The next frame light emission period starts from this time period.
More specifically, the first control line WS1m and the second control line WS2m are switched to a low level, and the fifth control line WS5m is switched to a high level. The fifth switching transistor TR5 is in the conducting state, and the other switching transistors are in the non-conducting state. The specific operation is similar to the operation described in the above-described [time period: Hm+1], and therefore the description thereof will be omitted.
As described above, in the third embodiment as well, if the operation of holding the threshold voltage Vth in the first capacitor CS1 is performed in a certain frame, this operation can be omitted in a subsequent frame. Therefore, the power consumption can be further reduced while canceling the influence exerted by the dispersion in threshold voltage Vth of the driving transistor TRDrv.
The fourth embodiment also relates to the display device, the display device driving method, and the display element according to the present disclosure.
The configuration of the display device becomes more complicated with the increase in the number of transistors that constitute the display element, and in the number of control lines. From the viewpoint of the electric power saving, cost reduction, or the like, it is preferable to reduce the number of transistors that constitute the display element. In addition, it is preferable to commonalize the control lines for controlling the transistors. In the third embodiment, the number of transistors and the number of control lines decrease in comparison with the first to third embodiments. In particular, the control lines are partially commonalized, and the second control line WS2 is omitted.
A display device 4 is also provided with: the display unit 10 in which the display elements 11 are arranged; and the drive unit 20 for driving the display unit 10. In the fourth embodiment, the data-line drive unit 21 supplies the video signal voltage Vsig and the initialization voltage Vini to the data line DTL. The power supply unit 22 supplies a driving voltage Vccp to the electric supply line DS.
The capacitor unit CP, the driving transistor TRDrv, and the first switching transistor TR1 in the display element 11 are configured in a similar manner to that described in the first embodiment, and therefore the description thereof will be omitted.
In the fourth embodiment, the drive unit 20 applies the reference voltage Vofs to the first node ND1_G, and applies the initialization voltage Vini to the second node ND2 and the third node ND3_S, thereby setting the voltage held by the capacitor unit CP so as to exceed the threshold voltage Vth of the driving transistor TRDrv. Subsequently, the drive unit 20 applies the driving voltage Vccp to one source/drain region of the driving transistor TRDrv in a state in which the reference voltage Vofs is applied to the first node ND1_G, so as to cause the electric potential of the third node ND3_S to get close to a voltage obtained by subtracting the threshold voltage Vth of the driving transistor TRDrv from the reference voltage Vofs, thereby causing a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv to be held in the first capacitor CS1.
In the fourth embodiment, the display elements 11 are each further provided with the second switching transistor TR2, the third switching transistor TR3, and the fourth switching transistor TR4. In the second switching transistor TR2, the initialization voltage Vini is applied to one source/drain region, and the other source/drain region is connected to the second node ND2. In the third switching transistor TR3, the reference voltage Vofs is applied to one source/drain region, and the other source/drain region is connected to the first node ND1_G. The other source/drain region of the driving transistor TRDrv is connected to one end of the light-emitting unit ELP through the fourth switching transistor TR4. The third switching transistor TR3 is brought into the conducting state, which causes the reference voltage Vofs to be applied to the first node ND1_G. The second switching transistor TR2 is brought into the conducting state, which causes the initialization voltage Vini to be applied to the second node ND2_G. The conducting state/non-conducting state of the second switching transistor TR2 is controlled by a control line in common with the first switching transistor TR1, that is to say, the first control line WS1.
Next, the operation of the display device 4 will be described with reference to the accompanying drawings.
[Time Period: Before H′m−4] (Refer to
This time period is before the [time period H′m−3] shown in
[Time Period: H′m−3] (Refer to
Initialization processing is performed during this time period. In other words, by applying the reference voltage Vofs to the first node ND1_G, and by applying the initialization voltage Vini to the second node ND2 and the third node ND3_S, the voltage held by the capacitor unit CP is set so as to exceed the threshold voltage Vth of the driving transistor TRDrv.
More specifically, the initialization voltage Vini is supplied to the data line DTLn. In addition, the first control line WS1m and the third control line WS3m are switched to a high level, and the fourth control line WS4m is switched to a low level. The first to third switching transistors TR1 to TR3 are in the conducting state. The fourth switching transistor TR4 is in the non-conducting state.
The fourth switching transistor TR4 is in the non-conducting state, and therefore a current flowing through the driving transistor TRDrv does not flow through the light-emitting unit ELP. The reference voltage Vofs is applied to the first node ND1_G through the third switching transistor TR3. The initialization voltage Vini is applied to the second node ND2 through the second switching transistor TR2. The initialization voltage Vini is applied from the data line DTLn to the third node ND3_S through the first switching transistor TR1. The voltage held by the capacitor unit CP becomes (Vofs−Vini), and exceeds the threshold voltage Vth of the driving transistor TRDrv. In addition, the electric potential of the third node ND3_S does not exceed (Vth-EL+Vcath), and therefore the light-emitting unit ELP maintains a non-lighting state.
[Time Period: H′m−2] (Refer to
Threshold voltage cancel processing is performed during this time period. In other words, the driving voltage Vccp is applied to one source/drain region of the driving transistor TRDrv in a state in which the reference voltage Vofs is applied to the first node ND1_G, so as to cause the electric potential of the third node ND3_S to get close to a voltage obtained by subtracting the threshold voltage Vth of the driving transistor TRDrv from the reference voltage Vofs, thereby causing a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv to be held in the first capacitor CS1.
More specifically, the first control line WS1m is switched to a low level, and the fourth control line WS4m is switched to a high level. The third control line WS3m maintains the previous state. The third switching transistor TR3 and the fourth switching transistor TR4 are in the conducting state. The first switching transistor TR1 and the second switching transistor TR2 are in the non-conducting state.
The reference voltage Vofs is applied to the first node ND1_G through the third switching transistor TR3. The voltage held by the capacitor unit CP exceeds the threshold voltage Vth of the driving transistor TRDrv, and therefore, through the driving transistor TRDrv, a current from the electric supply line DSm flows through the third node ND3_S. As the result, the electric potential of the third node ND3_S increases toward an electric potential obtained by subtracting the threshold voltage Vth of the driving transistor TRDrv from the reference voltage Vofs. (Refer to
If this time period is sufficiently long, an electric potential difference between the gate electrode of the driving transistor TRDrv and the other source/drain region reaches Vth, and the driving transistor TRDrv enters the non-conducting state (refer to
Incidentally, for convenience of explanation, the explanation is made on the assumption that the driving transistor TRDrv is already in the non-conducting state during this time period. However, the present disclosure is not limited to this. A mode may be employed in which the time period ends before the electric potential difference between the gate electrode of the driving transistor TRDrv and the other source/drain region reaches Vth.
If the change in potential of the third node ND3_S from the [time period: H′m−3] to the [time period: H′m−2] is represented as ΔVND3_S, the relationship among ΔVs, Vth, Vofs, and Vofs is represented by the following equation (3). In addition, if the change in potential of the second node ND2 during the same period is represented as ΔVND2, ΔVND2 is represented by the following equation (4).
V
th
=V
ofs
−V
ini
−ΔV
s (3)
ΔVND2=ΔVs·CS1/(CS1+CS2) (4)
Further, if the voltage held by the second capacitor CS2 is represented as Vth′, Vth′ is represented by the following equation (5).
V
th
′=V
ofs
−V
ini
−ΔV
ND2 (5)
As understood from the equation (3) and the equation (4), ΔVND2 is a voltage determined according to Vth. Therefore, a voltage corresponding to the threshold voltage Vth is held in the second capacitor CS2.
[Time Period: H′m−1] (Refer to
This time period is a time period immediately before performing the next write processing, and a time period for waiting for writing. The third control line WS3m and the fourth control line WS4m are switched to a low level, and the first control line WS1m maintains the previous state. The first to fourth switching transistors TR1 to TR4 are in the non-conducting state. If the driving transistor TRDrv is already in the non-conducting state in the [time period: H′m−2], electric potentials of the first node ND1_G, the second node ND2, and the third node ND3_S do not substantially change. It should be noted that this time period may be omitted.
[Time Period: Hm] (Refer to
A video signal voltage VSig_m is supplied to the data line DTLn in accordance with this time period. In addition, during this time period, in a state in which a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv is held by the first capacitor CS1, the video signal voltage VSig_m is written to the second capacitor CS2 through the first switching transistor TR1 in the conducting state.
More specifically, the first control line WS1m is switched to the high level. The other control lines maintain the previous state. The first switching transistor TR1 and the second switching transistor TR2 are in the conducting state. The other switching transistors are in the non-conducting state.
In the immediately preceding [time period: H′m−1], the electric potential of the first node ND1_G is Vofs, the electric potential of the third node ND3_S is (Vofs− Vth), and the voltage Vth′ is held by the first capacitor CS1. When the second switching transistor TR2 enters the conducting state, the reference voltage Vofs is applied to the second node ND2. Therefore, the electric potential of the second node ND2 changes from (Vofs−Vth′) to Vofs. Here, the third switching transistor TR3 is in the non-conducting state. Therefore, if an influence exerted by parasitic capacitance or the like can be ignored, the first capacitor CS1 maintains the previous state in which the voltage Vth′ is held. Therefore, the electric potential of the first node ND1_G becomes (Vofs+Vth′) from Vofs. In addition, the video signal voltage VSig_m is applied to the third node ND3_S through the first switching transistor TR1 in the conducting state. The reference voltage Vofs is applied to the second node ND2, and therefore a voltage, for example, (Vofs−VSig_m), is held in the second capacitor CS2. As the result, the capacitor unit CP that includes the first capacitor CS1 and the second capacitor CS2 holds a voltage, for example, (Vth′+Vofs−VSig_m).
[Time Period: Hm+1] (Refer to
A light emission period ranges from this time period until the starting period of a scanning period [time period: Hm−1] immediately before the scanning period H″m in the m-th row in the next frame.
More specifically, the first control line WS1m is switched to a low level, and the fourth control line WS4m is switched to a high level. The third control line WS3m maintains the previous state. The fourth switching transistor TR4 is in the conducting state, and the other switching transistors are in the non-conducting state.
The voltage Vgs between the gate and the source of the driving transistor TRDrv becomes a voltage (Vth′+Vofs−VSig_m) held by the capacitor unit CP. In addition, the driving voltage Vccp is applied to the source/drain region of one end of the driving transistor TRDrv, and therefore a current flows towards the light-emitting unit ELP through the driving transistor TRDrv, which causes an electric potential of the third node ND3_S to increase. At this point of time, a phenomenon similar to that of so-called a bootstrap circuit occurs in the gate electrode of the driving transistor TRDrv. Basically, the electric potential of the first node ND1_G increases so as to maintain the voltage Vgs between the gate and the source.
In addition, the electric potential of the third node ND3_S increases, and exceeds (Vth-EL+Vcath), and therefore the light-emitting unit ELP starts light emission. The current Ids flowing through the light-emitting unit ELP is represented by the following equation (6).
I
ds
=k·μ·(Vofs−VSig_m−(Vth−Vth′))2 (6)
Therefore, since the influence exerted by the dispersion in threshold voltage Vth of the driving transistor TRDrv of the display element 11 is canceled to some extent, the uneven brightness is reduced.
[Time Period: Hm−1] (Refer to
This time period is a time period immediately before performing the next write processing. The voltage Vth′ is already held in the first capacitor CS1, and thus the operation corresponding to the above-described [time period: H′m−3] and [time period: H′m−2] is omitted.
More specifically, the fourth control line WS4m is switched to a low level. The other control lines maintain the previous state. The first to fourth switching transistors TR1 to TR4 are in the non-conducting state.
The fourth switching transistor TR4 is in the non-conducting state, and therefore a current flowing through the driving transistor TRDrv does not flow through the light-emitting unit ELP. Therefore, the light-emitting unit ELP switches off the light. In addition, the electric potential of the third node ND3_S decreases to (Vth-EL+Vcath). The first node ND1_G and the second node ND2_S are in the floating state, and therefore these electric potentials also decrease according to the change in potential of the third node ND3_S. The first capacitor CS1 maintains a state in which the voltage Vth′ is held.
[Time Period: H″m] (Refer to
The next frame starts from this time period. A video signal voltage VSig_m is supplied to the data line DTLn in accordance with this time period. In addition, during this time period, in a state in which a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv is held by the first capacitor CS1, the video signal voltage VSig_m is written to the second capacitor CS2 through the first switching transistor TR1 in the conducting state.
More specifically, the first control line WS1m is switched to the high level. The other control lines maintain the previous state. The first switching transistor TR1 and the second switching transistor TR2 are in the conducting state. The other switching transistors are in the non-conducting state.
In the immediately preceding [time period: Hm−1], the voltage Vth′ is held in the first capacitor CS1. Further, the video signal voltage VSig_m is applied to the third node ND3_S through the first switching transistor TR1 in the conducting state. The reference voltage Vofs is applied to the second node ND2, and therefore a voltage, for example, (Vofs−VSig_m), is held in the second capacitor CS2. As the result, the capacitor unit CP that includes the first capacitor CS1 and the second capacitor CS2 holds a voltage, for example, (Vth′+Vofs−VSig_m).
[Time Period: H″m+1] (Refer to
The next frame light emission period starts from this time period.
More specifically, the first control line WS1m is switched to a low level, and the fourth control line WS4m is switched to a high level. The second control line WS2m maintains the previous state. The fourth switching transistor TR4 is in the conducting state, and the other switching transistors are in the non-conducting state. The specific operation is similar to the operation described in the above-described [time period: Hm+1], and therefore the description thereof will be omitted.
As described above, in the fourth embodiment as well, if the operation of holding the threshold voltage Vth in the first capacitor CS1 is performed in a certain frame, this operation can be omitted in a subsequent frame. Therefore, the power consumption can be further reduced while canceling the influence exerted by the dispersion in threshold voltage Vth of the driving transistor TRDrv.
Moreover, since the number of transistors that constitute the display element, and the number of control lines decrease, the fourth embodiment is also suitable for achieving high definition of the display device.
The fifth embodiment also relates to the display device, the display device driving method, and the display element according to the present disclosure.
The first to fourth embodiments described above each have the configuration in which when a voltage is held in the first capacitor CS1, the electric potential of the third node ND3_S is caused to get close to a voltage obtained by subtracting the threshold voltage Vth of the driving transistor TRDrv from the reference voltage Vofs. Meanwhile, the fifth embodiment has a configuration in which when a voltage is held in the first capacitor CS1, the electric potential of the first node ND1_G is caused to get close to an electric potential obtained by adding the threshold voltage Vth of the driving transistor TRDrv to the reference voltage Vofs.
A display device 5 is also provided with: the display unit 10 in which the display elements 11 are arranged; and the drive unit 20 for driving the display unit 10. In the fifth embodiment, the data-line drive unit 21 supplies the video signal voltage Vsig to the data line DTL. The power supply unit 22 supplies a driving voltage Vccp to the electric supply line DS.
The capacitor unit CP, the driving transistor TRDrv, and the first switching transistor TR1 in the display element 11 are configured in a similar manner to that described in the first embodiment, and therefore the description thereof will be omitted.
In the fifth embodiment, the drive unit 20 applies the reference voltage Vofs to the second node ND2 and the third node ND3_S, and supplies the driving voltage Vccp from the electric supply line DS in a state in which the first node ND1_G and one source/drain region of the driving transistor TRDrv electrically conduct with each other, thereby setting the voltage held by the capacitor unit CP so as to exceed the threshold voltage Vth of the driving transistor TRDrv. Subsequently, a connection between the electric supply line DS and the driving transistor TRDrv is interrupted in a state in which the reference voltage Vofs is applied to the second node ND2 and the third node ND3_S, so as to cause the electric potential of the first node ND1_G to get close to an electric potential obtained by adding the threshold voltage Vth of the driving transistor TRDrv to the reference voltage Vofs, thereby causing a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv to be held in the first capacitor CS1.
In the fifth embodiment, the display element 11 is further provided with the second switching transistor TR2, the third switching transistor TR3, the fourth switching transistor TR4, and the fifth switching transistor TR5. In the second switching transistor TR2, a reference voltage Vofs is applied to one source/drain region, and the other source/drain region is connected to the second node ND2. In the third switching transistor TR3, one source/drain region is connected to the second node ND2, and the other source/drain region is connected to the third node ND3_S. A connection between the first node ND1_G and one source/drain region of the driving transistor TRDrv is made through the fourth switching transistor TR4. A connection between the electric supply line DS and one source/drain region of the driving transistor TRDrv is made through the fifth switching transistor TR5. The reference voltage Vofs is applied to the second node ND2 and the third node ND3_S by bringing the second switching transistor TR2 and the third switching transistor TR3 into the conducting state. The first node ND1_G and one source/drain region of the driving transistor TRDrv are brought into the conducting state by bringing the fourth switching transistor TR4 into the conducting state. The connection between the electric supply line DS and the driving transistor TRDrv is interrupted by bringing the fifth switching transistor TR5 into the non-conducting state.
Next, the operation of the display device 5 will be described with reference to the accompanying drawings.
[Time Period: Before H′m−4] (Refer to
This time period is before the [time period H′m−3] shown in
[Time Period: H′m−3] (Refer to
Initialization processing is performed during this time period. In other words, the reference voltage Vofs is applied to the second node ND2 and the third node ND3_S, and the driving voltage Vccp is supplied from the electric supply line DSm in a state in which the first node ND1_G and one source/drain region of the driving transistor TRDrv electrically conduct with each other, thereby setting the voltage held by the capacitor unit CP so as to exceed the threshold voltage Vth of the driving transistor TRDrv.
More specifically, the second to fourth control lines WS2m to WS4m are switched to a high level. The other control lines maintain the previous state. The second to fifth switching transistors TR2 to TR5 are in the conducting state. The first switching transistor TR1 is in the non-conducting state.
The second node ND2 and the third node ND3_S are in the conducting state through the third switching transistor TR3. The reference voltage Vofs is applied to the second node ND2 and the third node ND3_S through the second switching transistor TR2. In addition, the driving voltage Vccp is applied from the electric supply line DSm to the first node ND1_G through the fourth switching transistor TR4. Therefore, the voltage held by the capacitor unit CP becomes (Vccp−Vofs), and exceeds the threshold voltage Vth of the driving transistor TRDrv.
Incidentally, the driving voltage Vccp is applied from the electric supply line DSm to one end of the light-emitting unit ELP through the fifth switching transistor TR5 and the driving transistor TRDrv. Therefore, it is also considered that the light-emitting unit ELP performs unintended light emission. However, one end of the light-emitting unit ELP is connected to the third node ND3_S, and therefore a path of a through current is formed through the fifth switching transistor TR5, the driving transistor TRDrv, the third switching transistor TR3, and the second switching transistor TR2. Taking the threshold voltage Vth-EL of the light-emitting unit ELP or the like into consideration, it is considered that a current generally flows through the path of the through current.
[Time Period: H′m−2] (Refer to
Threshold voltage cancel processing is performed during this time period. In other words, by interrupting the connection between the electric supply line DSm and the driving transistor TRDrv in a state in which the reference voltage Vofs is applied to the second node ND2 and the third node ND3_S, the electric potential of the first node ND1_G is caused to get close to an electric potential obtained by adding the threshold voltage Vth of the driving transistor TRDrv to the reference voltage Vofs.
More specifically, the fifth control line WS5m is switched to a low level. The other control lines maintain the previous state. The second to fourth switching transistors TR2 to TR4 are in the conducting state. The first switching transistor TR1 and the fifth switching transistor TR5 are in the non-conducting state.
The reference voltage Vofs is applied to the second node ND2 through the second switching transistor TR2, and the reference voltage Vofs is applied to the third node ND3_S through the second switching transistor TR2 and the third switching transistor TR3.
The fifth switching transistor TR5 is in the non-conducting state, and therefore the electric supply line DSm is electrically isolated from one source/drain region of the driving transistor TRDrv. The voltage Vgs between the gate and the source of the driving transistor TRDrv is the voltage (Vccp−Vofs) held by the capacitor unit CP, and exceeds the threshold voltage Vth. In addition, the first node ND1_G and one source/drain region of the driving transistor TRDrv electrically conduct with each other by the fourth switching transistor TR4. A current flows from the first node ND1_G through the driving transistor TRDrv, which causes the electric potential of the first node ND1_G to decrease (
If this time period is sufficiently long, an electric potential difference between the gate electrode of the driving transistor TRDrv and the other source/drain region reaches Vth, and the driving transistor TRDrv enters the non-conducting state (refer to
Incidentally, for convenience of explanation, the explanation is made on the assumption that the driving transistor TRDrv is already in the non-conducting state during this time period. However, the present disclosure is not limited to this. A mode may be employed in which the time period ends before the electric potential difference between the gate electrode of the driving transistor TRDrv and the other source/drain region reaches Vth.
[Time Period: H′m−1] (Refer to
This time period is a time period immediately before performing the next write processing, and a time period for waiting for writing. The third control line WS3m and the fourth control line WS4m are switched to a low level, and the other control lines maintain the previous state.
The second switching transistor TR2 is in the conducting state, and the first switching transistors TR1, the fourth switching transistor TR4, and the fifth switching transistor TR5 are in the non-conducting state. If the driving transistor TRDrv is already in the non-conducting state in the [time period: H′m−2], electric potentials of the first node ND1_G, the second node ND2, and the third node ND3_S do not substantially change. It should be noted that this time period may be omitted.
[Time Period: Hm] (Refer to
A video signal voltage VSig_m is supplied to the data line DTL in accordance with this time period. In addition, during this time period, in a state in which a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv is held by the first capacitor CS1, the video signal voltage VSig_m is written to the second capacitor CS2 through the first switching transistor TR1 in the conducting state.
More specifically, the first control line WS1m is switched to the high level. The other control lines maintain the previous state. The first switching transistor TR1 and the second switching transistor TR2 are in the conducting state. The other switching transistors are in the non-conducting state.
In the immediately preceding [time period: H′m−1], the electric potential of the first node ND1_G is (Vofs+th), the electric potential of the second node ND2 is Vofs, and the voltage Vth is held in the first capacitor CS1. The reference voltage Vofs is applied to the second node ND2 through the first switching transistor TR1. In addition, the video signal voltage VSig_m is applied to the third node ND3_S through the first switching transistor TR1. The reference voltage Vofs is applied to the second node ND2, and therefore a voltage, for example, (Vofs-VSig_m), is held in the second capacitor CS2. As the result, the capacitor unit CP that includes the first capacitor CS1 and the second capacitor CS2 holds a voltage, for example, (Vth+Vofs−VSig_m)
[Time Period: Hm+1] (Refer to
A light emission period ranges from this time period until the starting period of a scanning period [time period: Hm−1] immediately before the scanning period H″m in the m-th row in the next frame.
More specifically, the first control line WS1m and the second control line WS2m are switched to a low level, and the fifth control line WS5m is switched to a high level. The third control line WS3m and the fourth control line WS4m maintain the previous state. The fifth switching transistor TR5 is in the conducting state, and the other switching transistors are in the non-conducting state.
The voltage Vgs between the gate and the source of the driving transistor TRDrv becomes a voltage (Vth+Vofs−VSig_m) held by the capacitor unit CP. In addition, the driving voltage Vccp is applied to the source/drain region of one end of the driving transistor TRDrv, and therefore a current flows towards the light-emitting unit ELP through the driving transistor TRDrv, which causes an electric potential of the third node ND3s to increase. At this point of time, a phenomenon similar to that of so-called a bootstrap circuit occurs in the gate electrode of the driving transistor TRDrv. Basically, the electric potential of the first node ND1_G increases so as to maintain the voltage Vgs between the gate and the source.
In addition, the electric potential of the third node ND3s increases, and exceeds (Vth-EL+Vcath), and therefore the light-emitting unit ELP starts light emission. As described in the first embodiment, the current Ids flowing through the light-emitting unit ELP is represented by the above-described equation (2), and therefore does not depend on the threshold voltage Vth of the driving transistor TRDrv. In other words, since the influence exerted by the dispersion in threshold voltage Vth of the driving transistor TRDrv of the display element 11 is canceled, the uneven brightness is reduced.
[Time Period: Hm−1] (Refer to
This time period is a time period immediately before performing the next write processing. The voltage Vth is already held in the first capacitor CS1, and thus the operation corresponding to the above-described [time period: H′m−3] and [time period: H′m−2] is omitted.
More specifically, the second control line WS2m is switched to a high level, and the fifth control line WS5m is switched to a low level. The other control lines maintain the previous state. The second switching transistor TR2 is in the conducting state, and the other switching transistors are in the non-conducting state.
The reference voltage Vofs is applied to the second node ND2, and therefore the electric potential of the second node ND2 decreases to become Vofs. The first node ND1_G is in a floating state, and therefore the electric potential of the first node ND1_G decreases according to the change in potential of the second node ND2. The first capacitor CS1 maintains a state in which the voltage Vth is held. Incidentally, the electric potential of the third node ND3_S further decreases from (Vth-EL+Vcath) to some extent.
[Time Period: H″m] (Refer to
The next frame starts from this time period. A video signal voltage VSig_m is supplied to the data line DTLn in accordance with this time period. In addition, during this time period, in a state in which a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv is held by the first capacitor CS1, the video signal voltage VSig_m is written to the second capacitor CS2 through the first switching transistor TR1 in the conducting state.
More specifically, the first control line WS1m is switched to the high level. The other control lines maintain the previous state. The first switching transistor TR1 and the second switching transistor TR2 are in the conducting state. The other switching transistors are in the non-conducting state.
In the immediately preceding [time period: H′m−1], the voltage Vth is held in the first capacitor CS1 in a state in which the electric potential of the second node ND2 is Vofs. Further, the video signal voltage VSig_m is applied to the third node ND3_S through the first switching transistor TR1 in the conducting state. The reference voltage Vofs is applied to the second node ND2, and therefore a voltage, for example, (Vofs−VSig_m), is held in the second capacitor CS2. As the result, the capacitor unit CP that includes the first capacitor CS1 and the second capacitor CS2 holds a voltage, for example, (Vth+Vofs−VSig_m).
[Time Period: H″m+1] (Refer to
The next frame light emission period starts from this time period.
More specifically, the first control line WS1m and the second control line WS2m are switched to a low level, and the fifth control line WS5m is switched to a high level. The fifth switching transistor TR5 is in the conducting state, and the other switching transistors are in the non-conducting state. The specific operation is similar to the operation described in the above-described [time period: Hm+], and therefore the description thereof will be omitted.
As described above, in the fifth embodiment as well, if the operation of holding the threshold voltage Vth in the first capacitor CS1 is performed in a certain frame, this operation can be omitted in a subsequent frame. Therefore, the power consumption can be further reduced while canceling the influence exerted by the dispersion in threshold voltage Vth of the driving transistor TRDrv.
In addition, in the first to fourth embodiments, the initialization voltage Vini as well as the reference voltage Vofs is required. In the fifth embodiment, the initialization voltage Vini is not required. Accordingly, the fifth embodiment also has an advantage of being capable of reducing kinds of voltages supplied by the drive unit.
The sixth embodiment also relates to the display device, the display device driving method, and the display element according to the present disclosure.
The sixth embodiment mainly differs from the fifth embodiment in the operation of the [time period: H′m−3]. More specifically, a transistor is controlled so as not to form a path of a through current. With respect to a schematic diagram of a display device 6 according to the sixth embodiment, the display device 5 has only to be replaced with the display device 6 in
As with the fifth embodiment, the data-line drive unit 21 supplies the video signal voltage Vsig to the data line DTL. The power supply unit 22 supplies a driving voltage Vccp to the electric supply line DS.
The operation before the [time period: H′m−4] is similar to the operation described in the fifth embodiment, and therefore the description thereof will be omitted.
[Time Period: H′m−3] (Refer to
The first half of the initialization processing is performed during this time period. The second control line WS2m and the fourth control line WS4m are switched to a high level, and the other control lines maintain the previous state. The second switching transistor TR2 and the fifth switching transistor TR5 are in the conducting state. The other switching transistors are in the non-conducting state.
The reference voltage Vofs is applied to the second node ND2 through the second switching transistor TR2. In addition, the driving voltage Vccp is applied from the electric supply line DSm to the first node ND1_G through the fourth switching transistor TR4. The driving voltage Vccp is applied from the electric supply line DSm to one end of the light-emitting unit ELP through the fifth switching transistor TR5 and the driving transistor TRDrv.
A current flows through the light-emitting unit ELP, and unintended light emission occurs. The electric potential of the third node ND3_S exceeds (Vth-EL+Vcath), and becomes an electric potential corresponding to the light emission.
[Time Period: H′m−2] (Refer to
The latter half of the initialization processing and the threshold voltage cancel processing are performed during this time period. The third control line WS3m is switched to a high level, and the fifth control line WS5m is switched to a low level. The second to fourth switching transistors TR2 to TR4 are in the conducting state. The first switching transistor TR1 and the fifth switching transistor TR5 are in the non-conducting state.
The reference voltage Vofs is applied to the third node ND3_S through the second switching transistor TR2 and the third switching transistor TR3. In the starting period of this time period, an electric potential of the first node ND1_G is Vccp. Therefore, in the starting period of this time period, the voltage held by the capacitor unit CP becomes (Vofs−Vini), and exceeds the threshold voltage Vth of the driving transistor TRDrv.
The reference voltage Vofs is applied to the second node ND2 through the second switching transistor TR2, and the reference voltage Vofs is applied to the third node ND3_S through the second switching transistor TR2 and the third switching transistor TR3. The fifth switching transistor TR5 is in the non-conducting state, and therefore the electric supply line DSm is electrically isolated from one source/drain region of the driving transistor TRDrv. The voltage Vgs between the gate and the source of the driving transistor TRDrv is the voltage (Vccp−Vofs) held by the capacitor unit CP, and exceeds the threshold voltage Vth. In addition, the first node ND1_G and one source/drain region of the driving transistor TRDrv electrically conduct with each other by the fourth switching transistor TR4. A current flows from the first node ND1_G through the driving transistor TRDrv, which causes the electric potential of the first node ND1_G to decrease.
If this time period is sufficiently long, an electric potential difference between the gate electrode of the driving transistor TRDrv and the other source/drain region reaches Vth, and the driving transistor TRDrv enters the non-conducting state (refer to
The operation after the [time period: H′m−1] shown in
As with the fifth embodiment, the sixth embodiment also does not require the initialization voltage Vini, and therefore has the advantage of being capable of reducing kinds of voltages supplied by the drive unit. Further, the sixth embodiment also has the advantage of reducing a load of the element caused by the through current flowing through the transistor. It should be noted that since the contrast decreases due to unintended light emission, it is preferable that a time period during which the processing of the [time period: H′m−3] is performed be set to be short.
The seventh embodiment also relates to the display device, the display device driving method, and the display element according to the present disclosure.
The seventh embodiment mainly differs from the fifth embodiment in that the other source/drain region of the driving transistor TRDrv is connected to one end of the light-emitting unit ELP through the sixth switching transistor. This enables a through current to be prevented from flowing at the time of initialization.
A display device 7 is also provided with: the display unit 10 in which the display elements 11 are arranged; and the drive unit 20 for driving the display unit 10. As with the sixth embodiment, the data-line drive unit 21 supplies the video signal voltage Vsig to the data line DTL. The power supply unit 22 supplies a driving voltage Vccp to the electric supply line DS.
The capacitor unit CP, the driving transistor TRDrv, and the first switching transistor TR1 in the display element 11 are configured in a similar manner to that described in the first embodiment, and therefore the description thereof will be omitted. In addition, the second to fifth switching transistors TR2 to TR5 are configured in a similar manner to that described in the fifth embodiment, and therefore the description thereof will be omitted.
In the seventh embodiment, the display element 11 is further provided with a sixth switching transistor TR6. The other source/drain region of the driving transistor TRDrv is connected to one end of the light-emitting unit ELP through the sixth switching transistor TR6. The conducting state/non-conducting state of the sixth switching transistor TR6 is controlled by a signal of a sixth control line WS6.
Next, the operation of the display device 7 will be described with reference to the accompanying drawings.
[Time Period: Before H′m−4] (Refer to
This time period is before the [time period H′m−3] shown in
[Time Period: H′m−3] (Refer to
Initialization processing is performed during this time period. In other words, the reference voltage Vofs is applied to the second node ND2 and the third node ND3_S, and the driving voltage Vccp is supplied from the electric supply line DSm in a state in which the first node ND1_G and one source/drain region of the driving transistor TRDrv electrically conduct with each other, thereby setting the voltage held by the capacitor unit CP so as to exceed the threshold voltage Vth of the driving transistor TRDrv.
More specifically, the second to fourth control lines WS2m to WS4m are switched to a high level, and the sixth control line WS6m is switched to a low level. The other control lines maintain the previous state. The second to fifth switching transistors TR2 to TR5 are in the conducting state. The first switching transistor TR1 and the sixth switching transistor TR6 are in the non-conducting state.
The second node ND2 and the third node ND3_S are in the conducting state through the third switching transistor TR3. The reference voltage Vofs is applied to the second node ND2 and the third node ND3_S through the second switching transistor TR2. In addition, the driving voltage Vccp is applied from the electric supply line DSm to the first node ND1_G through the fourth switching transistor TR4. Therefore, the voltage held by the capacitor unit CP becomes (Vccp−Vofs), and exceeds the threshold voltage Vth of the driving transistor TRDrv.
In addition, the sixth switching transistor TR6 is in the non-conducting state, and therefore the light-emitting unit ELP is electrically isolated from the other source/drain region of the driving transistor TRDrv. Therefore, differently from the fifth embodiment, a through current does not flow.
[Time Period: H′m−2] (Refer to
Threshold voltage cancel processing is performed during this time period. In other words, by interrupting the connection between the electric supply line DSm and the driving transistor TRDrv in a state in which the reference voltage Vofs is applied to the second node ND2 and the third node ND3_S, the electric potential of the first node ND1_G is caused to get close to an electric potential obtained by adding the threshold voltage Vth of the driving transistor TRDrv to the reference voltage Vofs.
More specifically, the fifth control line WS5m is switched to a low level, and the sixth control line WS6m is switched to a high level. The other control lines maintain the previous state. The second switching transistor TR2, the third switching transistor TR3, the fourth switching transistor TR4, and the sixth switching transistor TR6 are in the conducting state. The first switching transistor TR1 and the fifth switching transistor TR5 are in the non-conducting state.
The reference voltage Vofs is applied to the second node ND2 through the second switching transistor TR2, and the reference voltage Vofs is applied to the third node ND3_S through the second switching transistor TR2 and the third switching transistor TR3.
The fifth switching transistor TR5 is in the non-conducting state, and therefore the electric supply line DSm is electrically isolated from one source/drain region of the driving transistor TRDrv. The voltage Vgs between the gate and the source of the driving transistor TRDrv is the voltage (Vccp−Vofs) held by the capacitor unit CP, and exceeds the threshold voltage Vth. In addition, the first node ND1_G and one source/drain region of the driving transistor TRDrv electrically conduct with each other by the fourth switching transistor TR4. A current flows from the first node ND1_G through the driving transistor TRDrv, which causes the electric potential of the first node ND1_G to decrease (
If this time period is sufficiently long, an electric potential difference between the gate electrode of the driving transistor TRDrv and the other source/drain region reaches Vth, and the driving transistor TRDrv enters the non-conducting state (refer to
Incidentally, for convenience of explanation, the explanation is made on the assumption that the driving transistor TRDrv is already in the non-conducting state during this time period. However, the present disclosure is not limited to this. A mode may be employed in which the time period ends before the electric potential difference between the gate electrode of the driving transistor TRDrv and the other source/drain region reaches Vth.
[Time Period: H′m−1] (Refer to
This time period is a time period immediately before performing the next write processing, and a time period for waiting for writing. The third control line WS3m, the fourth control line WS4m, and the sixth control line WS6m are switched to a low level, and the other control lines maintain the previous state. The second switching transistor TR2 is in the conducting state, and the other switching transistors are in the non-conducting state. If the driving transistor TRDrv is already in the non-conducting state in the [time period: H′m−2], electric potentials of the first node ND1_G, the second node ND2, and the third node ND3_S do not substantially change. It should be noted that this time period may be omitted.
[Time Period: Hm] (Refer to
A video signal voltage VSig_m is supplied to the data line DTLn in accordance with this time period. In addition, during this time period, in a state in which a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv is held by the first capacitor CS1, the video signal voltage VSig_m is written to the second capacitor CS2 through the first switching transistor TR1 in the conducting state.
More specifically, the first control line WS1m is switched to the high level. The other control lines maintain the previous state. The first switching transistor TR1 and the second switching transistor TR2 are in the conducting state. The other switching transistors are in the non-conducting state.
In the immediately preceding [time period: H′m−1], the electric potential of the first node ND1_G is (Vofs+Vth), the electric potential of the second node ND2 is Vofs, and the voltage Vth is held in the first capacitor CS1. The reference voltage Vofs is applied to the second node ND2 through the first switching transistor TR1. In addition, the video signal voltage VSig_m is applied to the third node ND3_S through the first switching transistor TR1. The reference voltage Vofs is applied to the second node ND2, and therefore a voltage, for example, (Vofs−VSig_m), is held in the second capacitor CS2. As the result, the capacitor unit CP that includes the first capacitor CS1 and the second capacitor CS2 holds a voltage, for example, (Vth+Vofs−VSig_m).
[Time Period: Hm+1] (Refer to
A light emission period ranges from this time period until the starting period of a scanning period [time period: Hm−1] immediately before the scanning period H″m in the m-th row in the next frame.
More specifically, the first control line WS1m and the second control line WS2m are switched to a low level, and the fifth control line WS5m and the sixth control line WS6m are switched to a high level. The third control line WS3m and the fourth control line WS4m maintain the previous state. The fifth switching transistor TR5 and the sixth switching transistor TR6 are in the conducting state, and the other switching transistors are in the non-conducting state.
The voltage Vgs between the gate and the source of the driving transistor TRDrv becomes a voltage (Vth+Vofs−VSig_m) held by the capacitor unit CP. In addition, the driving voltage Vccp is applied to the source/drain region of one end of the driving transistor TRDrv, and therefore a current flows towards the light-emitting unit ELP through the driving transistor TRDrv, which causes an electric potential of the third node ND3_S to increase. At this point of time, a phenomenon similar to that of so-called a bootstrap circuit occurs in the gate electrode of the driving transistor TRDrv. Basically, the electric potential of the first node ND1_G increases so as to maintain the voltage Vgs between the gate and the source.
In addition, the electric potential of the third node ND3_S increases, and exceeds (Vth-EL+Vcath), and therefore the light-emitting unit ELP starts light emission. As described in the first embodiment, the current Ids flowing through the light-emitting unit ELP is represented by the above-described equation (2), and therefore does not depend on the threshold voltage Vth of the driving transistor TRDrv. In other words, since the influence exerted by the dispersion in threshold voltage Vth of the driving transistor TRDrv of the display element 11 is canceled, the uneven brightness is reduced.
[Time Period: Hm−1] (Refer to
This time period is a time period immediately before performing the next write processing. The voltage Vth is already held in the first capacitor CS1, and thus the operation corresponding to the above-described [time period: H′m−3] and [time period: H′m−2] is omitted.
More specifically, the second control line WS2m is switched to a high level, and the sixth control line WS6m is switched to a low level. The other control lines maintain the previous state. The second switching transistor TR2 and the fifth switching transistor TR5 are in the conducting state, and the other switching transistors are in the non-conducting state.
The reference voltage Vofs is applied to the second node ND2, and therefore the electric potential of the second node ND2 decreases to become Vofs. The first node ND1_G is in a floating state, and therefore the electric potential of the first node ND1_G decreases according to the change in potential of the second node ND2. The first capacitor CS1 maintains a state in which the voltage Vth is held. Incidentally, the electric potential of the third node ND3_S further decreases from (Vth-EL+Vcath) to some extent.
[Time Period: H″m] (Refer to
The next frame starts from this time period. A video signal voltage VSig_m is supplied to the data line DTLn in accordance with this time period. In addition, during this time period, in a state in which a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv is held by the first capacitor CS1, the video signal voltage VSig_m is written to the second capacitor CS2 through the first switching transistor TR1 in the conducting state.
More specifically, the first control line WS1m is switched to the high level. The other control lines maintain the previous state. The first switching transistor TR1, the second switching transistor TR2, and the fifth switching transistor TR5 are in the conducting state. The other switching transistors are in the non-conducting state.
In the immediately preceding [time period: H′m−1], the voltage Vth is held in the first capacitor CS1 in a state in which the electric potential of the second node ND2 is Vofs. Further, the video signal voltage VSig_m is applied to the third node ND3_S through the first switching transistor TR1 in the conducting state. The reference voltage Vofs is applied to the second node ND2, and therefore a voltage, for example, (Vofs−VSig_m), is held in the second capacitor CS2. As the result, the capacitor unit CP that includes the first capacitor CS1 and the second capacitor CS2 holds a voltage, for example, (Vth+Vofs−VSig_m)
[Time Period: H″m+1] (Refer to
The next frame light emission period starts from this time period.
More specifically, the first control line WS1m and the second control line WS2m are switched to a low level, and the sixth control line WS6m is switched to a high level. The fifth switching transistor TR5 and the sixth switching transistor TR6 are in the conducting state, and the other switching transistors are in the non-conducting state. The specific operation is similar to the operation described in the above-described [time period: Hm+i], and therefore the description thereof will be omitted.
As with the fifth embodiment, the seventh embodiment also does require the initialization voltage Vini, and therefore has the advantage of being capable of reducing kinds of voltages supplied by the drive unit. In addition, a through current does not flow at the time of initialization.
The eighth embodiment also relates to the display device, the display device driving method, and the display element according to the present disclosure.
In comparison with the fifth embodiment, the eighth embodiment basically has a configuration in which the transistor that connects the first node ND1_G and the second node ND2 is omitted.
A display device 8 is provided with: the display unit 10 in which display elements 11 are arranged; and the drive unit 20 for driving the display unit 10. In the eighth embodiment, the data-line drive unit 21 supplies the video signal voltage Vsig and the initialization voltage Vini to the data line DTL. The power supply unit 22 supplies a driving voltage Vccp to the electric supply line DS.
The capacitor unit CP, the driving transistor TRDrv, and the first switching transistor TR1 in the display element 11 are configured in a similar manner to that described in the first embodiment, and therefore the description thereof will be omitted.
In the eighth embodiment as well, the drive unit 20 applies the reference voltage Vofs to the second node ND2 and the third node ND3_S, and supplies the driving voltage Vccp from the electric supply line DSm in a state in which the first node ND1_G and one source/drain region of the driving transistor TRDrv electrically conduct with each other, thereby setting the voltage held by the capacitor unit CP so as to exceed the threshold voltage Vth of the driving transistor TRDrv. Subsequently,
a connection between the electric supply line DSm and the driving transistor TRDrv is interrupted in a state in which the reference voltage Vofs is applied to the second node ND2 and the third node ND3_S, so as to cause the electric potential of the first node ND1_G to get close to an electric potential obtained by adding the threshold voltage Vth of the driving transistor TRDrv to the reference voltage Vofs, thereby causing a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv to be held in the first capacitor CS1.
In the eighth embodiment, the display elements 11 are each further provided with the second switching transistor TR2, the third switching transistor TR3, and the fourth switching transistor TR4. In the second switching transistor TR2, the reference voltage Vofs is applied to one source/drain region, and with respect to the other source/drain region, a connection is made through the third switching transistor TR3 between the first node ND1_G connected to the second node ND2 and one source/drain region of the driving transistor TRDrv. A connection between the electric supply line DSm and one source/drain region of the driving transistor TRDrv is made through the fourth switching transistor TR4. The reference voltage Vofs is supplied from the data line DTLn through the first switching transistor TR1, and is then applied to the first node ND1_G. The reference voltage Vofs is applied to the second node ND2 by bringing the second switching transistor TR2 into the conducting state. The first node ND1_G and one source/drain region of the driving transistor TRDrv are brought into the conducting state by bringing the third switching transistor TR3 into the conducting state. The connection between the electric supply line DSm and the driving transistor TRDrv is interrupted by bringing the fourth switching transistor TR4 into the non-conducting state.
Next, the operation of the display device 8 will be described with reference to the accompanying drawings.
[Time Period: Before H′m−4] (Refer to
This time period is before the [time period H′m−3] shown in
[Time Period: H′m−3] (Refer to
Initialization processing is performed during this time period. In other words, the reference voltage Vofs is applied to the second node ND2 and the third node ND3_S, and the driving voltage Vccp is supplied from the electric supply line DSm in a state in which the first node ND1_G and one source/drain region of the driving transistor TRDrv electrically conduct with each other, thereby setting the voltage held by the capacitor unit CP so as to exceed the threshold voltage Vth of the driving transistor TRDrv.
More specifically, the initialization voltage Vini is supplied to the data line DTLn. In addition, the first to third control lines WS1m to WS3m are switched to a high level. The fourth control line WS4m maintains the previous state. The first to fourth switching transistors TR1 to TR4 are in the conducting state.
The reference voltage Vofs is applied to the second node ND2 through the second switching transistor TR2. The reference voltage Vofs is applied from the data line DTLn to the third node ND3_S through the first switching transistor TR1. In addition, the driving voltage Vccp is applied from the electric supply line DSm to the first node ND1_G through the third switching transistor TR3 and the fourth switching transistor TR4. Therefore, the voltage held by the capacitor unit CP becomes (Vccp−Vofs), and exceeds the threshold voltage Vth of the driving transistor TRDrv.
Incidentally, the driving voltage Vccp is applied from the electric supply line DSm to one end of the light-emitting unit ELP through the fourth switching transistor TR4 and the driving transistor TRDrv. Therefore, it is also considered that the light-emitting unit ELP performs unintended light emission. However, one end of the light-emitting unit ELP is connected to the third node ND3_S, and therefore a path of a through current is formed through the fourth switching transistor TR4, the driving transistor TRDrv, and the first switching transistor TR1. Taking the threshold voltage Vth-EL of the light-emitting unit ELP or the like into consideration, it is considered that a current generally flows through the path of the through current.
[Time Period: H′m−2] (Refer to
Threshold voltage cancel processing is performed during this time period. In other words, by interrupting the connection between the electric supply line DSm and the driving transistor TRDrv in a state in which the reference voltage Vofs is applied to the second node ND2 and the third node ND3_S, the electric potential of the first node ND1_G is caused to get close to an electric potential obtained by adding the threshold voltage Vth of the driving transistor TRDrv to the reference voltage Vofs.
More specifically, the fourth control line WS4m is switched to a low level. The other control lines maintain the previous state. The first to third switching transistors TR1 to TR3 are in the conducting state. The fourth switching transistor TR4 is in the non-conducting state.
The reference voltage Vofs is applied to the second node ND2 through the second switching transistor TR2, and the reference voltage Vofs is applied to the third node ND3_S through the first switching transistor TR1.
The fourth switching transistor TR4 is in the non-conducting state, and therefore the electric supply line DSm is electrically isolated from one source/drain region of the driving transistor TRDrv. The voltage Vgs between the gate and the source of the driving transistor TRDrv is the voltage (Vp-Vofs) held by the capacitor unit CP, and exceeds the threshold voltage Vth. A current flows from the first node ND1_G through the driving transistor TRDrv, which causes the electric potential of the first node ND1_G to decrease (
If this time period is sufficiently long, an electric potential difference between the gate electrode of the driving transistor TRDrv and the other source/drain region reaches Vth, and the driving transistor TRDrv enters the non-conducting state (refer to
Incidentally, for convenience of explanation, the explanation is made on the assumption that the driving transistor TRDrv is already in the non-conducting state during this time period. However, the present disclosure is not limited to this. A mode may be employed in which the time period ends before the electric potential difference between the gate electrode of the driving transistor TRDrv and the other source/drain region reaches Vth.
[Time Period: H′m−1] (Refer to
This time period is a time period immediately before performing the next write processing, and a time period for waiting for writing. The first control line WS1m is switched to a low level, and the other control lines maintain the previous state. The second switching transistor TR2 is in the conducting state, and the other switching transistors are in the non-conducting state. If the driving transistor TRDrv is already in the non-conducting state in the [time period: H′m−2], electric potentials of the first node ND1_G, the second node ND2, and the third node ND3_S do not substantially change. It should be noted that this time period may be omitted.
[Time Period: Hm] (Refer to
A video signal voltage VSig_m is supplied to the data line DTLn in accordance with this time period. In addition, during this time period, in a state in which a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv is held by the first capacitor CS1, the video signal voltage VSig_m is written to the second capacitor CS2 through the first switching transistor TR1 in the conducting state.
More specifically, the first control line WS1m is switched to the high level. The other control lines maintain the previous state. The first switching transistor TR1 and the second switching transistor TR2 are in the conducting state. The other switching transistors are in the non-conducting state.
In the immediately preceding [time period: H′m−1], the electric potential of the first node ND1_G is (Vofs−Vth), the electric potential of the second node ND2 is Vofs, and the voltage Vth is held in the first capacitor CS1. The reference voltage Vofs is applied to the second node ND2 through the first switching transistor TR1. In addition, the video signal voltage VSig_m is applied to the third node ND3_S through the first switching transistor TR1. The reference voltage Vofs is applied to the second node ND2, and therefore a voltage, for example, (Vofs−VSig_m), is held in the second capacitor CS2. As the result, the capacitor unit CP that includes the first capacitor CS1 and the second capacitor CS2 holds a voltage, for example, (Vth+Vofs−VSig_m).
[Time Period: Hm+1] (Refer to
A light emission period ranges from this time period until the starting period of a scanning period [time period: Hm−1] immediately before the scanning period H″m in the m-th row in the next frame.
More specifically, the first control line WS1m and the second control line WS2m are switched to a low level, and the fourth control line WS4m is switched to a high level. The other control lines maintain the previous state. The fourth switching transistor TR4 is in the conducting state, and the other switching transistors are in the non-conducting state.
The voltage Vgs between the gate and the source of the driving transistor TRDrv becomes a voltage (Vth+Vofs−VSig_m) held by the capacitor unit CP. In addition, the driving voltage Vccp is applied to the source/drain region of one end of the driving transistor TRDrv, and therefore a current flows towards the light-emitting unit ELP through the driving transistor TRDrv, which causes an electric potential of the third node ND3s to increase. At this point of time, a phenomenon similar to that of so-called a bootstrap circuit occurs in the gate electrode of the driving transistor TRDrv. Basically, the electric potential of the first node ND1_G increases so as to maintain the voltage Vgs between the gate and the source.
In addition, the electric potential of the third node ND3s increases, and exceeds (Vth-EL+Vcath), and therefore the light-emitting unit ELP starts light emission. As described in the first embodiment, the current Ids flowing through the light-emitting unit ELP is represented by the above-described equation (2), and therefore does not depend on the threshold voltage Vth of the driving transistor TRDrv. In other words, since the influence exerted by the dispersion in threshold voltage Vth of the driving transistor TRDrv of the display element is canceled, the uneven brightness is reduced.
[Time Period: Hm−1] (Refer to
This time period is a time period immediately before performing the next write processing. The voltage Vth is already held in the first capacitor CS1, and thus the operation corresponding to the above-described [time period: H′m−3] and [time period: H′m−2] is omitted.
More specifically, the second control line WS2m is switched to a high level, and the fourth control line WS4m is switched to a low level. The other control lines maintain the previous state. The second switching transistor TR2 is in the conducting state, and the other switching transistors are in the non-conducting state.
The reference voltage Vofs is applied to the second node ND2, and therefore the electric potential of the second node ND2 decreases to become Vofs. The first node ND1_G is in a floating state, and therefore the electric potential of the first node ND1_G decreases according to the change in potential of the second node ND2. The first capacitor CS1 maintains a state in which the voltage Vth is held. Incidentally, the electric potential of the third node ND3_S further decreases from (Vth-EL+Vcath) to some extent.
[Time Period: H″m] (Refer to
The next frame starts from this time period. A video signal voltage VSig_m is supplied to the data line DTL in accordance with this time period. In addition, during this time period, in a state in which a voltage corresponding to the threshold voltage Vth of the driving transistor TRDrv is held by the first capacitor CS1, the video signal voltage VSig_m is written to the second capacitor CS2 through the first switching transistor TR1 in the conducting state.
More specifically, the first control line WS1m is switched to the high level. The other control lines maintain the previous state. The first switching transistor TR1 and the second switching transistor TR2 are in the conducting state. The other switching transistors are in the non-conducting state.
In the immediately preceding [time period: H′m−1], the voltage Vth is held in the first capacitor CS1 in a state in which the electric potential of the second node ND2 is Vofs. Further, the video signal voltage VSig_m is applied to the third node ND3_S through the first switching transistor in the conducting state. The reference voltage Vofs is applied to the second node ND2, and therefore a voltage, for example, (Vofs− VSig_m), is held in the second capacitor CS2. As the result, the capacitor unit CP that includes the first capacitor CS1 and the second capacitor CS2 holds a voltage, for example, (Vth+Vofs−VSig_m)
[Time Period: H″m+1] (Refer to
The next frame light emission period starts from this time period.
More specifically, the first control line WS1m and the second control line WS2m are switched to a low level, and the fourth control line WS4m is switched to a high level. The fourth switching transistor TR4 is in the conducting state, and the other switching transistors are in the non-conducting state. The specific operation is similar to the operation described in the above-described [time period: Hm+i], and therefore the description thereof will be omitted.
The embodiments of the present disclosure have been specifically described above. However, the present disclosure is not limited to the above-described embodiments, and various modifications based on the technical idea of the present disclosure can be made. For example, the numerical values, structures, substrates, materials, processes, and the like mentioned in the embodiments described above are merely examples, and numerical values, structures, substrates, materials, processes, and the like different from the above may be used as necessary.
Display Device According to Modified Examples
For example,
Explanation of Electronic Apparatus, and Others
The display device according to the present disclosure described above can be used as a display unit (display device) of an electronic apparatus in all fields, the display unit (display device) displaying a video signal input into the electronic apparatus, or a video signal generated in the electronic apparatus, as an image or a video. As an example, the display device according to the present disclosure can be used as, for example, a display unit including a television set, a digital still camera, a notebook-type personal computer, a mobile terminal device such as a portable telephone, a video camera, and a head-mounted display (head-mounted display) and the like.
The display device according to the present disclosure also includes a module-shaped display device having a sealed configuration. As an example, the module-shaped display device corresponds to a display module formed by sticking a facing part such as transparent glass on a pixel array part. It should be noted that the display module may be provided with a circuit unit, a flexible printed circuit (FPC), or the like that is used to input/output a signal or the like from the outside to the pixel array part. As a specific example of an electronic apparatus that uses the display device according to the present disclosure, a digital still camera and a head mounted display are presented below. However, the specific examples presented here is merely an example, and thus is not limited to this.
In addition, a monitor 314 is provided at the substantially center of the back surface of the camera body part 311. The upper part of the monitor 314 is provided with a viewfinder (finder eyepiece window) 315. The photographer looks into the viewfinder 315 to visually recognize an optical image of an object, the optical image being introduced from the photographic lens unit 312. This enables the photographer to perform composition determination.
The display device according to the present disclosure can be used as the viewfinder 315 of the lens-interchangeable single-lens reflex type digital still camera having the above-described configuration. In other words, the lens-interchangeable single-lens reflex type digital still camera according to the present example is manufactured by using the display device according to the present disclosure as the viewfinder 315.
The body part 512 is connected to the arm 513 and glasses 500. More specifically, an end part in the long-side direction of the body part 512 is joined to the arm 513, and one side of the side surface of the body part 512 is connected to the glasses 500 through a connection member. It should be noted that the body part 512 may be directly mounted to the head of a human body.
A control board used to control the operation of the see-through head mounted display 511 and a display unit are built into the body part 512. The arm 513 connects between the body part 512 and the lens tube 514, and supports the lens tube 514.
More specifically, the arm 513 is connected to both an end part of the body part 512 and an end part of the lens tube 514 to fix the lens tube 514. In addition, the arm 513 includes a built-in signal line for communicating data related to an image provided from the body part 512 to the lens tube 514.
Through an eyepiece, the lens tube 514 projects image light, which is provided from the body part 512 through the arm 513, toward eyes of a user who wears the see-through head mounted display 511. The display device according to the present disclosure can be used as the display unit of the body part 512 in this see-through head mounted display 511.
It should be noted that the present disclosure can also employ the following configurations.
[1]
A display device including: a display unit in which display elements are arranged; and a drive unit for driving the display unit, in which:
the display elements each include: a current-driven light-emitting unit; a capacitor unit including a first capacitor and a second capacitor; an n-channel driving transistor that causes a current corresponding to a voltage held by the capacitor unit to flow through the light-emitting unit; and a first switching transistor that writes a video signal voltage to the capacitor unit;
in the capacitor unit, one end of the first capacitor is connected to a gate electrode of the driving transistor to form a first node, the other end of the first capacitor is connected to one end of the second capacitor to form a second node, and the other end of the second capacitor is connected to one end of the light-emitting unit, and to the other source/drain region of the driving transistor to form a third node;
in the driving transistor, one source/drain region is connected to an electric supply line, and the other source/drain region is connected to the light-emitting unit;
in the first switching transistor, one source/drain region is connected to a data line, and the other source/drain region is connected to the third node; and
in a state in which the first capacitor holds a voltage corresponding to a threshold voltage of the driving transistor, the drive unit writes a video signal voltage to the second capacitor through the first switching transistor in a conducting state.
[2]
The display device set forth in the above-described [1], in which
the drive unit consecutively scans the display elements of the display unit, and
performs the operation of holding, in the first capacitor, a voltage corresponding to a threshold voltage of the driving transistor in a part of a plurality of consecutive frames.
[3]
The display device set forth in the above-described [1] or [2], in which
the drive unit applies a reference voltage to the first node, and applies an initialization voltage to the second node and the third node, to set a voltage held by the capacitor unit so as to exceed the threshold voltage of the driving transistor, and subsequently
applies the reference voltage to the first node, and applies the driving voltage to one source/drain region of the driving transistor in a state in which the second node and the third node electrically conduct with each other, so as to cause electric potentials of the second node and the third node to get close to a voltage obtained by subtracting the threshold voltage of the driving transistor from the reference voltage, consequently causing a voltage corresponding to the threshold voltage of the driving transistor to be held in the first capacitor.
[4]
The display device set forth in the above-described [3], in which:
the display elements each further include a second switching transistor, a third switching transistor, and a fourth switching transistor;
in the second switching transistor, the reference voltage is applied to one source/drain region, and the other source/drain region is connected to the second node;
in the third switching transistor, one source/drain region is connected to the second node, and the other source/drain region is connected to the third node;
in the fourth switching transistor, the reference voltage is applied to one source/drain region, and the other source/drain region is connected to the first node;
the reference voltage is applied to the first node by bringing the fourth switching transistor into the conducting state; and
the second node and the third node are brought into the conducting state by bringing the third switching transistor into the conducting state.
[5]
The display device set forth in the above-described [4], in which
the initialization voltage is supplied from the data line through the first switching transistor.
[6]
The display device set forth in the above-described [4], in which
the initialization voltage is supplied from the electric supply line through the driving transistor.
[7]
The display element set forth in the above-described [4], in which:
the display elements each further include a fifth switching transistor; and
the other source/drain region of the driving transistor is connected to one end of the light-emitting unit through the fifth switching transistor.
[8]
The display device set forth in the above-described [3], in which:
the display elements each further include a second switching transistor, a third switching transistor, a fourth switching transistor, and a fifth switching transistor;
in the second switching transistor, the reference voltage is applied to one source/drain region, and the other source/drain region is connected to the second node;
in the third switching transistor, the reference voltage is applied to one source/drain region, and the other source/drain region is connected to the first node;
the second node is connected to the other source/drain region of the driving transistor and one end of the light-emitting unit through the fourth switching transistor;
the third node is connected to the other source/drain region of the driving transistor and one end of the light-emitting unit through the fifth switching transistor;
the reference voltage is applied to the first node by bringing the third switching transistor into the conducting state; and
the initialization voltage is supplied from the electric supply line, and is applied to the second node and the third node through the fourth switching transistor and the fifth switching transistor that are in the conducting state.
[9]
The display device set forth in the above-described [1] or [2], in which
the drive unit applies a reference voltage to the first node, and applies an initialization voltage to the second node and the third node, to set a voltage held by the capacitor unit so as to exceed the threshold voltage of the driving transistor, and subsequently
applies the driving voltage to one source/drain region of the driving transistor in a state in which the reference voltage is applied to the first node, so as to cause an electric potential of the third node to get close to a voltage obtained by subtracting the threshold voltage of the driving transistor from the reference voltage, consequently causing a voltage corresponding to the threshold voltage of the driving transistor to be held in the first capacitor.
[10]
The display device set forth in the above-described [9], in which:
the display elements each further include a second switching transistor, a third switching transistor, and a fourth switching transistor;
in the second switching transistor, the initialization voltage is applied to one source/drain region, and the other source/drain region is connected to the second node;
in the third switching transistor, the reference voltage is applied to one source/drain region, and the other source/drain region is connected to the first node;
the other source/drain region of the driving transistor is connected to one end of the light-emitting unit through the fourth switching transistor;
the reference voltage is applied to the first node by bringing the third switching transistor into the conducting state;
the initialization voltage is applied to the second node by bringing the second switching transistor into the conducting state; and
a conducting state/a non-conducting state of the second switching transistor are controlled by a control line in common with the first switching transistor.
[11]
The display device set forth in the above-described [1], in which
the drive unit applies a reference voltage to the second node and the third node, and supplies a driving voltage from the electric supply line in a state in which the first node and one source/drain region of the driving transistor electrically conduct with each other, to set a voltage held by the capacitor unit so as to exceed a threshold voltage of the driving transistor, and subsequently
interrupts a connection between the electric supply line and the driving transistor in a state in which the reference voltage is applied to the second node and the third node, so as to cause an electric potential of the first node to get close to an electric potential obtained by adding the threshold voltage of the driving transistor to the reference voltage, consequently causing a voltage corresponding to the threshold voltage of the driving transistor to be held in the first capacitor.
[12]
The display device set forth in the above-described [11], in which:
the display elements each further include a second switching transistor, a third switching transistor, a fourth switching transistor, and a fifth switching transistor;
in the second switching transistor, the reference voltage is applied to one source/drain region, and the other source/drain region is connected to the second node;
in the third switching transistor, one source/drain region is connected to the second node, and the other source/drain region is connected to the third node;
a connection between the first node and one source/drain region of the driving transistor is made through the fourth switching transistor;
a connection between the electric supply line and one source/drain region of the driving transistor is made through the fifth switching transistor;
the reference voltage is applied to the second node and the third node by bringing the second switching transistor and the third switching transistor into the conducting state;
the first node and one source/drain region of the driving transistor are brought into the conducting state by bringing the fourth switching transistor into the conducting state; and
the connection between the electric supply line and the driving transistor is interrupted by bringing the fifth switching transistor into the non-conducting state.
[13]
The display element set forth in the above-described [12], in which:
the display elements each further include a sixth switching transistor; and
the other source/drain region of the driving transistor is connected to one end of the light-emitting unit through the sixth switching transistor.
[14]
The display device set forth in the above-described [11], in which:
the display elements each further include a second switching transistor, a third switching transistor, and a fourth switching transistor;
in the second switching transistor, the reference voltage is applied to one source/drain region, and the other source/drain region is connected to the second node;
a connection between the first node and one source/drain region of the driving transistor is made through the third switching transistor;
a connection between the electric supply line and one source/drain region of the driving transistor is made through the fourth switching transistor;
the reference voltage is supplied from the data line through the first switching transistor, and is applied to the first node, and the reference voltage is applied to the second node by bringing the second switching transistor into the conducting state;
the first node and one source/drain region of the driving transistor are brought into the conducting state by bringing the third switching transistor into the conducting state; and
the connection between the electric supply line and the driving transistor is interrupted by bringing the fourth switching transistor into the non-conducting state.
[15]
A method for driving a display device, the display device including: a display unit in which display elements are arranged; and a drive unit for driving the display unit, in which:
the display elements each include: a current-driven light-emitting unit; a capacitor unit including a first capacitor and a second capacitor; an n-channel driving transistor that causes a current corresponding to a voltage held by the capacitor unit to flow through the light-emitting unit; and a first switching transistor that writes a video signal voltage to the capacitor unit;
in the capacitor unit, one end of the first capacitor is connected to a gate electrode of the driving transistor to form a first node, the other end of the first capacitor is connected to one end of the second capacitor to form a second node, and the other end of the second capacitor is connected to one end of the light-emitting unit, and to the other source/drain region of the driving transistor to form a third node;
in the driving transistor, one source/drain region is connected to an electric supply line, and the other source/drain region is connected to the light-emitting unit;
in the first switching transistor, one source/drain region is connected to a data line, and the other source/drain region is connected to the third node; and in a state in which the first capacitor holds a voltage corresponding to a threshold voltage of the driving transistor, the drive unit writes a video signal voltage to the second capacitor through the first switching transistor in a conducting state.
[16]
A display element including: a current-driven light-emitting unit; a capacitor unit including a first capacitor and a second capacitor; an n-channel driving transistor that causes a current corresponding to a voltage held by the capacitor unit to flow through the light-emitting unit; and a first switching transistor that writes a video signal voltage to the capacitor unit;
in which:
in the capacitor unit, one end of the first capacitor is connected to a gate electrode of the driving transistor to form a first node, the other end of the first capacitor is connected to one end of the second capacitor to form a second node, and the other end of the second capacitor is connected to one end of the light-emitting unit, and to the other source/drain region of the driving transistor to form a third node;
in the driving transistor, one source/drain region is connected to an electric supply line, and the other source/drain region is connected to the light-emitting unit;
in the first switching transistor, one source/drain region is connected to a data line, and the other source/drain region is connected to the third node; and
in a state in which the first capacitor holds a voltage corresponding to a threshold voltage of the driving transistor, a video signal voltage is written to the second capacitor through the first switching transistor in a conducting state.
[17]
An electronic apparatus including a display device, in which:
the display device includes: a display unit in which display elements are arranged; and a drive unit for driving the display unit;
the display elements each include: a current-driven light-emitting unit; a capacitor unit including a first capacitor and a second capacitor; an n-channel driving transistor that causes a current corresponding to a voltage held by the capacitor unit to flow through the light-emitting unit; and a first switching transistor that writes a video signal voltage to the capacitor unit;
in the capacitor unit, one end of the first capacitor is connected to a gate electrode of the driving transistor to form a first node, the other end of the first capacitor is connected to one end of the second capacitor to form a second node, and the other end of the second capacitor is connected to one end of the light-emitting unit, and to the other source/drain region of the driving transistor to form a third node;
in the driving transistor, one source/drain region is connected to an electric supply line, and the other source/drain region is connected to the light-emitting unit;
in the first switching transistor, one source/drain region is connected to a data line, and the other source/drain region is connected to the third node; and in a state in which the first capacitor holds a voltage corresponding to a threshold voltage of the driving transistor, the drive unit writes a video signal voltage to the second capacitor through the first switching transistor in a conducting state.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-210650 | Oct 2015 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2016/073930 | 8/16/2016 | WO | 00 |
