Patent Application
20200098316
The present invention relates to display device drive methods, more specifically to a display device, such as an organic EL display device, which includes electro-optical elements driven by current, and a method for driving the same.
In recent years, organic EL (electroluminescent) display devices have been drawing attention and actively developed as thin display devices that achieve high image quality and low power consumption. In such an organic EL display device, pixel circuits, including organic EL elements, which are self-illuminating display elements driven by current, drive transistors, etc., are disposed in a matrix.
In Patent Document 1, a logic power supply voltage continues to be outputted for a power-off delay period in an OFF sequence initiated at the time when an organic EL display device is powered off, whereby a panel driver circuit, which is driven by the logic power supply voltage, is used to supply each pixel with preset black display data. Thus, it is possible to release electric charge remaining in the pixel, thereby erasing an afterimage appearing at the time of power off or an afterimage appearing on a display panel rebooted by turning power back on after power off.
Patent Document 1: Japanese Laid-Open Patent Publication No. 2014-71450
However, the pixel circuit of the organic EL display device described in Patent Document 1 does not include a data compensation circuit as provided in organic EL display devices to be described later in embodiments of the present invention in order to compensate for threshold voltage variations of drive transistors by means of diode connection. Accordingly, even when a drive method described in Patent Document 1 is applied to a pixel circuit with a diode-connected data compensation circuit, some electric charge remains in the pixel circuit at the time of power off, resulting in deterioration of transistors included in the pixel circuit or an afterimage appearing when another image is displayed on a display panel by turning the power back on after the power off.
Therefore, an objective of the present invention is to provide a display device drive method and a display device, both of which allow pixel circuits to be discharged without leaving electric charge in an OFF sequence performed for power off.
A first aspect of the present invention is directed to a method for driving an active-matrix display device for displaying an image by causing electro-optical elements to emit light, the display device including:
the pixel circuit includes:
an OFF sequence involved in powering off the display device includes:
According to a second aspect of the present invention, in the first aspect of the present invention,
transistors included in the pixel circuit are P-channel transistors, and
the second ground potential is less than or equal to a potential obtained by adding the threshold voltage of the drive transistor to the first ground potential.
According to a third aspect of the present invention, in the first aspect of the present invention,
transistors included in the pixel circuit are N-channel transistors, and
the second ground potential is greater than or equal to a potential obtained by subtracting the threshold voltage of the drive transistor from the first ground potential.
According to a fourth aspect of the present invention, in the first aspect of the present invention,
the initialization circuit includes an initialization line for supplying the first ground potential and an initialization transistor configured to electrically connect the initialization line and the first node, and
the initialization step includes:
According to a fifth aspect of the present invention, in the first aspect of the present invention,
the display device further includes a power supply configured to supply a power supply voltage to the electro-optical element, and
in the initialization step, the first ground potential is written to the first node at a time when the power supply voltage is stopped from being supplied to the electro-optical element.
According to a sixth aspect of the present invention, in the first aspect of the present invention,
the display device further includes a writing transistor configured to electrically connect the data line and the second node, and
the writing step includes:
According to a seventh aspect of the present invention, in the sixth aspect of the present invention,
the data compensation circuit includes:
the pixel circuit includes a third node connected to the first conductive terminal of the drive transistor, and
the writing step further includes:
According to an eighth aspect of the present invention, in the first aspect of the present invention,
the display device further includes a plurality of select/output circuits configured to select color data signals from among a plurality of color data signals for displaying color images and supply the selected color data signals respectively to the data lines, the plurality of color data signals being included in data signals that are supplied from the data line driver circuit and correspond to a plurality of primary colors,
the pixel circuits include a plurality of subpixel circuits configured to cause the electro-optical elements to emit light in accordance with the color data signals,
the initialization step includes simultaneously writing the first ground potential supplied through the initialization line to the first nodes of the subpixel circuits,
the writing step includes:
A ninth aspect of the present invention is directed to an active-matrix display device for displaying an image by causing electro-optical elements to emit light, the display device including:
the pixel circuit includes:
when the display device is powered off, the initialization circuit writes a first ground potential to the first node at some point during a period in which a black display potential corresponding to black display data is supplied to the data lines, the first ground potential initializing the potential on the first node, and
when the corresponding scanning line is activated, the data compensation circuit writes a second ground potential to the second node through the data line so as not to electrically connect the control terminal and the first conductive terminal.
In the first aspect, during an OFF sequence period in which the display device is powered off, the first node is set to the first ground potential. As a result, even when the second ground potential is supplied from the data line to the second conductive terminal of the drive transistor, the gate terminal of the drive transistor is not charged with a gate-to-source voltage. Accordingly, the display device is powered off with the gate terminal of the drive transistor being charged with the first ground potential. Therefore, since any electric charge in the pixel circuit is released and no electric charge remains in the pixel circuit at the end of the OFF sequence period, transistors included in the pixel circuit are kept from deteriorating, and no afterimage appears when another image is displayed by turning the power back on after the power off.
In the second aspect, since the transistors included in the pixel circuit are P-channel transistors and the second ground potential is less than or equal to a potential obtained by adding the threshold voltage of the drive transistor to the first ground potential, even when the second ground potential is supplied from the data line to the second conductive terminal of the drive transistor, the gate terminal of the drive transistor is not charged with the gate-to-source voltage. Thus, effects similar to those achieved by the first aspect can be achieved.
In the third aspect, since the transistors included in the pixel circuit are N-channel transistors and the second ground potential is greater than or equal to a potential obtained by subtracting the threshold voltage of the drive transistor from the first ground potential, even when the second ground potential is supplied from the data line to the second conductive terminal of the drive transistor, the gate terminal of the drive transistor is not charged with the gate-to-source voltage. Thus, effects similar to those achieved by the first aspect can be achieved.
In the fourth aspect, the potential with which to charge the initialization line is changed from the initialization potential to the first ground potential, and the first ground potential is written to the first node. Thus, the potential on the first node can be readily changed to the first ground potential, with the result that no electric charge remains in the pixel circuit after the OFF sequence period.
In the fifth aspect, the first ground potential is written to the first node at the time when the power supply voltage is stopped from being supplied to the electro-optical element, and therefore, the first node can be efficiently initialized.
In the sixth aspect, the drive transistor is in OFF state because of the first ground potential written to the first node. In this case, by rendering the writing transistor in ON state, the second ground potential is written from the data line to the second node connected to the second conductive terminal of the drive transistor and the second conductive terminal of the writing transistor. Thus, the drive transistor can more reliably be maintained in OFF state, with the result that no electric charge remains in the pixel circuit after the OFF sequence period.
In the seventh aspect, the drive transistor is in OFF state because of the first ground potential written to the first node. Accordingly, by rendering the compensation transistor in ON state, the first ground potential written to the first node is also written to the third node connected to the first conductive terminal of the drive transistor and the first conductive terminal of the compensation transistor. Thus, the drive transistor can more reliably be maintained in OFF state, with the result that no electric charge remains in the pixel circuit after the OFF sequence period.
In the eighth aspect, the display device includes the select/output circuits that select color data signals from among a plurality of color data signals for displaying color images and supply the selected color data signals respectively to the data lines, the plurality of color data signals being included in data signals that correspond to a plurality of primary colors; during the OFF sequence period in which the display device is powered off, initially, first nodes of all subpixel circuits are simultaneously set to the first ground potential. Next, the second ground potential is supplied from the data line sequentially to the second conductive terminals of the drive transistors for respective subpixel circuits. In this case, as in the first aspect, the gate terminals of the drive transistors are not charged with the gate-to-source voltage, and therefore, the display device is powered off with the gate terminals of the drive transistors being charged with the first ground potential. Thus, any electric charge in each subpixel circuit is released and no electric charge remains in the subpixel circuit at the end of the OFF sequence period, whereby the transistors included in the subpixel circuit are kept from deteriorating, and no afterimage appears when another image is displayed by turning the power back on after the power off.
The ninth aspect renders it possible to achieve effects similar to those achieved by the first aspect.
Before describing an organic EL display device according to the present embodiment, an organic EL display device in which data compensation circuits in pixel circuits are diode-connected circuits will be described with respect to the principle of transistor deterioration and afterimage appearance due to electric charge remaining in the pixel circuits in the course of an OFF sequence. Note that unless otherwise specified, transistors will be described herein as being of P-channel type, but the transistors are not limited to P-channel type and may be of N-channel type. Moreover, in the present embodiment, the transistors are, but are not limited to, for example, thin-film transistors (TFTs). The P-channel transistor is rendered in ON state when a low-level potential is supplied at a gate terminal, and in OFF state when a high-level potential is supplied.
The drive transistor T1 has a gate terminal (also referred to as a “control terminal”), a first conductive terminal, and a second conductive terminal; the first conductive terminal is connected to a third node N3, and the second conductive terminal is connected to a second node N2. In the case of the drive transistor T1, the first conductive terminal and the second conductive terminal respectively serve as a drain terminal and a source terminal, or vice versa, depending on carrier flow. For example, a data voltage supplied from a data line Dj is provided through the writing transistor T2, the drive transistor T1, and the compensation transistor T3 to the gate terminal of the drive transistor T1. In this case, the first conductive terminal of the drive transistor T1 serves as a drain terminal, and the second conductive terminal serves as a source terminal.
The pixel circuit 11 is connected to a scanning line Sj(also referred to as a “current scanning line”), a scanning line Sj-1 (also referred to as a “preceding scanning line”) immediately preceding the current scanning line Sj, an emission line Ej, the data line Dj, a high-level power line ELVDD, a low-level power line ELVSS, and an initialization line Vini. Note that the high-level power line ELVDD is a power line for supplying a high-level potential ELVDD, the low-level power line ELVSS is a power line for supplying a low-level potential ELVSS, and the initialization line Vini is a power line for supplying an initialization potential Vini.
In the pixel circuit 11, the writing transistor T2 has a gate terminal connected to the current scanning line Sj, a first conductive terminal connected to the data line Dj as a source terminal, and a second conductive terminal connected to the second node N2 as a drain terminal. The writing transistor T2 writes a data voltage with which the data line Dj is being charged, to the pixel circuit 11 in response to the current scanning line Sj being selected.
The source terminal, which is the second conductive terminal of the drive transistor T1, is connected by the second node N2 to the drain terminal, which is the second conductive terminal of the writing transistor T2. The drive transistor T1 supplies the organic EL element OLED with a drive current I in accordance with a gate-to-source voltage Vgs via the emission control transistor T6 to be described later.
The compensation transistor T3 is provided between the gate terminal and the first conductive terminal of the drive transistor T1, and has a first conductive terminal connected by the third node N3 to the first conductive terminal of the drive transistor T1. In the pixel circuit 11, the compensation transistor T3 has a gate terminal connected to the current scanning line Sj. When the compensation transistor T3 is rendered in ON state in response to the current scanning line Sj being selected, the compensation transistor T3 diode-connects the drive transistor T1 by connecting the gate terminal and the first conductive terminal of the drive transistor T1.
The initialization transistor T4 is provided between the gate terminal of the drive transistor T1 and the initialization line Vini and has a gate terminal connected to the preceding scanning line SjI. When the initialization transistor T4 is rendered in ON state in response to the preceding scanning line Sj-1 being selected, a potential on a first node N1, which connects a drain terminal of the initialization transistor T4 and the gate terminal of the drive transistor T1, is set to the initialization potential Vini. As a result, the initialization potential Vini is supplied to the gate terminal of the drive transistor T1.
The power supply transistor T5 is provided between the high-level power line ELVDD and the first conductive terminal of the drive transistor T1, and has a gate terminal connected to the emission line Ej When the power supply transistor T5 is rendered in ON state in response to the emission line Ej being selected, the drive transistor T1 is supplied with the high-level potential ELVDD at the second conductive terminal.
The emission control transistor T6 is provided between the drive transistor T1 and the organic EL element OLED, and has a gate terminal connected to the emission line Ej. When the emission control transistor T6 is rendered in ON state in response to the emission line Ej being selected, the emission control transistor T6 supplies the drive current I to the organic EL element OLED.
The capacitor C has a first terminal connected to the gate terminal of the drive transistor T1 and a second terminal connected to the high-level power line ELVDD. The capacitor C holds a gate voltage Vg of the drive transistor T1 when the current scanning line Sj connected to the pixel circuit 11, including the capacitor C, is deselected, whereby the compensation transistor T3 is rendered in OFF state.
The organic EL element OLED has an anode (a terminal of the organic EL element OLED) connected to a second conductive terminal of the emission control transistor T6 and a cathode (the other terminal of the organic EL element OLED) connected to the low-level power line ELVSS. The organic EL element OLED emits light with a luminance in accordance with the drive current I supplied by the drive transistor T1.
First, the initialization period will be described. At time t1, the preceding scanning line Sj-1 experiences a change in potential from high level to low level. As a result, a low-level voltage is supplied to the gate terminal of the initialization transistor T4, whereby the initialization transistor T4 is rendered in ON state. Accordingly, the initialization potential Vini, which is lower than the ground potential Vgnd, is supplied to the first node N1 from the initialization line Vini through the initialization transistor T4, whereby the first node N1 is charged with the initialization potential Vini. At time t2, the preceding scanning line Sj-1 experiences a change in potential from low level to high level, whereby the initialization transistor T4 is rendered in OFF state. In this manner, an initialization circuit 41, including the initialization transistor 14, is operated during the initialization period. In this case, since the potential on the current scanning line Sj is high-level, the data compensation circuit 42, including the compensation transistor T3 and the capacitor C, is not operated, and the data line Dj is set at the ground potential Vgnd.
Next, the writing period will be described. At time t3, the current scanning line Sj experiences a change in potential from high level to low level. As a result, the writing transistor T2 and the compensation transistor T3 are rendered in ON state. Moreover, the data line Dj is set at the ground potential Vgnd. Accordingly, the ground potential Vgnd on the data line Dj is written to the first node N1 via the writing transistor T2, the drive transistor T1, and the compensation transistor T3. In this case, the gate-to-source voltage Vgs on the drive transistor T1 is lower than the ground potential Vgnd on the source terminal by a threshold voltage Vth of the drive transistor T1. Accordingly, the potential on the first node N1 connected to the gate terminal of the drive transistor T1 does not rise from the initialization potential Vini to as high as the ground potential Vgnd, but only to a potential lower than the ground potential Vgnd by the threshold voltage Vth.
As a result, electric charge held in the capacitor C is not completely released, so that the organic EL display device is powered off, leaving some electric charge unreleased. In this case, the ground potential Vgnd provided through the data line Dj is written to the second node N2, which connects the second conductive terminal of the drive transistor T1 and the second conductive terminal of the writing transistor T2, and also written to the third node N3, which connects the first conductive terminal of the drive transistor T1 and the first conductive terminal of the compensation transistor T3. Accordingly, when the organic EL display device is powered off, the electric charge remaining in the capacitor C is left unreleased and might cause deterioration of the drive transistor T1 and/or an afterimage appearing on a display part 10 when the power is turned back on.
In this manner, the potential on the first node N1 connected to the gate terminal of the drive transistor T1 is initialized to the initialization potential Vini by the initialization circuit 41 during the initialization period. Thereafter, the data compensation circuit 42 performs potential compensation, and therefore, even when an attempt is made to write the ground potential Vgnd, with which the data line Dj is being charged, to the first node N1 in order to set the potential on the first node N1 to the ground potential Vgnd, the potential on the first node N1 only rises to a value lower than the ground potential Vgnd by the threshold voltage Vth. Therefore, there is a problem in that the capacitor C holds an electric charge corresponding to the threshold voltage Vth, and the charge is left unreleased even after the OFF sequence period.
Therefore, embodiments will be described below with reference to drive methods which keep any electric charge from remaining in the first node N1 after the OFF sequence period.
Hereinafter, a first embodiment of the present invention will be described with reference to the accompanying drawings.
The organic EL display device 1 is an active-matrix display device including a display part 10, a display control circuit 20, a data driver 30, a scan driver 50, and an emission driver 60, as shown in
The display part 10 has provided therein m (where m is an integer of 2 or more) data lines D1 to Dm and n scanning lines S1 to Sn crossing the data lines. The display part 10 has also provided therein (m×n) pixel circuits 11 corresponding to intersections of the data lines D1 to Dm and the scanning lines S1 to Sn. The display part 10 has n emission lines E1 to En provided parallel to the n scanning lines S1 to Sn and serving as control lines. The m data lines D1 to Dm are connected to the data driver 30, and the n scanning lines S1 to Sn are connected to the scan driver 50. The n emission lines E1 to En are connected to the emission driver 60.
The display part 10 has power lines provided in common to the pixel circuits 11. More specifically, provided is a power line for supplying a high-level potential ELVDD for driving organic EL elements to be described later, and also a power line for supplying a low-level potential ELVSS for driving the organic EL elements. There is also provided an initialization line Viini for supplying an initialization potential Vini for an initialization operation to be described later. These potentials are respectively supplied by a first power supply 15 and a second power supply 16. In the present embodiment, the high-level power line ELVDD supplies the high-level potential ELVDD, and the low-level power line ELVSS supplies the low-level potential ELVSS.
Furthermore, there are m data capacitors Cd1 to Cdm respectively connected at one terminal to the m data lines D1 to Dm and grounded at the other terminal (not connected to the data lines Dj) so as to hold the data signals provided to the data lines Dj.
The display control circuit 20 outputs various control signals to the data driver 30, the scan driver 50, and the emission driver 60. More specifically, the display control circuit 20 outputs a data start pulse DSP, a data clock DCK, display data DA, and a latch pulse LP to the data driver 30. Moreover, the display control circuit 20 outputs a gate start pulse SSP and a gate clock SCK to the scan driver 50 and an emission start pulse EMSP and an emission clock EMCK to the emission driver 60.
The data driver 30 includes unillustrated elements such as an m-bit shift register, a sampling circuit, a latch circuit, and m D/A converters. The shift register has m bistable circuits cascaded to each other, and transfers the data start pulse DSP supplied to the first stage sequentially to subsequent stages in synchronization with the data clock DCK, with the result that sampling pulses are outputted from the stages. Concurrently with the outputting of each sampling pulse, the sampling circuit is supplied with display data DA. The sampling circuit memorizes the display data DA in accordance with the sampling pulse. Once the sampling circuit memorizes the display data DA for one row, the display control circuit 20 outputs a latch pulse LP to the latch circuit. Upon reception of the latch pulse LP, the latch circuit holds the display data DA memorized in the sampling circuit. The D/A converters are provided corresponding to the m data lines D1 to Dm respectively connected to m output terminals (not shown) of the data driver 30, in order to supply the data lines D1 to Dm with data signals, which are analog signals converted from the display data DA held in the latch circuit by the D/A converters.
The scan driver 50 drives the n scanning lines S1 to Sn. More specifically, the scan driver 50 includes unillustrated elements such as a shift register and a buffer. The shift register sequentially transfers gate start pulses SSP in synchronization with a gate clock SCK. Scanning signals, which are outputs from stages of the shift register, are sequentially supplied to corresponding current scanning lines Sj (where j=1 to n) via the buffer. The m pixel circuits 11 connected to the current scanning line Sj are collectively selected by an active scanning signal (in the present embodiment, a “low-level scanning signal”). Note that the scanning signal supplied to the current scanning line Sj will also be referred to as the current scanning signal, and the scanning signal supplied to the preceding scanning line Sj-1 will also be referred to as the preceding scanning signal.
The emission driver 60 drives the n emission lines E1 to En. More specifically, the emission driver 60 includes unillustrated elements such as a shift register and a buffer. The shift register sequentially transfers emission start pulses EMSP in synchronization with an emission clock EMCK. Emission signals, which are outputs from stages of the shift register, are supplied to corresponding emission lines Ej via the buffer.
The configuration of the pixel circuit 11 in the organic EL display device 1 according to the present embodiment is the same as the configuration of the pixel circuit 11 described in the basic study and shown in
First, the initialization period will be described. At time t1, the preceding scanning line Sj-1 experiences a change in potential from the ground potential Vgnd to low level. As a result, the gate terminal of the initialization transistor T4 is supplied with a low-level voltage, whereby the initialization transistor T4 is rendered in ON state. Moreover, at a time (not shown) when the organic EL display device is provided with a power-off command, the initialization line Vini experiences a change in potential from low level to the first ground potential Vgnd1, i.e., high level. As a result, unlike in the basic study, the first ground potential Vgnd1, which is a potential higher than the initialization potential Vini, is supplied from the initialization line Vini to the first node N1 via the initialization transistor T4 in ON state.
At time t2, the preceding scanning line Sj-1 experiences a change in potential from low level to high level. Note that since the potential on the current scanning line Sj is high-level, as in the basic study, the data compensation circuit 42 is not operated, and the data line Dj is set at the second ground potential Vgnd2.
Next, the writing period will be described. At time t3, the current scanning line Sj experiences a change in potential from high level to low level. Moreover, the data line Dj is set at the second ground potential Vgnd2. Accordingly, the writing transistor T2 is rendered in ON state, and the second ground potential Vgnd2 is written from the data line Dj to the second node N2 connected to both the source terminal, which is the second conductive terminal of the drive transistor T1, and the drain terminal, which is the second conductive terminal of the writing transistor T2. On the other hand, the first node N1 connected to the gate terminal of the drive transistor T1 is set at the first ground potential Vgnd1. Therefore, to keep the threshold voltage Vth from being compensated for by the data compensation circuit 42, the following formula (1) needs to be established.
V
gnd1
+V
th
≥V
gnd2 (1)
In the case where formula (1) is established, the first node N1 is not set to the gate-to-source voltage Vgs represented by equation (2) below and remains at the first ground potential Vgnd1, whereby the drive transistor T1 remains in OFF state. Accordingly, the data compensation circuit 42 does not compensate for threshold voltage, and the first node N1 remains at the first ground potential Vgnd1.
V
gs
=V
gnd2
−V
th (2)
Furthermore, at time t3, since the current scanning line Sj is set to low level, the compensation transistor T3 has a low-level voltage at the gate terminal. Accordingly, the compensation transistor T3 is rendered in ON state. As a result, through the compensation transistor T3, the first ground potential Vgnd1 with which the first node N1 has been charged during the initialization period is supplied to the third node N3, which is a connecting point between the first conductive terminal of the drive transistor T1 and the first conductive terminal of the compensation transistor T3, with the result that the third node N3 is set to the first ground potential Vgnd1 as well. In this manner, the first node N1 and the third node N3 in the pixel circuit 11 are set at the first ground potential Vgnd1, and the second node N2 is set at the second ground potential Vgnd2, whereby the organic EL display device 1 will not be powered off with any electric charge remaining in the pixel circuit 11. Thus, no electric charge remains in the pixel circuit, whereby the transistors included in the pixel circuit 11 are kept from deteriorating and no afterimage appears when the display part 10 displays another image by turning power back on after power off.
Once the organic EL display device 1 is powered off and the OFF sequence period starts at time t0, the potential of an image signal is switched to a black display potential. As a result, the black display potential is applied to charge the first node N1 through the data line Dj, the writing transistor T2, the drive transistor T1, and the compensation transistor T3, whereby the first node N1 is set at the black display potential as well. During the initialization period from time t0 to time t3 and the writing period from time t3 to time t5, a high-level power line of the organic EL display device 1 maintains a high-level potential ELVDD, and a low-level power line ELVSS maintains a low-level potential ELVSS.
During the period from time t1 to time t2, the high-level power line ELVDD, which supplies a power supply potential to the organic EL element OLED of each pixel circuit 11, experiences a change in potential from the high-level potential ELVDD to the ground potential Vgnd or floating state, and the low-level power line ELVSS experiences a change in potential from the low-level potential ELVSS to the ground potential Vgnd or floating state. Concurrently with this, the initialization potential Vini on the initialization line Vini is changed from low level to the first ground potential Vgnd1.
During the period from time t2 to time t3, the data driver 30 provides the data line Dj with a black display potential, which corresponds to a black display data signal for causing the display part 10 to display an entirely black screen, with the result that the data line Dj is charged with the black display potential, which is written to the first node N1 via the writing transistor T2, the drive transistor T1, and the compensation transistor T3. Moreover, at time t2, the initialization potential Vini is set to the first ground potential Vgnd1. At time t3, the potential of the black display data signal changes to the second ground potential Vgnd2, thereby keeping the gate-to-source voltage Vgs from being written to the gate terminal of the drive transistor T1, with the result that the gate terminal remains at the first ground potential Vgnd1, and the drive transistor T1 is rendered in OFF state. In this manner, the drive transistor T1 is rendered in OFF state by changing the initialization potential Vini from low level to the first ground potential Vgnd1, i.e., high level, at the time when the high-level potential ELVDD and the low-level potential ELVSS are changed to the ground potential Vgnd or floating state. In the foregoing, the initialization potential Vini on the initialization line Vini is changed from low level to the first ground potential Vgnd1 during the period from time t1 to time t2, but this is not limiting, and such a change may occur during any period, for example, the period from time t0 to time t1 or from time t2 to time t3, so long as the image signal is set at the black display potential during that period.
It should be noted that the gate start pulse SSP and the gate clock SCK intended for driving the scan driver 50 and the emission start pulse EMSP and the emission clock EMCK intended for driving the emission driver 60 continue to be outputted until time t4, and therefore, the data driver 30, the scan driver 50, and the emission driver 60 are operated until time t4.
Next, the operation of the organic EL display device 1 during the period from time t5 to time t7 will be described. During the period from time t5 to time t6, each of the high-level potential GVDD from the high-level power supply of the organic EL display device 1 and the low-level potential GVSS from the low-level power is changed to the ground potential Vgnd. Moreover, during the period from time t5 to time t6, each of the gate start pulse SSP, the gate clock SCK, the emission start pulse EMSP, and the emission clock EMCK is changed from high or low level to the ground potential Vgnd.
In the basic study, the initialization potential Vini on the initialization line Vini is changed from low level to the first ground potential Vgnd1 during the period from time t5 to time t6. However, in the present embodiment, as has already been described, the initialization potential Vini is changed from low level to high level during the period from time t1 to time t2 within the initialization period. Accordingly, in the present embodiment, the first ground potential Vgnd1 with which the first node N1 has been charged during the initialization period keeps the drive transistor T1 in OFF state, and therefore, no electric charge remains in the pixel circuit 11.
In the present embodiment, during the OFF sequence period, the first node N1 is set to the first ground potential Vgnd1, which is a potential higher than the initialization potential Vini. As a result, even when the second ground potential Vgnd2 is supplied from the data line Dj to the second conductive terminal of the drive transistor T1, the gate terminal of the drive transistor T1 is not charged with the gate-to-source voltage Vgs. Therefore, the organic EL display device 1 is powered off with the gate terminal of the drive transistor T1 being charged with the first ground potential Vgnd1. Thus, no electric charge remains in the pixel circuit 11 after the power off, whereby the transistors included in the pixel circuit 11 are kept from deteriorating and no afterimage appears when the display part 10 displays another image by turning the power back on after the power off.
In the embodiment, all of the six transistors included in the pixel circuit 11 are of P-channel type, but the transistors may be of N-channel type. Accordingly, the present variant will be described with respect to the case where all of the six transistors included in the pixel circuit are of N-channel type. In this case, the general configuration of the organic EL display device is the same as in the embodiment, and the pixel circuit is the same as the pixel circuit 11 shown in
First, the initialization period will be described. At time t1, the preceding scanning line Sj-1 experiences a change in potential from low level to high level. As a result, the gate terminal of the initialization transistor T4 is supplied with a high-level voltage, whereby the initialization transistor T4 is rendered in ON state. Moreover, at a time (not shown) when the organic EL display device is provided with a power-off command, the initialization line Vini experiences a change in potential from high level to the first ground potential Vgnd1, i.e., low level. As a result, the first ground potential Vgnd1 from the initialization line Vini is written to the first node N1 via the initialization transistor T4 in ON state. At time t2, the preceding scanning line Sj-1 experiences a change in potential from high level to low level. In this manner, during the initialization period, the initialization circuit 41 is operated, thereby charging the first node N1 with the first ground potential Vgnd1. Note that since the current scanning line Sj is at low level, the data compensation circuit 42 is not operated, and the data line Dj is set at the second ground potential Vgnd2.
Next, the writing period will be described. At time t3, the current scanning line Sj experiences a change in potential from low level to high level. Moreover, the data line Dj is at the second ground potential Vgnd2. Accordingly, the writing transistor T2 is rendered in ON state, and the second ground potential Vgnd2 from the data line Dj is written to the second node N2 connected to the second conductive terminal of the drive transistor T1 and the second conductive terminal of the writing transistor T2.
On the other hand, the first node N1 connected to the gate terminal of the drive transistor T1 is at the first ground potential Vgnd1. Therefore, to keep any changes of the threshold voltage Vth from being compensated for by the data compensation circuit 42, the following formula (3) needs to be established, given the drive transistor T1 is of N-channel type.
V
gnd1
−V
th
≤V
gnd2 (3)
In the case where formula (3) is established, the first node N1 is not set to the gate-to-source voltage Vgs represented by formula (4) below and remains at the first ground potential Vgnd1, with the result that the drive transistor T1 remains in OFF state. Accordingly, the data compensation circuit 42 does not compensate for any changes of the threshold voltage Vth, and the first node N1 remains at the first ground potential Vgnd1.
V
gs
=V
gnd2
+V
th (4)
Furthermore, at time t3, the current scanning line Sj experiences a change from low level to high level, and therefore, the compensation transistor T3 has also a high-level voltage at the gate terminal. Accordingly, the compensation transistor T3 is rendered in ON state. As a result, the first ground potential Vgnd1 with which the first node N1 has been charged during the initialization period is supplied to the third node N3, which is a connecting point between the first conductive terminal of the drive transistor T1 and the first conductive terminal of the compensation transistor T3, via the compensation transistor T3, with the result that the third node N3 is set to the first ground potential Vgnd1 as well. In this manner, each of the first node N1 and the third node N3 in the pixel circuit 11 is set to the first ground potential Vgnd1, and the second node N2 is set to the second ground potential Vgnd2, whereby the organic EL display device 1 will not be powered off with any electric charge remaining in the pixel circuit 11. Thus, no electric charge remains in the pixel circuit after the organic EL display device is powered off, whereby the transistors included in the pixel circuit 11 are kept from deteriorating, and no afterimage appears when the display part 10 displays another image by turning the power back on after the power off.
The display part 10 has m data lines D1 to Dm disposed along with n scanning lines S1 to Sn, and n emission lines E1 to En. The demultiplexing part 40 includes m demultiplexers (also referred to as “select/output circuits”) 431 to 43m, which are respectively connected to the m data lines D1 to Dm. Note that since the display part 10, the display control circuit 20, the data driver 30, the scan driver 50, and the emission driver 60 are configured in the same manner as in
The selection transistors Tr, Tg, and Tb included in the demultiplexer 43j respectively select an R data signal Rj, a G data signal Gj, and a B data signal Bj. When a gate terminal of the selection transistor Tr is provided with a selection control signal ASWr from the display control circuit 20 simultaneously with an R data signal Rj being provided through the data line Dj, the selection transistor Tr is rendered in ON state and supplies the R data signal Rj to the R data line Drj. When a gate terminal of the selection transistor Tg is provided with a selection control signal ASWg from the display control circuit 20 simultaneously with a G data signal Gj being provided through the data line Dj, the selection transistor Tg supplies the G data signal Gj to the G data line Dgj. When a gate terminal of the selection transistor Tb is provided with a selection control signal ASWb from the display control circuit 20 simultaneously with a B data signal Bj being provided through the data line Dj, the selection transistor Tb supplies the B data signal B to the B data line Dbj.
Similarly, for each horizontal period, the other demultiplexers supply R data signals to R data lines, G data signals to G data lines, and B data signals to B data lines. In this manner, by using the demultiplexers 431 to 43m, it is rendered possible to reduce the number of output terminals of the data driver 30, thereby reducing the cost of producing the data driver 30. Note that the number of selection transistors included in the demultiplexer 43j in
The R data line Dj is connected to n R subpixel circuits 11r, and R data signals sequentially supplied through the R data line Drj are sequentially written to the n R subpixel circuits 11r. The G data line Dgj is connected to n G subpixel circuits 11g, and G data signals sequentially supplied through the G data line Dgj are sequentially written to the n G subpixel circuits 11g. The B data line Db is connected to n B subpixel circuits 11b, and B data signals sequentially supplied through the B data line Dbj are sequentially written to the n B subpixel circuits 11b.
During the period from time t3 to time t4, simultaneously with an R data signal Rj being supplied to the data line Dj, a data control signal Aswr experiences a change in potential from high level to low level, thereby rendering the selection transistor Tr in ON state. As a result, the selection transistor Tr selects and writes the R data signal Rj to the data line Drj. During the period from time t5 to time t6, simultaneously with a G data signal Gj being supplied to the data line Dj, a data control signal Aswg experiences a change in potential from high level to low level, thereby rendering the selection transistor Tg in ON state. As a result, the selection transistor Tg selects and writes the G data signal Gj to the data line Dgj. During the period from time t7 to time t8, simultaneously with a B data signal Bj being supplied to the data line Dj, a data control signal Aswb experiences a change in potential from low level to high level, thereby rendering the selection transistor Tb in ON state. As a result, the selection transistor Tb selects and writes the B data signal Bj to the data line Dbj. In this manner, the data signals Rj, Gj, and Bj are respectively written to the data lines Drj, Dgj, and Dbj.
During the period from time t9 to time t10, the current scanning line Sj experiences a change in potential from high level to low level, thereby rendering the writing transistor T2 in each of the subpixel circuits 11r, 11g, and 11b in ON state. As a result, the second ground potential Vgnd2 as below is simultaneously written to the second node N2 in each of the subpixel circuits 11r, 11g, and 11b. More specifically, the second ground potential Vgnd2 written to the R data line Drj during the period from time t3 to time t4 is written to the second node N2 of the R subpixel circuit 11r, the second ground potential Vgnd2 written to the G data line Dgj during the period from time t5 to time t6 is written to the second node N2 of the G subpixel circuit 11g, and the second ground potential Vgnd2 written to the B data line Dbj during the period from time t7 to time t8 is written to the second node N2 of the B subpixel circuit 11b.
Furthermore, at time t9, since the current scanning line Sj is set to low level, the compensation transistor T3 has a low-level voltage at the gate terminal. Accordingly, the compensation transistor T3 in each of the subpixel circuits 11r, 11g, and 11b is rendered in ON state. As a result, the first ground potential Vgnd1 with which the first node N1 of each of the subpixel circuits 11r, 11g, and 11b has been charged during the initialization period is supplied to the third node N3, which is a connecting point between the first conductive terminal of the drive transistor T1 and the first conductive terminal of the compensation transistor T3, via the compensation transistor T3. Consequently, the third node N3 of each of the subpixel circuits 11r, 11g, and 11b is set to the first ground potential Vgnd1.
In the present embodiment, since the first node N1 and the third node N3 in each of the subpixel circuits 11r, 11g, and 11b are set at the first ground potential Vgnd1, and the second node N2 is set at the second ground potential Vgnd2, the organic EL display device 1 is not powered off with any electric charge remaining in the subpixel circuits 11r, 11g, and 11b. Thus, since no electric charge remains in the pixel circuit when the organic EL display device is powered off, the transistors included in the pixel circuit 11 are kept from deteriorating, and no afterimage appears when the display part 10 displays another image by turning the power back on after the power off.
The displays described herein are not limited to display panels with organic EL elements OLED, and may be display panels with electro-optical elements whose luminance and/or transmittance are controlled by current. Examples of displays with such current-controlled electro-optical elements include EL displays, such as organic EL displays with organic light-emitting diodes (OLEDs) and inorganic EL displays with inorganic light-emitting diodes, and QLED displays with quantum-dot light-emitting diodes.
1 display device
10 display part
11 pixel circuit
11
r, 11g, 11b subpixel circuit
15 first power supply
16 second power supply
20 display control circuit
30 data driver (data line driver circuit)
40 demultiplexing part
50 scan driver (scanning line driver circuit)
60 emission driver (control line driver circuit)
Dj output line
Sj scanning line
Ej emission line (control line)
T1 to T6 transistor
C capacitor (capacitive element)
ELVDD high-level power line
ELVSS low-level power line
Vini initialization line
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2017/011348 | 3/22/2017 | WO | 00 |
