Patent Application
20060050031
The entire disclosure of Japanese Patent Applications Nos. 2004-258593 and 2004-258594, including their specifications, claims, drawings, and abstracts, is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a display-device driving circuit, and more particularly to a driving circuit for an inorganic electroluminescence (EL) display device.
2. Description of the Related Art
Inorganic electroluminescence (EL) display devices are a type of know flat-panel display device. The display plane of a typical inorganic EL display device is composed of a plurality of row-electrode lines Lrow that are each consecutively arranged in parallel with one another on an insulating substrate, a high-dielectric-constant film formed on the top surface of the row-electrode lines Lrow, an intermediate layer, a phosphor layer, and an intermediate layer that are provided in that order on the high-dielectric-constant film, inorganic-EL luminous body layers that are elongated in the direction perpendicular to the row-electrode lines Lrow and are each periodically arranged in parallel with one another, and a plurality of linear column-electrode lines Lcol that are each arranged in parallel with one another on the inorganic-EL luminous body layer. The row-electrode lines Lrow and the column-electrode lines Lcol are connected to a row driver 10 and a column driver 12, respectively.
An inorganic EL display device can be represented by an equivalent circuit such as that illustrated in
A driving circuit corresponding to each pixel in an inorganic EL display device is disclosed. As illustrated in
In addition, the voltage drop through the transistors 58 and 60 is the same as the sum of the threshold voltage VT of the transistors 58 and the threshold voltage VT of the transistor 60 that are the same as the threshold voltage VT of the transistors 64 and the threshold voltage VT of the transistor 66, respectively. As a result, the output of the driving circuit 50 does not have any “dead band”.
In a driving circuit described above, because the output voltage VOUT is from 0 to 80 V and has a fixed polarity, the electric-potential difference between the voltage Vrow and the output voltage VOUT, which is applied across each pixel, always has the same polarity over an electric-potential range from the maximal electric-potential difference ΔVMAX to the minimal electric-potential difference ΔVMIN. As described above, a one-side drive method causes a problem in that continual application of a voltage with a fixed polarity to an EL element causes a problem greatly reduces the lifetime of the EL element.
Moreover, if, in order to control the output voltage VOUT through one-side drive with a fixed polarity, a necessary resolution is to be provided, the time required for control will greatly increase. For example, if the output voltage VOUT Of 0 to 80 V is to be controlled with a resolution of steps, the pulse width of the PWM signal 72 as a basis should be created in accordance with the resolution of steps. Accordingly, the logic circuit 52 should create PWM signals, while counting with a counter or the like the resolution of 0 to 256. As a result, the time required for counting is great, making high-speed control difficult to achieve.
In addition, in the conventional driving circuit 50 described above, when a certain external fluctuation is added to the output voltage VOUT, the high-frequency components of the external fluctuation directly affect the capacitor 68 through the parasitic capacitance C between the source and the gate of the transistor 64. As a result, a problem results in that the accumulated voltage across the capacitor 68 is susceptible to the effects of fluctuations.
The present invention provides a display-device driving circuit in which, by creating a driving voltage that corresponds to a certain gradation for making a luminescence element emit light, and by supplying a luminescence element with the driving voltage, the luminescence element is made to emit light, the display-device driving circuit characterized by including a circuit that, when receiving gradation data that indicates a gradation for making a luminescence element emit light, generates an output voltage greater than or equal to the ground potential, when the gradation indicated by the gradation data is greater than or equal to a predetermined threshold value, and that generates an output voltage smaller than the ground potential, when the gradation indicated by the gradation data is smaller than the predetermined threshold value.
A preferred embodiment of the present invention will be described in further detail based on the following drawings, wherein:
A display-device driving circuit 100 according to an embodiment of the present invention is made up of a level shift circuit 20, a dead-band eliminating circuit 22, transistors 24 through 29, and a capacitor C1.
In a conventional display-device driving circuit, a luminescence element is driven with a voltage on one side of the ground potential, for example, a voltage of 0 to 80 V. In the driving circuit 100 according to the present embodiment, a luminescence element is driven with a voltage being at both positive and negative sides with respect to the ground potential, for example, a voltage of −40 V to 40 V.
As illustrated in
To the logic circuit 20a, digital gradation data that indicates the luminescence intensity of an EL element is input. When receiving the gradation data, the logic circuit 20a creates an N-channel signal or a P-channel signal that is a pulse-width coded (PWM) signal having a pulse width corresponding to the gradation data. The N-channel signal or the P-channel signal is a signal whose pulse width is in proportion to the level of the luminescence-intensity gradation for an EL element. In such a case, when the gradation indicated by the gradation data is greater than or equal to a predetermined threshold value, a P-channel signal is created that has a pulse width corresponding to the difference obtained by subtracting the threshold value from the gradation data, while, when the gradation indicated by the gradation data is smaller than the predetermined threshold value, an N-channel signal is created that has a pulse width corresponding to the gradation indicated by the gradation data. In the present embodiment, the threshold value is set to one half of the entire gradation range. Therefore, when the gradation data is smaller than the half of the entire gradation range, an N-channel signal is created and, when the gradation data meets or exceeds one half of the entire gradation range, a P-channel signal is created. In other words, the logic circuit 20a switches an N-channel signal and a P-channel signal in response to the gradation data, and outputs one or the other.
For example, when the entire gradation range is represented by the gradations of 0 to 255, as illustrated in
The logic circuit 20a creates, in response to the gradation data, either one of the N-channel signal and the P-channel signal, and outputs the N-channel signal or the P-channel signal to an N-channel input terminal or a P-channel input terminal, of the voltage shift circuit 20b, respectively.
The voltage shift circuit 20b steps up the P-channel and N-channel signals output from the logic circuit 20a to high-voltage signals. The driving circuit 100 is made up of logic circuits up to the logic circuit 20a; therefore, the P-channel and N-channel signals output from the logic circuit 20a are low-voltage (e.g., 0 to V or ±3.3 V) pulse signals. Thus, in order to drive the following-stage high-voltage circuits, the voltage shift circuit 20b converts the low-voltage P-channel and N-channel signals into high-voltage signals (e.g., ±40 V).
The source of the transistor 32 is connected to a positive high-voltage power supply bias AVDD and the drain of the transistor 32 is connected to a negative high-voltage power supply bias AVSS (e.g., −40 V) by way of drain and source of the transistor 33. The N-channel transistor 33, to the gate of which a negative gate bias Vn is applied, functions as a current source. The drain of the transistor 31 is connected to the gate of the P-channel transistor 32; change in voltage at the drain terminal of the transistor 31 is output as the P-channel high voltage signal. In other words, because of the step-up circuit comprising the transistors 30 through 33, the P-channel signal of about 3.3 V is converted into a pulse signal of ±40 V, and the pulse signal is output.
Transistors 34 through 37 constitute a step-up circuit for the N-channel signal. The drain of the transistor 34 is connected to a negative high-voltage power supply bias AVSS (e.g., −40 V) by way of the drain and the source, of a transistor 35; the source of the transistor 34 is connected to a positive low-voltage power supply bias DVSS (e.g., +3.3 V). The N-channel transistor 35, to the gate of which a negative gate bias Vn is applied, functions as a current source. To the gate of the P-channel transistor 34, the N-channel signal is input. The transistor 34 becomes OFF while the pulse of the N-channel signal is raised, but becomes ON while the pulse of the N-channel signal is not raised. Accordingly, the voltage at the drain terminal of the transistor 34 is maintained at approximately the positive low-voltage power supply bias DVSS while the pulse of the N-channel signal is lowered, but is kept approximately at the negative high-voltage power supply bias AVSS while the pulse of the N-channel signal is not lowered.
The source of the transistor 37 is connected to a negative high-voltage power supply bias AVSS, while the drain of the transistor 37 is connected to a positive high-voltage power supply bias AVDD by way of drain and source of the transistor 36. The P-channel transistor 36, to the gate of which a positive gate bias Vp is applied, functions as a current source. The drain of the transistor 34 is connected to the gate of the N-channel transistor 37; change in voltage at the source terminal of the transistor 34 is output as the N-channel high voltage signal. In other words, because of the step-up circuit comprising the transistors 34 through 37, the N-channel signal of about +3.3 V is converted into a pulse signal of ±40 V, and the pulse signal is output.
In other words, when the gradation data is smaller than a threshold value (in the present embodiment, smaller than the 128th gradation, half of the entire 256 gradation), a pulse that has amplitude of ±40 V and a pulse width corresponding to the N-channel signal is output as the N-channel high voltage signal. When the gradation data is the same as, or larger than, the threshold value (in the present embodiment, smaller than the 128th gradation, half of the entire 256 gradation), a pulse that has amplitude of ±40 V and a pulse width corresponding to the P-channel signal is output as the P-channel high voltage signal.
The P-channel and N-channel high voltage signals output from the level shift circuit 20 are input to the gates of the transistors 24 and 26, respectively. The source of the transistor 24 is connected to a ramp voltage VR(+); the source of the transistor 26 is connected to a ramp voltage VR(−). In addition, the drains of the transistors 24 and 26 are connected to each other; the node A is grounded through the capacitor C1.
As illustrated in
The transistor 24 becomes ON only while the pulse of the P-channel high voltage signal is output. In contrast, the transistor 26 becomes ON only while the pulse of the N-channel high voltage signal is output. Accordingly, when the pulse of the P-channel high voltage signal is output, as illustrated in
For example, when the P-channel signal (P-channel high-voltage signal) and the N-channel signal (N-channel high voltage signal) are each output with the pulse width corresponding to a gradation in the entire 128 gradations (0 to 127th), the charging voltage Vc reaches a voltage value corresponding to the pulse width, the voltage range of 0 to 40 V or 0 to −40V being represented in 128 gradations.
The dead-band eliminating circuit 22 receives as an input voltage the charging voltage Vc across the capacitor C1, thereby eliminating the dead band.
The drain of the transistor 38 is connected to a positive high-voltage power supply bias AVDD, while the source of the transistor 38 is connected to a negative high-voltage power supply bias AVSS by way of drain and source of the transistor 39. To the gate of the transistor 38, the charging voltage Vc across the capacitor is input. In addition, the N-channel transistor 39, to the gate of which a negative gate bias Vn is applied, functions as a current source.
The drain of the transistor 41 is connected to a negative high-voltage power supply bias AVSS, while the source of the transistor 41 is connected to a positive high-voltage power supply bias AVDD by way of drain and source of the transistor 40. To the gate of the transistor 41, the charging voltage Vc across the capacitor is input. The P-channel transistor 40, to the gate of which a positive gate bias Vp is applied, functions as a current source.
When the charging voltage Vc becomes positive, through the action of the transistor 41 included in a source-follower circuit, the charging voltage Vc+threshold voltage Vt is output, as a N-channel eliminating signal, from the source of the transistor 41, in response to the charging voltage Vc. In contrast, when the charging voltage Vc becomes negative, through the action of the transistor 38 included in a source-follower circuit, the charging voltage Vc-threshold voltage Vt is output, as a P-channel eliminating signal, from the source of the transistor 38, in response to the charging voltage Vc.
To the gate of the transistor 28, the N-channel eliminating signal is input, while the P-channel eliminating signal is input the gate of the transistor 29. The drain of the transistor 28 is connected to a positive AC (sinusoidal) power supply Vsin(+) and the drain of the transistor 29 is connected to a negative AC (sinusoidal) power supply Vsin(−). The source of the transistor 28 is connected to the source of the transistor 29 and a driving voltage VDRV for the EL device is output from the node.
As illustrated in
The transistor 29 outputs the P-channel eliminating signal+threshold voltage Vt, i.e., the driving voltage VDRV corresponding to the charging voltage Vc, in accordance with the change of the P-channel eliminating signal. In contrast, the transistor 28 outputs the N-channel eliminating signal—threshold voltage Vt, i.e., the driving voltage VDRV corresponding to the charging voltage Vc, in accordance with the change of the N-channel eliminating signal.
In this situation, the voltage drop across the transistor 28 is compensated for by the threshold voltage VT of the transistor 41, and the voltage drop across the transistor 29 is compensated by the threshold voltage VT of the transistor 38; therefore, the output of the driving circuit 100 does not have any “dead band”.
Accordingly, as illustrated in
Moreover, because the driving voltage VDRV is controlled through two-side driving having positive and negative polarities, in the positive and negative polarities, respective resolutions may be less than the entire resolutions. For example, when the threshold value is one half of the entire range of gradations, the resolution in each polarity may similarly be half of the entire resolutions. When, as in the present example, there are a total of 256 gradations, and the threshold value is half of the entire gradations, i.e., 128, the respective resolutions may be 128 gradations in positive and negative polarities. Accordingly, the logic circuit 20a may create the N-channel and P-channel signals, while counting the resolutions of 0 to 127 using a counter or the like. Therefore, it is possible to make the counting time shorter than that of a conventional logic circuit, and thereby enhance the speed of control.
Moreover, even when a certain external fluctuation such as a surge is added to the driving voltage VDRV and is transferred through the parasitic capacitance of the transistors 28 and 29, the extent to which the external fluctuation affects the capacitor C1 can be reduced by the transistors 38 and 41 of the dead-band eliminating circuit 22.
In addition, as illustrated in
Although an inorganic EL display device has been described as an example display device, the present invention is not limited to inorganic EL display devices, and any display device can be utilized in the present invention, as long as the display is of a type utilizing an element that can emit light in response to application of a bipolar voltage. In this regard, however, in a display device, such as an inorganic EL display device, whose applied voltage is over a range of several tens of volts, enabling two-side driving, i.e., positive and negative driving can achieve demonstrable effects such as prolonging the lifetime of the luminescence element or enabling reduction in the voltages that must be withstood by devices included in the driving circuit.
As explained above, according to the present invention, because two-side driving of a luminescent device with a driving voltage having both positive and negative polarities is employed, the lifetime of the luminescent device can be extended. Moreover, the two-side driving method utilizing both positive and negative polarities can speed up the control. Furthermore, effects of external fluctuation on the driving voltage can be reduced.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-258593 | Sep 2004 | JP | national |
| 2004-258594 | Sep 2004 | JP | national |
