Patent Grant
11922877
The following disclosure relates to a display device, and more particularly to a display device provided with a pixel circuit including a display element driven by a current such as an organic electroluminescent (EL) element.
In recent years, an organic EL display device provided with a pixel circuit including an organic EL element has been put into practical use. The organic EL element is also called an organic light-emitting diode (OLED) and is a self-luminous display element that emits light with luminance corresponding to a current flowing therethrough. With the organic EL element being a self-luminous display element as described above, the organic EL display device can be easily reduced in thickness and power consumption and increased in luminance as compared to a liquid crystal display device that requires a backlight, a color filter, and the like.
Regarding the pixel circuit of the organic EL display device, a thin-film transistor (TFT) is typically employed as a drive transistor for controlling the supply of a current to the organic EL element. However, the thin-film transistor is prone to variations in its characteristics. Specifically, variations in threshold voltage are likely to occur. When variations in threshold voltage occur in drive transistors provided in a display unit, variations in luminance occur to cause deterioration in display quality. Therefore, various types of processing to compensate for variations in threshold voltage (compensation processing) have been proposed.
As the method of the compensation processing, the following methods are known: an internal compensation method in which compensation processing is performed by providing a capacitor in a pixel circuit to hold information on a threshold voltage of a drive transistor; and an external compensation method in which compensation processing is performed by, for example, measuring the magnitude of a current flowing through the drive transistor under a predetermined condition in a circuit provided outside the pixel circuit and correcting a video signal based on the measurement result.
As a pixel circuit of an organic EL display device employing the internal compensation method for compensation processing, for example, as illustrated in
At the time of charging the holding capacitor C9 in the pixel circuit 90 based on a data signal D(m), first, the gate voltage of the drive transistor (transistor T91) is initialized by turning on the transistor 194. Thereafter, the data signal D(m) is written to the holding capacitor C9 by turning on the transistors T92, T93. At that time, a current is supplied as indicated by an arrow denoted by reference numeral 92 in
Therefore, for the pixel circuit, a configuration has been proposed in which a holding capacitor is provided between a node connected to a data signal line and a node connected to a control terminal (gate terminal) of a drive transistor so that the holding capacitor is charged not via the drive transistor (e.g., see Japanese Laid-Open Patent Publication No. 2014-139696).
In recent years, there has been an increasing demand for a reduction in power consumption for display devices. Therefore, a display device that performs low-frequency drive (low-speed drive) with a drive frequency of, for example, 1 Hz when there is no change in the display screen has been developed. In this regard, with a relatively large leakage current (off-leakage) being generated in the LTPS-TFT, when the pixel circuit 90 having the configuration illustrated in
Therefore, U.S. Pat. No. 10,304,378 describes the use of a thin-film transistor in which a channel layer is formed of an oxide semiconductor (hereinafter referred to as an “oxide TFT”) for some thin-film transistors in a pixel circuit to prevent the generation of a leakage current when low-frequency drive is performed. Oxide TFTs have an advantage of an extremely low leakage current (off leakage), and hence their use in thin-film transistors that make up the pixel and drive circuits of display devices has been increasing in recent years. The oxide semiconductor forming the channel layer of the oxide TFT is made of, for example, indium, gallium, zinc, and oxygen.
Meanwhile, in recent years, a display device including a pixel circuit capable of operating at various frequencies between 1 to 120 Hz, for example, (i.e., a pixel circuit capable of adapting to both high-frequency drive and low-frequency drive) has been developed. With a configuration described in U.S. Pat. No. 10,304,378, it is possible to perform low-frequency drive without causing deterioration in display quality. However, similarly to the configuration illustrated in
Therefore, an object of the following disclosure is to achieve a display device including a pixel circuit that enables both high-frequency drive and low-frequency drive without causing deterioration in display quality.
A display device according to some embodiments of the present disclosure is a display device provided with a pixel circuit including a display element driven by a current, the display device including a display unit that includes
A display device according to some other embodiments of the present disclosure is a display device provided with a pixel circuit including a display element driven by a current, the display device including a display unit that includes
A display device according to still some other embodiments of the present disclosure is a display device provided with a pixel circuit including a display element driven by a current, the display device including a display unit that includes
According to some embodiments of the present disclosure, with regard to the configuration of the pixel circuit, the holding capacitor is provided between the second control node connected to the data signal line via the write control transistor and the first control node connected to the control terminal of the drive transistor. With such a configuration, the holding capacitor is charged not via the drive transistor. That is, the holding capacitor is charged quickly. Since it is sufficient that the voltage of the data signal is determined by the time when the threshold voltage compensation transistor changes from the on-state to the off-state, the display quality does not deteriorate unless a large delay occurs in the waveform change of the data signal. From the above, even when high-frequency drive (high-speed drive) with a drive frequency of 120 Hz, for example, is performed, favorable display quality is maintained. In addition, regarding each of the transistors having the conductive terminal connected to the first control node (the first initialization transistor having the second conductive terminal connected to the first control node, and the threshold voltage compensation transistor having the first conductive terminal connected to the first control node), the channel layer is formed of an oxide semiconductor. Hence the generation of a leakage current in these transistors is prevented. Thus, even when low-frequency drive (low-speed drive) with a drive frequency of 1 Hz, for example, is performed, the display quality is not deteriorated due to the leakage current. That is, favorable display quality is maintained. From the above, a display device including a pixel circuit that enables both high-frequency drive and low-frequency drive without causing deterioration in display quality is achieved.
Embodiments will be described below with reference to the accompanying drawings. In the following description, it is assumed that i and j are integers of 2 or more, m is an integer of 1 or more and i or less, and n is an integer of 1 or more and j or less. In addition, the voltage of each node or the like represents a potential difference from a reference potential when 0 V is set as the reference potential.
<1.1 Overall Configuration>
In the display unit 200, i data signal lines D(1) to D(i) and (j+1) scanning signal lines SCAN(0) to SCAN(j) orthogonal thereto are disposed. Further, in the display unit 200, j emission control lines EM(1) to EM(j) are disposed to correspond one-to-one to the j scanning signal lines SCAN(1) to SCAN(j) except for the scanning signal line SCAN(0). The scanning signal lines SCAN(0) to SCAN(j) and the emission control lines EM(1) to EM(j) are parallel to each other. Furthermore, in the display unit 200, i×j pixel circuits 20 are provided to correspond to the intersections of the i data signal lines D(1) to D(i) and the j scanning signal lines SCAN(1) to SCAN(j). By providing the i×j pixel circuits 20 in this manner, a pixel matrix of i columns and j rows is formed in the display unit 200. In the following, reference numerals SCAN(0) to SCAN(j) may also be attached to scanning signals respectively provided to the (j+1) scanning signal lines SCAN(0) to SCAN(j), reference numerals EM(1) to EM(j) may also be attached to emission control signals respectively provided to the j emission control lines EM(1) to EM(j), and reference numerals D(1) to D(i) may also be attached to data signals respectively provided to the i data signal lines D(1) to D(i).
In the display unit 200, power lines (not illustrated) common to all the pixel circuits 20 are disposed. More specifically, a power line that supplies a high-level power supply voltage ELVDD for driving the organic EL element (hereinafter referred to as a “high-level power line”), a power line that supplies a low-level power supply voltage ELVSS for driving the organic EL element (hereinafter referred to as a “low-level power line”), and a power line that supplies a reference voltage Vsus (hereinafter referred to as an “reference power line”) are disposed. The high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the reference voltage Vsus are supplied from a power supply circuit (not illustrated). In the present embodiment, a first power line is achieved by the high-level power line, and a second power line is achieved by the low-level power line.
Hereinafter, the operation of each component illustrated in
The source driver 300 is connected to the i data signal lines D(1) to D(i). The source driver 300 receives the digital video signal DV and the source control signal SCTL which are outputted from the display control circuit 100 and applies data signals to the i data signal lines D(1) to D(i). The source driver 300 includes an i-bit shift register, a sampling circuit, a latch circuit, i D/A converters, and the like (not illustrated). The shift register has i registers that are cascade-connected. On the basis of the source clock signal, the shift register sequentially transfers the pulse of the source start pulse signal supplied to the first-stage register from the input terminal to the output terminal. A sampling pulse is outputted from each stage of the shift register in accordance with the transfer of the pulse. On the basis of the sampling pulse, the sampling circuit stores the digital video signal DV. The latch circuit captures and holds the digital video signal DV for one row stored in the sampling circuit in accordance with the latch strobe signal. The D/A converter is provided to correspond to each of the data signal lines D(1) to D(i). The D/A converter converts the digital video signal DV held in the latch circuit into an analog voltage. The converted analog voltages are simultaneously applied to all the data signal lines D(1) to D(i) as data signals.
The gate driver 400 is connected to the (j+1) scanning signal lines SCAN(0) to SCAN(j). The gate driver 400 includes a shift register, a logic circuit, and the like. On the basis of the gate control signal GCTL outputted from the display control circuit 100, the gate driver 400 drives the (j+1) scanning signal lines SCAN(0) to SCAN(j).
The emission driver 500 is connected to the j emission control lines EM(1) to EM(j). The emission driver 500 includes a shift register, a logic circuit, and the like. On the basis of the emission driver control signal EMCTL outputted from the display control circuit 100, the emission driver 500 drives the j emission control lines EM(1) to EM(j).
The i data signal lines D(1) to D(i), the (j+1) scanning signal lines SCAN(0) to SCAN(j), and the j emission control lines EM(1) to EM(j) are driven as described above, whereby an image based on the image data DAT is displayed on the display unit 200.
<1.2 Configuration of Pixel Circuit>
Next, the configuration of the pixel circuit 20 in the display unit 200 will be described.
With regard to the configuration illustrated in
The first initialization transistor T1 has a control terminal connected to the scanning signal line SCAN(n−1) in the (n−1)th row, a first conductive terminal connected to the high-level power line and the first conductive terminal of the first emission control transistor T5, and a second conductive terminal connected to the first control node NG. The threshold voltage compensation transistor T2 has a control terminal connected to the scanning signal line SCAN(n) in the nth row, a first conductive terminal connected to the first control node NG, and a second conductive terminal connected to the first conductive terminal of the drive transistor T4 and the second conductive terminal of the first emission control transistor T5. The write control transistor T3 has a control terminal connected to the scanning signal line SCAN(n) in the nth row, a first conductive terminal connected to the data signal line D(m) in the mth column, and a second conductive terminal connected to the second control node NA. The drive transistor T4 has a control terminal connected to the first control node NG, a first conductive terminal connected to the second conductive terminal of the threshold voltage compensation transistor T2 and the second conductive terminal of the first emission control transistor T5, and a second conductive terminal connected to the second conductive terminal of the second emission control transistor T6, the first conductive terminal of the second initialization transistor T7, and the anode terminal (first terminal) of the organic EL element 21.
The first emission control transistor T5 has a control terminal connected to the emission control line EM(n) in the nth row, a first conductive terminal connected to the high-level power line and the first conductive terminal of the first initialization transistor T1, and a second conductive terminal connected to the second conductive terminal of the threshold voltage compensation transistor T2 and the first conductive terminal of the drive transistor T4. The second emission control transistor T6 has a control terminal connected to the emission control line EM(n) in the nth row, a first conductive terminal connected to the second control node NA, and a second conductive terminal connected to the second conductive terminal of the drive transistor T4, the first conductive terminal of the second initialization transistor T7, and the anode terminal of the organic EL element 21. The second initialization transistor T7 has a control terminal connected to the scanning signal line SCAN(n) in the nth row, a first conductive terminal connected to the second conductive terminal of the drive transistor T4, the second conductive terminal of the second emission control transistor T6, and the anode terminal of the organic EL element 21, and a second conductive terminal connected to the reference power line. The holding capacitor C1 has a first electrode connected to the first control node NG and a second electrode connected to the second control node NA. The organic EL element 21 has an anode terminal connected to the second conductive terminal of the drive transistor T4, the second conductive terminal of the second emission control transistor T6, and the first conductive terminal of the second initialization transistor T7, and has a cathode terminal (second terminal) connected to the low-level power line.
In the present embodiment, an oxide TFT is employed for each of the first initialization transistor T1, the threshold voltage compensation transistor T2, and the second initialization transistor T7, and an LTPS-TFT is employed for each of the write control transistor T3, the drive transistor T4, the first emission control transistor T5, and the second emission control transistor T6.
Note that the oxide semiconductor forming the channel layer of the oxide TFT is made of indium, gallium, zinc, and oxygen in the present embodiment. However, it is not limited thereto.
<1.3 Drive Method (Operation of Pixel Circuit)>
Next, the operation of the pixel circuit 20 illustrated in
In the period before period P1, the emission control signal EM(n) is at the high level, and the scanning signals SCAN(n) and SCAN(n−1) are at the low level. At this time, the first emission control transistor T5 and the second emission control transistor T6 are in the on-state. With the second emission control transistor T6 being in the on-state, the voltage between the control terminal and the second conductive terminal of the drive transistor T4 is equal to the charging voltage of the holding capacitor C1. In addition, with the first emission control transistor T5 being in the on-state, the drive current is supplied to the organic EL element 21 in accordance with the magnitude of the charging voltage of the holding capacitor C1. Thus, the organic EL element 21 emits light in accordance with the magnitude of the drive current.
When period P1 is reached, an emission control signal EM(n) changes from the high level to the low level. Thereby, the first emission control transistor T5 and the second emission control transistor T6 are turned off. As a result, the supply of the drive current to the organic EL element 21 is cut off, and the organic EL element 21 is interrupted.
When period P2 is reached, the scanning signal SCAN(n−1) changes from the low level to the high level. Thereby, the first initialization transistor T1 is turned on, and a current is supplied to the first control node NG as indicated by an arrow denoted by reference numeral 61 in
When period P3 is reached, the scanning signal SCAN(n−1) changes from the high level to the low level. Thereby, the first initialization transistor T1 is turned off, and the initialization of the voltage of the first control node NG ends. In addition, when period P3 is reached, the scanning signal SCAN(n) changes from the low level to the high level. Thereby, the threshold voltage compensation transistor T2, the write control transistor T3, and the second initialization transistor T7 are turned on. By the write control transistor T3 being turned on, the data signal D(m) is provided to the second control node NA via the write control transistor T3 as indicated by an arrow denoted by reference numeral 62 in
When period P4 is reached, the scanning signal SCAN(n) changes from the high level to the low level. Thereby, the threshold voltage compensation transistor T2, the write control transistor T3, and the second initialization transistor T7 are turned off. In period P4, the voltages of the first control node NG and the second control node NA are maintained at the voltage at the end of period P3.
When period P5 is reached, an emission control signal EM(n) changes from the low level to the high level. Thereby, the second emission control transistor T6 is turned on, and the second conductive terminal of the drive transistor T4 and the second control node NA are connected electrically. That is, the voltage of the second conductive terminal of the drive transistor T4 becomes equal to the voltage of the second control node NA. In addition, in period P5, the first emission control transistor T5 is turned on. From the above, in accordance with the magnitude of the voltage between the control terminal and the second conductive terminal of the drive transistor T4 (the charging voltage of the holding capacitor C1), the drive current is supplied to the organic EL element 21 as indicated by an arrow denoted by reference numeral 64 in
Thereafter, the state in which the organic EL element 21 emits light in accordance with the magnitude of the drive current is continued throughout the period until the emission control signal EM(n) changes from the high level to the low level.
Here, specific examples of voltage settings and voltage changes will be described. For example, the high-level power supply voltage ELVDD is set to 11.5 V, the low-level power supply voltage ELVSS and the reference voltage Vsus are set to 2.5 V, the high-level side voltages of the scanning signal SCAN and the emission control signal EM are set to 14.5 V, and the low-level side voltages of the scanning signal SCAN and the emission control signal EM are set to −3.5 V. The voltage of the data signal D is set within a range of 1 V to 6 V. In this regard, the voltage corresponding to white is 1 V, and the voltage corresponding to black is 6 V. It is assumed that the threshold voltage of the drive transistor T4 is 4 V. Further, it is assumed that the voltage Voled between the anode and the cathode of the organic EL element 21 during the emission period is 4 V when the voltage of the data signal D is a voltage (1 V) corresponding to white, and it is assumed that the voltage Voled between the anode and the cathode of the organic EL element 21 during the emission period is 0 V when the voltage of the data signal D is a voltage (6 V) corresponding to black.
First, a case where the voltage of the data signal D is a voltage (1 V) corresponding to white will be described. At the end of period P2, the voltage of the first control node NG is 11.5 V regardless of the voltage of the data signal D.
In period P3, the voltage of the second control node NA becomes 1 V. Further, as described above, the voltage of the first control node NG decreases until becoming equal to the sum of the reference voltage Vsus and the threshold voltage Vth of the drive transistor 14. Thus, at the end of period P3, the voltage of the first control node NG is 6.5 V. As described above, in period P4, the voltages of the first control node NG and the second control node NA are maintained at the voltage at the end of period P3. From the above, at the end of period P4, the voltage of the second control node NA is 1 V, and the voltage of the first control node NG is 6.5 V.
In period P5, the voltage of the second control node NA becomes equal to the sum of the low-level power supply voltage ELVSS and the voltage Voled between the anode and the cathode of the organic EL element 21. That is, the voltage VNA of the second control node NA in period P5 is expressed by Expression (1) below.
VNA=ELVSS+Voled (1)
Thus, in period P5, the voltage VNA of the second control node NA is 6.5 V.
When the voltage of the data signal D is represented by Vdata, a change ΔVNA of the voltage of the second control node NA from period P4 to period P5 is expressed by Expression (2) below.
ΔVNA=ELVSS+Voled−Vdata (2)
In this example, the change ΔVNA in the voltage of the second control node NA is 5.5 V.
As described above, in period P5, the voltage of the first control node NG also changes in accordance with the change in the voltage of the second control node NA. The voltage of the first control node NG at the end of period P4 is equal to the sum of the reference voltage Vsus and the threshold voltage Vth of the drive transistor T4, and hence a voltage VNG of the first control node NG in period P5 is expressed by Expression (3) below. Note that k is a ratio of the capacitance value of the holding capacitor C1 to the capacitance value of the entire capacitance formed by the second control node NA, and here, it is assumed that “k=1” holds.
VNG=Vsus+Vth+kΔVNA (3)
From the above, in period P5, the voltage VNG of the first control node NG is 12 V.
A voltage Vgs between the first conductive terminal and the second conductive terminal of the drive transistor 14 in period P5 is expressed by Expression (4) below.
In this example, the voltage Vgs between the first conductive terminal and the second conductive terminal of the drive transistor T4 is 5.5 V.
A current Ioled flowing through the organic EL element 21 in the period after period P5 is expressed by Expression (5) below when “Vgs≥Vth” holds, and is expressed by Expression (6) below when “Vgs<Vth” holds.
However, β=(W/L)×μ×Cox
With regard to the time when “Vgs<Vth” holds, the surface potential can be approximated by “VNG−Vth”, and thus Ioled is proportional to exp(q(VNG−Vth)/kT). That is, when “Vgs<Vth” holds, Ioled decreases exponentially as VNG decreases.
Next, a case where the voltage of the data signal D is a voltage (6 V) corresponding to black will be described. As described above, at the end of period P2, the voltage of the first control node NG is 11.5 V regardless of the voltage of the data signal D.
In period P3, the voltage of the second control node NA is 6 V. In addition, as described above, the voltage of the first control node NG is 6.5 V at the end of period P3, and the voltages of the first control node NG and the second control node NA are maintained at the voltage at the end of period P3, in period P4. From the above, at the end of period P4, the voltage of the second control node NA is 6 V, and the voltage of the first control node NG is 6.5 V.
In period P5, the voltage VNA of the second control node NA is 2.5 V according to Expression (1) above. A change ΔVNA in the voltage of the second control node NA from period P4 to period P5 is −3.5 V according to Expression (2) above. In period P5, the voltage VNG of the first control node NG is 3 V according to Expression (3) above. The voltage Vgs between the first conductive terminal and the second conductive terminal of the drive transistor T4 in period P5 is 0.5 V according to Expression (4) above.
The current Ioled flowing through the organic EL element 21 in the period after period P5 is expressed by the same Expression as in the case where the voltage of the data signal D is the voltage (1 V) corresponding to white (cf. Expressions (5) and (6) above).
<1.4 Comparison with Known Example>
According to the configuration described in U.S. Pat. No. 10,304,378 (cf.
<1.5 Effects>
According to the present embodiment, with regard to the configuration of the pixel circuit 20, the holding capacitor C1 is provided between the second control node NA connected to the data signal line D via the write control transistor T3 and the first control node NG connected to the control terminal of the drive transistor T4. With such a configuration, the holding capacitor C1 is charged not via the drive transistor T4. That is, the holding capacitor C1 is charged quickly. In addition, it is sufficient that the voltage of the data signal D is determined by the time when the threshold voltage compensation transistor T2 changes from the on-state to the off-state (time point to in
<1.6 Modification>
A modification of the first embodiment will be described below. However, differences from the first embodiment will be mainly described.
When the second initialization transistor T7 is turned on, the anode terminal of the organic EL element 21 and the reference power line are electrically connected, and the anode voltage of the organic EL element 21 is initialized based on the reference voltage Vsus. Thus, the reset control line EMB is signal wiring for initializing the state of the anode terminal of the organic EL element 21.
In the present modification as well, an oxide TFT is employed for each of the first initialization transistor T1, the threshold voltage compensation transistor T2, and the second initialization transistor T7, and an LIPS-TFT is employed for each of the write control transistor T3, the drive transistor T4, the first emission control transistor T5, and the second emission control transistor T6.
The operation of the pixel circuit 20 illustrated in
The period before period P1 is the same as that in the first embodiment. Note that the reset control signal EMB(n) is at the low level. In period P1, as in the first embodiment, the organic EL element 21 is turned off. Further, in period P1, the reset control signal EMB(n) changes from the low level to the high level. Thereby, the second initialization transistor T7 is turned on, a current is generated as indicated by an arrow denoted by reference numeral 65 in
In period P2, as in the first embodiment, the voltage of the first control node NG (i.e., the gate voltage of the drive transistor T4) is initialized by the first initialization transistor T1 being turned on.
In period P3, the reset control signal EMB(n) is maintained at the high level, and the scanning signal SCAN(n) changes from the low level to the high level. Thereby, the second initialization transistor T7 is maintained in the on-state, and the threshold voltage compensation transistor T2 and the write control transistor T3 are turned on. From the above, similarly to the first embodiment, the data signal D(m) is provided to the second control node NA via the write control transistor T3 as indicated by an arrow denoted by reference numeral 66 in
In period P4, as in the first embodiment, the voltages of the first control node NG and the second control node NA are maintained at the voltage at the end of period P3.
When period P5 is reached, the reset control signal EMB(n) changes from the high level to the low level. Thereby, the second initialization transistor T7 is turned off. Further, in period P5, the emission control signal EM(n) changes from the low level to the high level. Thereby, the first emission control transistor T5 and the second emission control transistor T6 are turned on, and as in the first embodiment, a drive current is supplied to the organic EL element 21 as indicated by an arrow denoted by reference numeral 68 in
Thereafter, the state in which the organic EL element 21 emits light in accordance with the magnitude of the drive current is continued throughout the period until the emission control signal EM(n) changes from the high level to the low level.
According to the present modification, it is possible to obtain an effect of preventing the occurrence of flicker during the low-frequency drive as compared to the first embodiment. This will be described below with reference to
First, attention is paid to the first embodiment (cf.
Next, attention is paid to the present modification (cf.
<2.1 Overall Configuration>
<2.2 Configuration of Pixel Circuit>
With regard to the configuration illustrated in
The first initialization transistor M1 has a control terminal connected to the scanning signal line SCAN(n) in the nth row, a first conductive terminal connected to the reference power line, and a second conductive terminal connected to the second control node NA. The threshold voltage compensation transistor M2 has a control terminal connected to the scanning signal line SCAN(n) in the nth row, a first conductive terminal connected to the first control node NG, and a second conductive terminal connected to the second conductive terminal of the drive transistor M4 and the first conductive terminal of the first emission control transistor M5. The write control transistor M3 has a control terminal connected to the scanning signal line SCAN(n) in the nth row, a first conductive terminal connected to the data signal line D(m) in the mth column, and a second conductive terminal connected to the second control node NA. The drive transistor M4 has a control terminal connected to the first control node NG, a first conductive terminal connected to the high-level power line, and a second conductive terminal connected to the second conductive terminal of the threshold voltage compensation transistor M2 and the first conductive terminal of the first emission control transistor M5.
The first emission control transistor M5 has a control terminal connected to the emission control line EM(n) in the nth row, a first conductive terminal connected to the second conductive terminal of the threshold voltage compensation transistor M2 and the second conductive terminal of the drive transistor M4, and a second conductive terminal connected to the first conductive terminal of the second emission control transistor M6 and the anode terminal (first terminal) of the organic EL element 21. The second emission control transistor M6 has a control terminal connected to the emission control line EM(n) in the nth row, a first conductive terminal connected to the second conductive terminal of the first emission control transistor M5 and the anode terminal of the organic EL element 21, and a second conductive terminal connected to the second conductive terminal of the second initialization transistor M7 and the initialization power line. The second initialization transistor M7 has a control terminal connected to the scanning signal line SCAN(n−1) in the (n−1)th row, a first conductive terminal connected to the first control node NG, and a second conductive terminal connected to the second conductive terminal of the second emission control transistor M6 and the initialization power line. The holding capacitor C2 has a first electrode connected to the first control node NG and a second electrode connected to the second control node NA. The organic EL element 21 has an anode terminal connected to the second conductive terminal of the first emission control transistor M5 and the first conductive terminal of the second emission control transistor M6, and has a cathode terminal (second terminal) connected to the low-level power line.
In the present embodiment, an oxide TFT is employed for each of the threshold voltage compensation transistor M2, the write control transistor M3, the second emission control transistor M6, and the second initialization transistor M7, and an LTPS-TFT is employed for each of the first initialization transistor M1, the drive transistor M4, and the first emission control transistor M5.
<2.3 Drive Method (Operation of Pixel Circuit)>
Next, the operation of the pixel circuit 20 illustrated in
In a period before period P11, the emission control signal EM(n), the scanning signal SCAN(n), and the scanning signal SCAN(n−1) are at the low level. At this time, the threshold voltage compensation transistor M2, the second emission control transistor M6, and the second initialization transistor M7 are in the off-state, and the first emission control transistor M5 is in the on-state. Thus, a drive current is supplied to the organic EL element 22 in accordance with the magnitude of the voltage between the control terminal and the second conductive terminal of the drive transistor M4. Thereby, the organic EL element 22 emits light in accordance with the magnitude of the drive current. Note that the voltage of the second control node NA is equal to the reference voltage Vsus because the write control transistor M3 is in the off-state and the first initialization transistor M1 is in the on-state.
When period P11 is reached, an emission control signal EM(n) changes from the low level to the high level. Thereby, the first emission control transistor M5 is turned off, and the second emission control transistor M6 is turned on. By the first emission control transistor M5 being turned off, the supply of the drive current to the organic EL element 22 is interrupted, and the organic EL element 22 is turned off. In addition, by the second emission control transistor M6 being turned on, the anode voltage of the organic EL element 22 is initialized based on the initialization voltage Vini.
When period P12 is reached, the scanning signal SCAN(n−1) changes from the low level to the high level. Thereby, the second initialization transistor M7 is turned on, and a current flows from the first control node NG to the initialization power line as indicated by an arrow denoted by reference numeral 71 in
When period P13 is reached, the scanning signal SCAN(n−1) changes from the high level to the low level. Thereby, the second initialization transistor M7 is turned off, and the initialization of the voltage of the first control node NG ends. Further, when period P13 is reached, the scanning signal SCAN(n) changes from the low level to the high level. Thereby, the first initialization transistor M1 is turned off, and the threshold voltage compensation transistor M2 and the write control transistor M3 are turned on. By the first initialization transistor M1 being turned off and the write control transistor M3 being turned on, the data signal D(m) is provided to the second control node NA via the write control transistor M3 as indicated by an arrow denoted by reference numeral 72 in
When period P14 is reached, the scanning signal SCAN(n) changes from the high level to the low level. Thereby, the threshold voltage compensation transistor M2 and the write control transistor M3 are turned off, and the first initialization transistor M1 is turned on. By the write control transistor M3 being turned off and the first initialization transistor M1 being turned on, a current flows from the second control node NA to the reference power line as indicated by an arrow denoted by reference numeral 74 in
When period P15 is reached, an emission control signal EM(n) changes from the high level to the low level. Thereby, the second emission control transistor M6 is turned off, and the first emission control transistor M5 is turned on. As a result, a drive current is supplied to the organic EL element 22 as indicated by an arrow denoted by reference numeral 75 in
Thereafter, the state in which the organic EL element 22 emits light in accordance with the magnitude of the drive current is continued throughout the period until the emission control signal EM(n) changes from the high level to the low level.
<2.4 Effects>
According to the present embodiment, with regard to the configuration of the pixel circuit 20, the holding capacitor C2 is provided between the second control node NA connected to the data signal line D via the write control transistor M3 and the first control node NG connected to the control terminal of the drive transistor M4. With such a configuration, the holding capacitor C2 is charged not via the drive transistor M4. That is, the holding capacitor C2 is charged quickly. In addition, since it is sufficient that the voltage of the data signal D is determined by the time when the threshold voltage compensation transistor M2 changes from the on-state to the off-state, the display quality does not deteriorate unless a large delay occurs in the waveform change of the data signal D. Furthermore, with the LTPS-TFT being employed for the drive transistor M4, the first control node NG is quickly charged in period P13 (cf.
In addition, by employing a p-channel transistor for the first initialization transistor M1 and an n-channel transistor for the threshold voltage compensation transistor M2 and the write control transistor M3, the operations of the transistors M1 to M3 can be controlled by one control line (scanning signal line SCAN). Therefore, high definition is possible.
<3. Others>
Although the organic EL display device has been described above as an example, it is not limited thereto, and the present disclosure can also be applied to an inorganic EL display device, a quantum dot light-emitting diode (QLED) display device, and the like.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2020/028372 | 7/22/2020 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2022/018842 | 1/27/2022 | WO | A |
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| Official Communication issued in International Patent Application No. PCT/JP2020/028372, dated Oct. 20, 2020. |
| Number | Date | Country | |
|---|---|---|---|
| 20230298522 A1 | Sep 2023 | US |
