Patent Application
20250078724
This application claims the benefit of the Republic of Korea Patent Application No. 10-2023-0117534 filed on Sep. 5, 2023, which is hereby incorporated by reference in its entirety.
The present disclosure relates to a high-speed driving display apparatus.
Recently, display apparatuses including a high-performance source driver integrated circuit (IC) have been developed to be suitable for high-speed driving. The display apparatuses have increased the output performance of an output circuit included in a source driver IC to increase an output slew rate of a target data voltage which is to be written in a display panel.
However, because a level of a main bias current supplied to an output circuit should increase for increasing an output slew rate, there is a problem where power consumption increases. A power consumption characteristic and a data charging/discharging characteristic (i.e., an output slew rate) needed for high-speed driving display apparatuses have a trade-off relationship therebetween. In high-speed driving display apparatuses of the related art, it is difficult to satisfy all of a power consumption characteristic and a data charging/discharging characteristic.
To overcome the aforementioned problem of the related art, the present disclosure may provide a display apparatus which may decrease power consumption and may enhance an output slew rate even without an increase in a main bias current supplied to an output circuit.
To achieve these objects and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, a display apparatus includes a display panel including a plurality of pixels, a timing controller configured to generate current mirror control information, based on an amount of transition of image data to be written in the plurality of pixels, and an output circuit configured to output a target data voltage, corresponding to the image data, to a data output channel connected to one of the plurality of pixels, wherein the output circuit includes a mirroring current generator configured to generate a mirroring current and an amplifier circuit including a pull-up transistor including a gate electrode connected to a first control node, a first current mirror configured to supply the mirroring current to the first control node according to the current mirror control information, a pull-down transistor including a gate electrode connected to a second control node, and a second current mirror configured to supply the mirroring current to the second control node according to the current mirror control information.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the disclosure and together with the description serve to explain the principle of the disclosure. In the drawings:
Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. The disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the disclosure to those skilled in the art.
Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is only defined by scopes of claims.
The shapes, sizes, ratios, angles, numbers and the like disclosed in the drawings for description of various embodiments of the present disclosure to describe embodiments of the present disclosure are merely exemplary and the present disclosure is not limited thereto. Like reference numerals refer to like elements throughout. Throughout this specification, the same elements are denoted by the same reference numerals. As used herein, the terms “comprise”, “having,” “including” and the like suggest that other parts can be added unless the term “only” is used. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless context clearly indicates otherwise.
Elements in various embodiments of the present disclosure are to be interpreted as including margins of error even without explicit statements.
In describing a position relationship, for example, when a position relation between two parts is described as “on˜”, “over˜”, “under˜”, and “next˜”, one or more other parts may be disposed between the two parts unless “just” or “direct” is used.
It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.
In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Referring to
A plurality of data lines DL and a plurality of gate lines GL may be provided in the display panel PNL, and a plurality of pixels PIX may be respectively arranged in a plurality of intersection areas between the signal lines GL and DL. A pixel array may be provided in a display area of the display panel PNL by using the pixels PIX arranged as a matrix type.
In the pixel array, the pixels PIX may configure a horizontal line in a horizontal direction so as to be adjacent. The number of horizontal lines may be a vertical resolution of the display panel PNL. Pixels PIX configuring the same horizontal line may be connected to the same gate line GL and different data lines DL, but are not limited thereto. Each of the pixels PIX may be implemented as an emission cell including a light emitting diode or a liquid crystal cell including a liquid crystal layer, but the present embodiment is not limited thereto.
The timing controller CONT may generate a data timing control signal DDC for controlling an operation timing of the data driver circuit DDRV and a gate timing control signal GDC for controlling an operation timing of the gate driver circuit GDRV, based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE input from a host system (not shown). The gate timing control signal GDC may include a gate start signal and gate shift clocks. The data timing control signal DDC may include a source start pulse, a source sampling clock, and a source output enable signal.
The timing controller CONT may transfer image data DATA, input from the host system, to the data driver circuit DDRV through an internal interface circuit. The image data DATA may be for displaying an image by using the pixels PIX, and the data driver circuit DDRV may convert the image data DATA into data voltages respectively corresponding to gray levels and may write the data voltages in the pixels PIX. The internal interface circuit for data communication between the timing controller CONT and the data driver circuit DDRV may be an embedded panel interface (EPI) circuit.
The timing controller CONT may compare image data DATA of a previous horizontal line with image data DATA of a current horizontal line to calculate the degree of transition of the image data DATA by pixel units, and then, may generate current mirror control information, based on the degree of transition of the image data DATA. The timing controller CONT may encode the data timing control signal DDC, the current mirror control information, and the image data DATA in an EPI transfer format and may transfer the encoded timing control signal DDC, current mirror control information, and image data DATA to the data driver circuit DDRV through the internal interface circuit.
The gate driver circuit GDRV may generate a scan signal, based on the gate timing control signal GDC from the timing controller CONT, and may supply the scan signal to the gate lines GL. A horizontal line in which a data voltage is to be written may be selected by the scan signal. The gate driver circuit GDRV may be embedded into a non-display area of the display panel PNL, based on a gate in panel (GIP) type. The non-display area may be disposed outside the panel array in the display panel PNL.
The data driver circuit DDRV may include at least one source driver integrated circuit (IC) SD-IC. The source driver IC SD-IC may decode the EPI transfer format transferred from the timing controller CONT to separate the data timing control signal DDC, the current mirror control information, and the image data DATA from the EPI transfer format. The source driver IC SD-IC may convert the image data DATA into data voltages, based on the data timing control signal DDC, and may output the data voltages to the data lines DL1 to DLn through data output channels CH1 to CHn.
At this time, the source driver IC SD-IC may selectively improve an output slew rate of each of the data voltages, based on the current mirror control information, thereby enhancing all of a power consumption characteristic and a data charging/discharging characteristic.
Referring to
The control logic circuit 300 may sample RGB image data included in an EPI transfer format of a serial type to recover, based on an internal clock timing. The control logic circuit 300 may sample a bit of control packet data included in the EPI transfer format, based on an internal clock timing, and may sample the data timing control signal DDC and current mirror control information CON1 to CONn, which are for controlling an operation of the source driver IC SD-IC, from the sampled control packet data to recover, based on the internal clock timing.
The current mirror control information CON1 to CONn may be independently set and recovered at a period of one horizontal period for each data output channel. The current mirror control information CON1 to CONn may include transition direction information (i.e., first control information) for selectively turning on a first current mirror or a second current mirror in the output circuit 330 and on time information (i.e., second control information) for setting a time for maintaining a selected current mirror in an enable state.
The transition direction information may denote a transition direction of a data voltage and may include a first logic value (or a first bit value) indicating up transition and a second logic value (or a second bit value) indicating down transition. The transition direction information may be based on the amount of pixel-based data transition of each output channel obtained by comparing Nth−1 (where N may be a natural number) horizontal line image data with Nth horizontal line image data. Based on a positive (+) sign or a negative (−) sign of data transition, the second current mirror may be turned on, or the first current mirror may be turned on. That is, the transition direction information may be a criterion which selects a current mirror enabled among the first and second current mirrors in the output circuit 330.
When the first logic value indicating up transition is input to the output circuit 330, the second current mirror may be enabled, and a gate on voltage of a pull-up transistor may be bootstrapped, and thus, an up transition time of a data voltage may be reduced.
When the second logic value indicating down transition is input to the output circuit 330, the first current mirror may be enabled, and a gate on voltage of a pull-down transistor may be bootstrapped, and thus, a down transition time of the data voltage may be reduced.
The on time information may be a criterion for setting an enable maintenance time of a current mirror selected based on the transition direction information. The on time information may be set so that an enable maintenance time of a current mirror increases as the amount of transition of a data voltage increases. For example, when the first logic value indicating up transition is input to the output circuit 330, the second current mirror may be enabled, and an enable maintenance time of the second current mirror may be determined based on the on time information. As the amount of up transition of a data voltage increases, the enable maintenance time of the second current mirror may increase, and thus, an up transition time may decrease. In this manner, when the second logic value indicating down transition is input to the output circuit 330, the first current mirror may be enabled, and an enable maintenance time of the first current mirror may be determined based on the on time information. As the amount of down transition of the data voltage increases, the enable maintenance time of the first current mirror may increase, and thus, a down transition time may decrease. Also, when the amount of transition of the data voltage is less than or equal to a predetermined threshold value, the on time information may be set to disable all of the first and second current mirrors.
The latch circuit 310 may convert bits of RGB image data, sampled by the control logic circuit 300, into a parallel-type data format. The latch circuit 310 may be synchronized based on an internal clock output from the control logic circuit 300.
The D/A conversion circuit 320 may map RGB image data, converted into the parallel-type data format, to gamma compensation voltages output by a gamma circuit to generate a target data voltage. The gamma circuit may include at least one gamma resistor string for divide a high level gamma voltage and a low level gamma voltage and a plurality of gamma buffers which output, as gamma compensation voltages, voltages applied to voltage division nodes of the gamma resistor string.
The D/A conversion circuit 320 may include a plurality of DAC switches which are individually coupled to output buffers 330-1 to 330-n of the output circuit 330. Each of the DAC switches may selectively supply a gamma compensation voltage, mapped to each gray level of the RGB image data, as a target data voltage to the output circuit 330.
The output circuit 330 may include a plurality of output buffers 330-1 to 330-n and may output the target data voltage, corresponding to the RGB image data, to the data output channels CH1 to CHn. An output slew rate of an amplifier circuit included in each of the plurality of output buffers 330-1 to 330-n may be individually controlled based on the current mirror control information CON1 to CONn input from the control logic circuit 300.
The output circuit 330 may include a main bias unit MBB (e.g., a circuit) and a mirroring current generator CSB, which are connected to the output buffers 330-1 to 330-n in common.
The main bias unit MBB may apply an amplifier bias current, needed for an operation of each output buffer, to the output buffers 330-1 to 330-n in common. The amplifier bias current may be set to a minimum level based on a normal transition condition, power consumption occurring in the output buffers 330-1 to 330-n may be reduced.
The mirroring current generator CSB may generate a mirroring current for increasing an output slew rate of the amplifier circuit and may apply the mirroring current to the output buffers 330-1 to 330-n. The mirroring current generator CSB may adjust a level of the mirroring current, based on the current mirror control information CON1 to CONn input from the control logic circuit 300.
Referring to
The amplifier circuit may be connected to an input stage ISTG of the amplifier AMP to which a target data voltage is input. The amplifier circuit may be connected a first control node Q1 and a second control node Q2 of the input stage ISTG and may be enabled with the mirroring current Iadd supplied to the first control node Q1 and the second control node Q2 to output the target data voltage to an output node NO.
The amplifier circuit may include a pull-up transistor TU including a gate electrode which is connected to the first control node Q1, a first current mirror CM1 which supplies the mirroring current Iadd to the first control node Q1 according to current mirror control information CON, a pull-down transistor TD including a gate electrode which is connected to the second control node Q2, and a second current mirror CM2 which supplies the mirroring current Iadd to the second control node Q2 according to the current mirror control information CON.
The pull-up transistor TU may be implemented as a P-type transistor (for example, PMOS) connected between a high level voltage source PVDD and an output node NO. The pull-down transistor TD may be implemented as an N-type transistor (for example, NMOS) connected between a low level voltage source VSSH and the output node NO.
The first current mirror CM1 may include a first mirror transistor MF and a first switch SF, which are serially connected between the high level voltage source PVDD and the first control node Q1. The first mirror transistor MF may be implemented as a P-type transistor (for example, PMOS) and may configure a current mirror along with a transistor M1 of the mirroring current generator CSB. To this end, a gate electrode of the first mirror transistor MF may be connected to a gate electrode of the transistor M1 through a node NX, and the same mirroring current Iadd may flow in the first mirror transistor MF and the transistor M1. The first switch SF may be enabled (for example, turned on) based on first control information CTR_1 (i.e., transition direction information) of the current mirror control information CON. An enable maintenance time of the first switch SW may be controlled based on second control information CTR_2 (i.e., on time information) of the current mirror control information CON.
The second current mirror CM2 may include a second mirror transistor MR and a second switch SR, which are serially connected between the low level voltage source VSSH and the second control node Q2. The second mirror transistor MR may be implemented as an N-type transistor (for example, NMOS) and may configure a current mirror along with a transistor M2 of the mirroring current generator CSB. To this end, a gate electrode of the second mirror transistor MR may be connected to a gate electrode of the transistor M2 through a node NY, and the same mirroring current Iadd may flow in the second mirror transistor MF and the transistor M2. The second switch SR may be enabled (for example, turned on) based on the first control information CTR_1 (i.e., transition direction information) of the current mirror control information CON. An enable maintenance time of the second switch SR may be controlled based on the second control information CTR_2 (i.e., on time information) of the current mirror control information CON.
The amplifier circuit may further include a first capacitor C1 connected between the first control node Q1 and the output node NO and a second capacitor C2 connected between the second control node Q2 and the output node NO. The first and second capacitors C1 and C2 may electrically couple the first control node Q1 to the second control node Q2 to allow gate voltages of the pull-up and pull-down transistors TU and TD to be bootstrapped based on a predetermined condition.
The mirroring current generator CSB may apply the same mirroring current Iadd to the first current mirror CM1 and the second current mirror CM2 and may thus prevent a problem of output asymmetry between a rising output and a falling output occurring when enhancing an output slew rate of the amplifier circuit.
The mirroring current generator CSB may include a current source MCS and transistors M1 to M3, which are connected to the high level voltage source PVDD generating the mirroring current Iadd. One electrode of the transistor M1 may be connected to the high level voltage source PVDD, and a gate electrode and a drain electrode of the transistor M1 may be connected to the node NX. The transistor M1 may be implemented as a PMOS transistor. One electrode of the transistor M2 may be connected to the low level voltage source VSSH, and a gate electrode and a drain electrode of the transistor M2 may be connected to the node NY. A gate electrode of the transistor M3 may be connected to the node NY, a drain electrode of the transistor M3 may be connected to the node NX, and a source electrode of the transistor M3 may be connected to the low level voltage source VSSH. Each of the transistors M2 and M3 may be implemented as an NMOS transistor.
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The mirroring current level setting unit XX may set a level of a mirroring current Iadd, based on a current level setting signal ISEL further included in a current mirror control information CON. A level of the mirroring current Iadd may determine a response time of each of mirror transistors MF and MR, and thus, a level of the mirroring current Iadd may need to be adjusted so that an appropriate level is selected based on a model and a spec. The mirroring current level setting unit XX may be based thereon.
The mirroring current level setting unit XX may include a reference current source RCS which is connected between a high level voltage source PVDD and a low level voltage source VSSH to generate a reference current Iref and a current adjusters A1 to A4 which amplify the reference current Iref to vary a level of the mirroring current Iadd.
Channel capacities of transistors A1 to A4 configuring the current adjuster may differ, and for example, a channel capacity of a fourth transistor A4 may be greater than that of a first transistor A1.
A current level setting signal ISEL may include, for example, four logic combination values LL, LH, HL, and HH as in
Transistors B1 to B4, C1, and C2 undescribed with reference to
In a liquid crystal display (LCD) apparatus, when a target data voltage is higher than a common voltage Vcom, a polarity of the target data voltage may be positive (+), and when the target data voltage is lower than the common voltage Vcom, a polarity of the target data voltage may be negative (−). In a voltage range of a data voltage, a positive (+) polarity may relatively be within a high voltage range RG1, and a negative (−) polarity may relatively be within a low voltage range RG2.
In a case where an output amplifier is implemented as a single type, as in
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The timing controller may set first control information CTR_1 for selecting a first current mirror or a second current mirror of an output amplifier, based on a positive (+) sign or a negative (−) sign of the amount of data transition “DATA_Δ” (S30). When the amount of data transition “DATA_Δ” is positive (+) (DATA_Δ>0), the timing controller may determine a transition direction of output data of a corresponding subpixel as a rising direction, and when the amount of data transition “DATA_Δ” is negative (−) (DATA_Δ<0), the timing controller may determine the transition direction of the output data of the corresponding subpixel as a falling direction. Accordingly, the timing controller may set the first control information CTR_1 which denotes the transition direction of the output data, and the first control information CTR_1 may be decoded by a source driver IC and may thus be a criterion for selecting a first current mirror or a second current mirror of an output amplifier.
When the transition direction of the output data is determined, the timing controller may set second current control information CTR_2 which determines an on time of a first current mirror or a second current mirror, based on a magnitude of the amount of data transition “DATA_Δ” (S40). The timing controller may set the on time to increase as the amount of data transition “DATA_Δ” increases, thereby enhancing a charging/discharging characteristic. Accordingly, the timing controller may set second current control information CTR_2 so that an on time of a current mirror is set based on the amount of data transition “DATA_Δ”, and when the amount of data transition “DATA_Δ” is less than or equal to a threshold value, the timing controller may set second current control information CTR_2 so that a corresponding current mirror is disabled.
The timing controller may format current mirror control information CON, including the first current control information CTR_1 and the second current control information CTR_2 about subpixel-based RGB data, into EPI transfer data and may transfer the EPI transfer data to a source driver IC (S50).
Referring to
When the amount of data transition “DATA_Δ” is positive (+) (DATA_Δ>0), the timing controller may set the first control information CTR_1 to ‘01’ or‘1’ (S310).
When the amount of data transition “DATA_Δ” is negative (−) (DATA_Δ<0), the timing controller may set the first control information CTR_1 to ‘10’ or ‘0’ (S320).
The timing controller may output the first control information CTR_1 to an EPI formatter to reflect in the EPI transfer data (S330).
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The timing controller may determine whether the amount of data transition “DATA_Δ” is less than or equal to the first reference value VTH1 (S400). The first reference value VTH1 may be a grayscale value represented by 3 bits and may be set within a grayscale range of 16 to 96.
When the amount of data transition “DATA_Δ” is less than or equal to the first reference value VTH1 (DATA_Δ_≤VTH1), the timing controller may set the second control information CTR_2 to ‘00’ (CTR_2=00) (S405).
When the amount of data transition “DATA_Δ” is greater than the first reference value VTH1, the timing controller may determine whether the amount of data transition “DATA_Δ” is less than or equal to the second reference value VTH2 (S410). The second reference value VTH2 may be a grayscale value represented by 3 bits and may be set within a grayscale range of 104 to 160.
When the amount of data transition “DATA_Δ” is less than or equal to the second reference value VTH2 (VTH1<DATA_Δ_VTH2), the timing controller may set the second control information CTR_2 to ‘01’ (CTR_2=01) (S415).
When the amount of data transition “DATA_Δ” is greater than the second reference value VTH2, the timing controller may determine whether the amount of data transition “DATA_Δ” is less than or equal to the third reference value VTH3 (S420). The third reference value VTH3 may be a grayscale value represented by 3 bits and may be set within a grayscale range of 168 to 224.
When the amount of data transition “DATA_Δ” is less than or equal to the third reference value VTH3 (VTH2<DATA_Δ<VTH3), the timing controller may set the second control information CTR_2 to ‘10’ (CTR_2=10) (S425).
When the amount of data transition “DATA_Δ” is greater than the third reference value VTH3, the timing controller may set the second control information CTR_2 to ‘11’ (CTR_2=11) (S430).
The timing controller may output the second control information CTR_2 to the EPI formatter to reflect in the EPI transfer data (S440).
Referring to
Moreover, the second control information CTR_2 transferred as ‘01’ through the EPI transfer data may be decoded in the source driver IC and may be a criterion for setting an on time of the current mirror to 100%.
Moreover, the second control information CTR_2 transferred as ‘10’ through the EPI transfer data may be decoded in the source driver IC and may be a criterion for setting the on time of the current mirror to 120%.
Moreover, the second control information CTR_2 transferred as ‘11’ through the EPI transfer data may be decoded in the source driver IC and may be a criterion for setting the on time of the current mirror to 150%.
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The present embodiment may realize the following effects.
In the present embodiment, a current mirror of an amplifier circuit may be selectively enabled on an output channel where the degree of data transition is large, and thus, a data charging/discharging speed of the amplifier circuit may increase even without an increase in power consumption.
In the present embodiment, a rising current mirror or a falling current mirror may be selectively enabled in a direction of pixel-based data transition, and an enable time of a current mirror may be adjusted based on a magnitude of data transition, thereby more enhancing a data charging/discharging speed of the amplifier circuit.
In the present embodiment, the same mirroring current may be applied to a first current mirror and a second current mirror in a mirroring current generator, thereby preventing an output asymmetric problem between a rising output and a falling output occurring when enhancing an output slew rate of the amplifier circuit.
In the present embodiment, because a timing controller may transfer current mirror control information to a source driver IC by using an EPI protocol, a separate transfer line for transferring the current mirror control information may be omitted.
The effects according to the present disclosure are not limited to the above examples, and other various effects may be included in the specification.
While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0117534 | Sep 2023 | KR | national |
