The following disclosure relates to a display device, and more specifically to a display device having two or more display regions.
In recent years, regarding a display device such as an organic EL display device and a liquid crystal display device, an increase in resolution and an increase in the size of a screen have advanced. Due to this, a panel load is large compared with that of a known configuration, increasing power consumption. Moreover, to improve display quality, an increase in luminance is advancing. In terms of this, too, power consumption increases. Further, with the advancement of an increase in resolution, drive time per line is reduced, and in order to implement the reduction in drive time, there is a need to improve the ability of a drive circuit (e.g., an LSI), which leads to an increase in power consumption. Regarding a display device, power consumption has increased as described above, and thus, an increase in the size of the drive circuit and an increase in the performance of peripheral parts are required. Such requirements are particularly remarkable in a display device used for virtual reality (VR) (e.g., a head mounted display). However, an increase in the size of the drive circuit and an increase in the performance of peripheral parts are big factors in cost increase.
In relation to this matter, Japanese Laid-Open Patent Publication No. 2003-344823 and Japanese Laid-Open Patent Publication No. 2009-276547 disclose display devices having a configuration in which switching elements whose on/off is controlled by a control signal are provided on data signal lines (source bus lines). In such a configuration, when a switching element is turned off, a data signal line on one side with respect to the position of the switching element (hereinafter, referred to as “first line”.) and a data signal line on the other side (hereinafter, referred to as “second line”) go into an electrically disconnected state. Here, assuming that a source driver is directly connected to the first line, when a data signal is written into a pixel circuit connected to the first line, the switching element is turned off. At this time, a wiring load on the data signal line is reduced compared with that of a configuration in which the switching elements are not provided on the data signal lines. By this, power consumption related to driving of the data signal lines is reduced.
[Patent Document 1] Japanese Laid-Open Patent Publication No. 2003-344823
[Patent Document 2] Japanese Laid-Open Patent Publication No. 2009-276547
Meanwhile, in recent years, for example, in order to achieve an improvement in display quality upon display of a moving image/an increase in frame rate has advanced. In addition, regarding a display device including a touch panel, in order to increase the accuracy of touch detection, there is a demand for the securing of a sufficiently long period for touch detection during a period during which drive operation for display is not performed. From the above-described facts, there is a problem about the reduction in drive time per scanning signal line over that of a known configuration. Neither of Japanese Laid-Open Patent Publication No. 2003-344823 and Japanese Laid-Open Patent Publication No. 2009-276547 mentions the reduction in drive time of the scanning signal lines.
An object of the following disclosure is therefore to implement a display device that can reduce drive time per scanning signal line compared to the known configuration while reducing power consumption.
A display device according to some embodiments of the present disclosure is a display device that displays an image by writing a data signal into a plurality of pixel circuits arranged in a display panel, wherein
A display device according to some other embodiments of the present disclosure is a display device that displays an image by writing a data signal into a plurality of pixel circuits arranged in a display panel, wherein
A display device according to some still other embodiments of the present disclosure is a display device chat displays an image by writing a data signal into a plurality of pixel circuits arranged in a display panel, wherein
According to some embodiments of the present disclosure, in a display device, two display regions (a first display region and a second display region) are provided in a display panel. Further, in the display panel there is provided a first switching element that controls a state of electrical connection between a first data signal line disposed in the first display region and a second data signal line disposed in the second display region, and a first switching signal is provided to a control terminal of the first switching element. Thus, by changing the level of the first switching signal, on/off of the first switching element can be controlled. Here, since a data signal line drive circuit is provided at one edge of the second display region, when writing of a data signal into pixel circuits in the second display region is performed, the first data signal line and the second data signal line can be brought into an electrically disconnected state by turning off the first switching element. By this, wiring loads on data signal lines upon writing the data signal into the pixel circuits in the second display region are reduced over those of an original configuration, reducing power consumption compared with that of a known configuration. In addition, when the wiring loads on the data signal lines are reduced over those of the original configuration, a data signal writing period can be reduced to the extent that problems concerning display do not occur. That is, drive time per scanning signal line can be reduced over that of the known configuration. As described above, a display device is implemented that can reduce drive time per scanning signal line compared to the known configuration while reducing power consumption.
According to some other embodiments of the present disclosure, in a display device in which two switchable modes are prepared, drive time per scanning signal line can be reduced compared to the known configuration while reducing power consumption.
Embodiments will be described below with reference to the accompanying drawings. Note that in the following, N and J are assumed to be integers greater than or equal to 2, M is assumed to be an integer greater than or equal to 4, p is assumed to be an integer between 1 and H, inclusive, and q is assumed to be an integer between 1 and J, inclusive.
[1.1 Functional Configuration]
In the display unit 200 there are disposed J data signal lines SL(1) to SL(J) and M scanning signal lines GL(1) to GL(M) orthogonal to the J data signal lines SL(1) to SL(J). Moreover, in the display unit 200, M light emission control lines EM(1) to EM (M) are disposed so as to have a one-to-one correspondence with the M scanning signal lines GL(1) to GL(M). The scanning signal lines GL(1) to GL(M) and the light emission control lines EM(1) to EM(M) are typically parallel to each other. Furthermore, in the display unit 200, M×J pixel circuits 20 are provided at intersecting portions of the J data signal lines SL(1) to SL(J) and the M scanning signal lines GL(1) to GL(M). By thus providing the M×J pixel circuits 20, a pixel matrix of M rows×J columns is formed in the display unit 200. In the following, scanning signals provided to the respective M scanning signal lines GL(1) to GL(M) are also given reference characters GL(1) to GL(M), light emission control signals provided to the respective M light emission control lines EM(1) to EM(M) are also given reference characters EM(1) to EM(M), and data signals provided to the respective J data signal lines SL(1) to SL(J) are also given reference characters SL(1) to SL(J), as necessary. Note that the display unit 200 of the present embodiment includes two display regions (a first display region and a second display region), the detailed description of which will be made later.
In the display unit 200 there are also disposed power supply lines (not shown) common to the pixel circuits 20. More specifically, there are disposed a power supply line (hereinafter, referred to as “high-level power supply line”) that supplies a high-level power supply voltage ELVDD for driving organic EL light-emitting elements (hereinafter, referred to as “organic EL element”., a power supply line (hereinafter, referred to as “low-level power supply line”) that supplies a low-level power supply voltage ELVSS for driving the organic EL elements, and a power supply line (hereinafter, referred to as “initialization power supply line”) that supplies an initialization voltage Vini. The high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini are supplied from a power supply circuit which is not shown.
The operation of each component shown in
The gate driver 300 is connected to the M scanning signal lines GL(1) to GUM). The gate driver 300 applies scanning signals to the M scanning signal lines GL(1) to GL(m), based on the gate control signals GCTL outputted from the display control circuit 100.
The emission driver 400 is connected to the M light emission control lines EM(1) to EM(M). The emission driver 400 applies light emission control signals to the M light emission control lines EM(1) to EM(M), based on the emission driver control signals EMCTL outputted from the display control circuit 100.
The source driver 500 includes a J-bit shift register, a sampling circuit, a latch circuit, J D/A converters, etc., which are not shown. The shift register has J cascade-connected registers. The shift register sequentially transfers a pulse of the source start pulse signal supplied to a register at an initial stage, from an input terminal to an output terminal, based on the source clock signal. According to the transfer of the pulse, a sampling pulse is outputted from each stage of the shift register. Based on the sampling pulse, the sampling circuit stores a digital video signal DV. The latch circuit captures and holds digital video signals DV for one row which are stored in the sampling circuit, in accordance with the latch strobe signal. The D/A converters are provided so as to correspond to the respective data signal lines SL(1) to SL(J). The D/A converters convert the digital video signals DV held in the latch circuit into analog voltages. The converted analog voltages are simultaneously applied, as data signals, to all data signal lines SL(1) to SL(J).
In the above-described manner, the data signals are applied to the J data signal lines SL(1) to SL(J), the scanning signals are applied to the M scanning signal lines GL(1) to GL(M), and the light emission control signals are applied to the M light emission control lines EM(1) to EM(M), by which an image based on the input image signal DIN is displayed on the display unit 200.
<1.2 Display Unit>
Next, with reference to
In the connection control part 250 between the first display region 210 and the second display region 220, a switching signal line SWL extending in parallel to the M scanning signal lines GL(1) to GL(M) is disposed so as to intersect the J data signal lines SL(1) to SL(J). Furthermore, the connection control part 250 includes J switches (analog switches) 252 provided at intersecting portions of the J data signal lines SL(1) to SL(J) and the switching signal line SWL. By the switches 252, first switching elements are implemented. First data signal lines SLa(l) to SLa(J); and second data signal lines SLb(1) to SLb(J) are connected to each other through their corresponding switches 252. The switching signal line SWL transmits a switch control signal SWCTL that controls on/off of the J switches 252. Each switch 252 is connected at its control terminal to the switching signal line SWL, connected at its first conductive terminal to a corresponding first data signal line SLa through a contact hole, and connected at its second conductive terminal to a corresponding second data signal line SLb through a contact hole. By such a configuration, the switch 252 functions to control a state of electrical connection between the first data signal line SLa and the second data signal line SLb. Note that the organic EL panel 6 may be foldable, and the connection control part 250 may be provided at a folding portion of the organic EL panel 6.
The M scanning signal lines GL(1) to GL(M) include, as shown in
Note that, typically, a semiconductor layer of the switch 252 is formed in the same layer as a semiconductor layer that forms the pixel circuit 20, and using the same material as the semiconductor layer that forms the pixel circuit 20. In the present embodiment, the switch 252 is implemented by a p-channel thin-film transistor (TFT). Note, however, that the configuration is not limited thereto, and the switch 252 may be implemented by an element other than a p-channel thin-film transistor.
<1.3 Pixel Circuits>
Next, the configuration and operation of the pixel circuit 20 in the display unit 200 will be described. Note that the configuration of the pixel circuit 20 shown here is an example and the configuration is not limited thereto.
The initialization transistor T1 is connected at its control terminal to a scanning signal line GL(p−1) in a (p−1)th row, connected at its first conductive terminal to a second conductive terminal of the threshold voltage compensation transistor T2, a control terminal of the drive transistor T4, and a second electrode of the holding capacitor C1, and connected at its second conductive terminal to the initialization power supply line. The threshold voltage compensation transistor 72 is connected at its control terminal to a scanning signal line GL(p) in a pth row, connected at its first conductive terminal to a second conductive terminal of the drive transistor T4 and a first conductive terminal of the light emission control transistor T6, and connected at its second conductive terminal to the first conductive terminal of the initialization transistor 71, the control terminal of the drive transistor 14, and the second electrode of the holding capacitor C1. The write control transistor T3 is connected at its control terminal to the scanning signal line GL(p) in the pth row, connected at its first conductive terminal to a data signal line SL(q) in a qth column, and connected at its second conductive terminal to a first conductive terminal of the drive transistor T4 and a second conductive terminal of the power supply control transistor T5. The drive transistor T4 is connected at its control terminal to the first conductive terminal of the initialization transistor T1, the second conductive terminal of the threshold voltage compensation transistor T2, and the second electrode of the holding capacitor C1, connected at its first conductive terminal to the second conductive terminal of the write control transistor T3 and the second conductive terminal of the power supply control transistor T5, and connected at its second conductive terminal to the first conductive terminal of the threshold voltage compensation transistor T2 and the first conductive terminal of the light emission control transistor T6.
The power supply control transistor T5 is connected at its control terminal to a light emission control line EM (p) in the pth row, connected at its first conductive terminal to a high-level power supply line and a first electrode of the holding capacitor C1, and connected at its second conductive terminal to the second conductive terminal of the write control transistor T3 and the first conductive terminal of the drive transistor T4. The light emission control transistor T6 is connected at its control terminal to the light emission control line EM(p) in the pth row, connected at its first conductive terminal to the first conductive terminal of the threshold voltage compensation transistor T2 and the second conductive terminal of the drive transistor T4, and connected at its second conductive terminal to a first conductive terminal of the anode control transistor T7 and an anode terminal of the organic EL element 21. The anode control transistor T7 is connected at its control terminal to a scanning signal line GL(p) in the pth row, connected at its first conductive terminal to the second conductive terminal of the light emission control transistor T6 and the anode terminal of the organic EL element 21, and connected at its second conductive terminal to the initialization power supply line. The holding capacitor C1 is connected at its first electrode to the high-level power supply line and the first conductive terminal of the power supply control transistor T5, and connected at its second electrode to the first conductive terminal of the initialization transistor T1, the second conductive terminal of the threshold voltage compensation transistor T2, and the control terminal of the drive transistor T4. The organic EL element 21 is connected at its anode terminal to the second conductive terminal of the light emission control transistor T6 and the first conductive terminal of the anode control transistor T7, and connected at its cathode terminal to the low-level power supply line.
At time t0, the light emission control signal EM(p) changes from the low level to a high level. By this, the power supply control transistor T5 and the light emission control transistor T6 go into an off state. As a result, the supply of a current to the organic EL element 21 is interrupted, and the organic EL element 21 goes Into a turn-off state.
At time t1, the scanning signal GL(p−1) changes from the high level to a low level. By this, the initialization transistor T1 goes into an on state. As a result, a gate voltage of the drive transistor T4 is initialized. That is, the gate voltage of the drive transistor T4 becomes equal to an initialization voltage Vini.
At time t2, the scanning signal GL(p−1) changes from the low level to the high level. By this, the initialization transistor T1 goes into an off state. In addition, at time t2, the scanning signal GL(p) changes from the high level to a low level. By this, the threshold voltage compensation transistor T2, the write control transistor T3, and the anode control transistor T7 go into an on state. By the anode control transistor T7 going into an on state, an anode voltage of the organic EL element 21 is initialized based on the initialization voltage Vini. Further, by the threshold voltage compensation transistor T2 and the write control transistor T3 going into an on state, a data signal SL(q) is provided to the second electrode of the holding capacitor C1 through the write control transistor 73, the drive transistor 74, and the threshold voltage compensation transistor 72. By this, the holding capacitor C1 is charged.
At time t3, the scanning signal GL(p) changes from the low level to the high level. By this, the threshold voltage compensation transistor T2, the write control transistor T3, and the anode control transistor T7 go into an off state.
At time t4, the light emission control signal EM(p) changes from the high level to the low level. By this, the power supply control transistor T5 and the light emission control transistor T6 go into an on state. By this, a drive current based on the charged voltage of the holding capacitor C1 is supplied to the organic EL element 21. As a result, the organic EL element 21 emits light depending on the magnitude of the drive current. Thereafter, the organic EL element 21 emits light throughout a period up to when the light emission control signal EM(p) changes from the low level to the high level at time t10.
<1.4 Regarding Driving Of The Data Signal Lines>
Meanwhile, regarding driving of the data signal lines, it is also possible to adopt a drive scheme called “SSD” in which an output (i.e., a data signal) from the source driver 500 is shared between a plurality of data signal lines. Note that the “SSD” is an abbreviation of “source shared driving”.
In a configuration such as that described above, as shown in
By adopting the SSD such as that described above, the number of data signal lines SL to be disposed in a picture-frame region is reduced, and thus, even if an increase in resolution advances, an increase of the picture-frame region can be suppressed.
<1.5 Drive Method For The Organic EL Panel>
<1.5.1 Control of the Switches in the Connection Control Part>
During the first vertical scanning period Ta, as shown in
During the second vertical scanning period Tb, as shown in
As described above, during the first vertical scanning period Ta, data signals need to be supplied to the first data signal lines SLa (data signal lines in the first display region 210), and thus, by bringing the switches 252 into an on state, the first data signal lines SLa and the second data signal lines SLb go into an electrically connected state. During the second vertical scanning period Tb, there is no need to supply data signals to the first data signal lines SLa, and thus, in order to reduce wiring loads, by bringing the switches 252 into an off state, the first data signal lines SLa and the second data signal lines SLb go into an electrically disconnected state.
<1.5.2 Details>
Here, it is assumed that the number of scanning signal lines GL and the number of light emission control lines EM are 16, scanning signal lines GL(1) to GL(8) and light emission control lines EM(1) to EM(8) are disposed in the first display region 210, and scanning signal lines GL(9) to GL(16) and light emission control lines EM(9) to EM(16) are disposed in the second display region 220 (the same also applies to the second to fourth embodiments). That is, the scanning signal lines GL(1) to GL (8) are first scanning signal lines, and the scanning signal lines GL(9) to GL(16) are second scanning signal lines. As such, although description will be made using an example in which the switches 252 are provided such that the number of first scanning signal lines is equal to the number of second scanning signal lines, the configuration is not limited thereto, and the switches 252 may be provided such that the number of first scanning signal lines differs from the number of second scanning signal lines. Note that in
Regarding
As can be grasped from
Here, we focus on a first vertical scanning period Ta. During the first vertical scanning period Ta, the scanning signals GL(1) to GL(8) sequentially go to a low level for a predetermined period. By this, during the first vertical scanning period Ta, writing of data signals into pixel circuits 20 in the first display region 210 is performed. At this time, the switch control signal SWCTL is at the low level. Hence, the switches 252 in the connection control part 250 are in an on state. Thus, the first data signal lines SLa and the second data signal lines SLb are in an electrically connected state, and data signals are supplied to the first data signal lines SLa from the source driver 500 through the second data signal lines SLb.
Next, we focus on a second vertical scanning period Tb. During the second vertical scanning period Tb, the scanning signals GL(9) to GL(16) sequentially go to a low level for a predetermined period. By this, during the second vertical scanning period Tb, writing of data signals into pixel circuits 20 in the second display region 220 is performed. At this time, the switch control signal SWCTL is at a high level. Hence, the switches 252 in the connection control part 250 are in an off state. Thus, the first data signal lines SLa and the second data signal lines SLb are in an electrically disconnected state, and wiring loads on the data signal lines SL are remarkably smaller than those of the original configuration.
As described above, when the gate driver 300 applies an on-level (here, low level) scanning signal to any of the first scanning signal lines GL(1) to GL(8), the switches 202 in the connection control part 250 are turned on, and when the gate driver 300 applies an on-level scanning signal to any of the second scanning signal lines GL(9) to GL(16), the switches 252 in the connection control part 250 are turned off. Further, when a period during which an on-level scanning signal is applied to each of the first scanning signal lines so that data signals are written into pixel circuits 20 included in the first display region 210 is defined as “first writing period”, and a period during which an on-level scanning signal is applied to each of the second scanning signal lines so that data signals are written into pixel circuits 20 included in the second display region 220 is defined as “second writing period”, the gate driver 300 sets a second writing period TW2 shorter than a first writing period TW1 (see
As can be grasped from
Now, a difference between a vertical period of the known configuration and a vertical period of the present embodiment will be described.
As shown in
Meanwhile, according to the present embodiment, the length of a light emission period of the organic EL element 21 in the pixel circuit 20 varies depending on the row, which will be described below. As described above, in each pixel circuit 20, the organic EL element 21 emits light during a period from when the light emission control signal EM(p) is changed from the high level to the low level until when the light emission control signal EM(p) changes from the low level to the high level (see
First, the first exemplary measures will be described. In this example, the voltage value of a data signal (the value of a voltage applied to a data signal line SL) is corrected so that in a pixel circuit 20 included in a row with a short light emission period, a large drive current compared with that of a pixel circuit 20 included in a row with a long light emission period flows through an organic EL element 21. Regarding this, the source driver 500 generates a data signal based on a digital video signal DV transmitted from the display control circuit 100. Accordingly, correction of the voltage value of the data signal is implemented by the display control circuit 100 correcting the value of the digital video signal DV.
Next, the second exemplary measures will be described. In this example, instead of driving the light emission control lines EM(1) to EM(M) by the emission driver 400 based on the emission start pulse signal EMSP and emission clock signals EMCK1 and EMCK2, the display control circuit 100 directly provides light emission control signals to all light emission control lines EM(1) to EM5M). Regarding this, the display control circuit 100 allows the light emission control signals to be maintained at a low level for a period of the same length in all light emission control lines EM(1) to EM(M). By this, the light emission periods for all rows have the same length. Note, however, that in this example, there are required M signal lines (signal lines through which light emission control signals are transmitted) that connect the display control circuit 100 to each of the light emission control lines EM(1) to EM(M) in the display unit 200. Thus, this example is not suitable for a high-resolution display device.
<1.6 Effects>
According to the present embodiment, in an organic EL display device, in the display unit 200 there are provided the first display region 210 and the second display region 220 which are two display regions, and there are provided the switches 252 for controlling states of electrical connection between data signal lines disposed in the first display region 210 (the first data signal lines SLa) and data signal lines disposed in the second display region 220 (the second data signal lines SLb) The on/off of the switches 252 is controlled by a switch control signal SWCTL transmitted from the display control circuit 100. When data signals are written into pixel circuits 20 included in the first display region 210, the switches 2S2 are turned on, and when data signals are written into pixel circuits 20 included in the second display region 220, the switches 252 are turned off. Meanwhile, in general, power consumption required to charge and discharge data signal lines is proportional to the product of drive frequency, loads (wiring loads) on the data signal lines, the voltage amplitudes of data signals, and the number of the data signal lines. When data signals are written into pixel circuits 20 included in the first display region 210, due to the provision of the switches 252, a wiring load on each data signal line is larger than that of the original configuration. However, when data signals are written into pixel circuits 20 included in the second display region 220, the first data signal lines SLa and the second data signal lines SLb are in an electrically disconnected state, and thus, a wiring load on each data signal line is smaller than that of the original configuration. Power consumption reduced thereby is larger than power consumption that increases with the increase in wiring loads upon writing of data signals into the pixel circuits 20 included in the first display region 210. Thus, power consumption as a whole is reduced compared with that of the known configuration. In addition, when data signals are written into the pixel circuits 20 included in the second display region 220, a wiring load on each data signal line is smaller than that of the original configuration, and thus, a data signal writing period can be reduced to the extent that problems concerning display do not occur. Hence, in the present embodiment, as described above, a second writing period (a data writing period in a second vertical scanning period Tb) TW2 is shorter than a first writing period (a data writing period in a first vertical scanning period Ta) TW1. As a result, drive time per scanning signal line is shorter than that of the known configuration. As above, according to the present embodiment, a display device is implemented that can reduce drive time per scanning signal line compared to the known configuration while reducing power consumption.
In addition, by the reduction in power consumption, the following effects are expected. First, miniaturization of the source driver 500 which is implemented by an LSI, etc., and cost reduction associated therewith are expected. Moreover, in mobile phones, etc., usable hours after charging are extended. Furthermore, since it becomes possible to miniaturize a battery used in a device, flexibility in the design of the device improves, and implementation of appealing designs is expected. Moreover, radiation noise iron a display device is reduced. Furthermore, since it becomes possible to maintain drive voltage at a high level, extension of a dynamic range or an increase in the amplitudes of gate control signals GCTL can be achieved.
A second embodiment will be described. Note, however, that the following mainly describes differences from the first embodiment.
<2.1 Summary>
A functional configuration of an organic EL display device, a configuration of the display unit 200, a configuration of the pixel circuits 20, and control of the switches 252 in the connection control part 250 are the same as those of the above-described first embodiment. In the first embodiment, a vertical period is short compared with that of the known configuration. On the other hand, a vertical period of the present embodiment has the same length as the vertical period of the known configuration. A drive method of the present embodiment will be described below.
<2.2 Drive Method for the Organic EL Panel>
As can be grasped from
<2.3 Effects>
According to the present embodiment, as in the first embodiment, a display device is implemented that can reduce drive time per scanning signal line compared to the known configuration while reducing power consumption. In addition, the vertical flyback period TF is long compared with that of the known configuration (see
<3.1 Summary>
A functional configuration of an organic EL display device, a configuration of the display unit 200, a configuration of the pixel circuits 20, and control of the switches 252 in the connection control part 250 are the same as those of the above-described first embodiment. In the first embodiment, a second vertical scanning period Tb is shorter than a first vertical scanning period Ta. On the other hand, in the present embodiment, a second vertical scanning period Tb has the same length as a first vertical scanning period Ta. Further, in the first embodiment, a vertical period is short compared with that of the known configuration. On the other hand, as in the second embodiment, a vertical period of the present embodiment has the same length as the vertical period of the known configuration. A drive method of the present embodiment will be described below.
<3.2 Drive Method for the Organic EL Panel>
Meanwhile, as shown in
<3.3 Effects>
According to the present embodiment, as in the first embodiment, a display device is implemented that can reduce drive time per scanning signal line compared to the known configuration while reducing power consumption. In addition, the second writing period TW2 is shorter than the first writing period TW1, and the first writing period TW1 has the same length as the data writing period of the known configuration. That is, the second writing period TW2 is shorter than the data writing period of the known configuration. Thus, the length of a horizontal flyback period in the second vertical scanning period Tb is longer by a period TK of
<4.1 Summary>
In the above-described first to third embodiments, a wiring load on the switching signal line SWL (see
<4.2 Drive Method for an Organic EL Panel>
Here, as shown in
Meanwhile, by the provision of the transition period TS whose length corresponds to one horizontal scanning period, compared with a case in which the transition period TS is not provided, scanning timing of each of the second scanning signal lines GL(9) to GL(16) (timing at which each scanning signal changes from a high level to a low level) and output timing of data signals for each row from the source driver 500 in the second vertical scanning period Tfc are shifted by one horizontal scanning period. Hence, in the present embodiment, a vertical flyback period is short compared with that in a case in which the transition period TS is not provided. Thus, as shown in
Note that the length of the transition period TS is not limited to a length corresponding to one horizontal scanning period, and any transition period TS may be provided as long as the transition period TS has a sufficient length for changing on/off of the switches 252 in the connection control part 250.
(4.3 Effects)
According to the present embodiment, a display device is implemented that can reduce drive time per scanning signal line compared to the known configuration while reducing power consumption, without causing a display failure resulting from insufficient charging, etc., even in a case in which a wiring load on the switching signal line SWL is large.
<5.1 Summary>
A functional configuration of an organic EL display device, a configuration of the display unit 200, a configuration of the pixel circuits 20, and control of the switches 252 in the connection control part 250 are the same as those of the above-described first embodiment. In the organic EL display device according to the present embodiment, as display modes, there are prepared a first node (low-speed mode) in which drive frequency is a first frequency, and a second mode (high-speed mode) in which drive frequency is a second frequency higher than the first frequency. As shown in
In both the first mode and the second mode, during the first vertical scanning period (a period during which writing of data signals into pixel circuits 20 included in the first display region 210 is performed) Ta, a switch control signal SWCTL is maintained at a low level, by which the switches 252 in the connection control part 250 are maintained in an on state, and during the second vertical scanning period (a period during which writing of data signals into pixel circuits 20 included in the second display region 220 is performed) Tb, the switch control signal SWCTL is maintained at a high level, by which the switches 252 in the connection control part 250 are maintained in an off state. Thus, in both the first mode and the second mode, during the second vertical scanning period Tb, writing of data signals into the pixel circuits 20 is performed with wiring loads on the data signal lines SL being smaller than those of the original configuration (the known configuration in which the switches 252 are not provided).
When the wiring loads are smaller than those of the original configuration, the length of a writing period can be reduced compared to the original configuration. However, as described above, in the first mode, the second writing period TW2 has the same length (i.e., the original length) as the first writing period TW1. This fact can cause a difference between a charging rate for the first display region 210 and a charging rate for the second display region 220 in the first mode. Hence, in the present embodiment, in the first node, bias currents of output amplifiers in the source driver 500 are adjusted. Specifically, in the first mode, in the second vertical scanning period Tb, the bias currents are reduced compared with those in the first vertical scanning period Ta.
<5.2 For Components Related to the Adjustment to the Bias Currents>
Components related to the adjustment to the bias currents will be described below.
Next, a configuration of an output amplifier provided for one source bus line SL will be described. As shown in
The operational amplifier 522 includes, for example, a differential amplifier 5220 having a configuration such as that shown in
<5.3 Effects>
According to the present embodiment, in the second mode (high-speed mode), the same driving as that of any of the first to fourth embodiments is performed. Hence, in the second mode, while power consumption is reduced, drive time per scanning signal line can be reduced cox-cared to the known configuration. In addition, in the first mode (low-speed mode), in the second vertical scanning period Tb, the magnitude of bias currents of the output amplifiers in the source driver 500 is reduced over that in the first vertical scanning period Ta. Hence, in the first node, too, power consumption is reduced compared to the known configuration.
Although two display regions (the first display region 210 and the second display region 220) are provided in the display unit 200 in each of the above-described embodiments, the configuration is not limited thereto, and three or more display regions may be provided in the display unit 200. An example in which three display regions (the first display region 210, the second display region 220, and a third display region 230) are provided in the display unit 200 will be described below as a variant.
As in the above-described first embodiment, the connection control part 250 is provided between the second display region 220 and the first display region 210, and the switches 252 for controlling states of electrical connection between the second data signal lines SLb and the first data signal lines SLa are provided in the connection control part 250. Note that in the present variant, the connection control part 250 is referred to as “first connection control part”, a signal that controls on/off of the switches 252 is referred to as “first switch control signal”, and a signal line through which the first switch control signal is transmitted is referred to as “first switching signal line”.
In addition, as shown in
In the present variant, in an effective vertical scanning period, each period appears in the order of “a third vertical scanning period (a period during which writing of data signals into pixel circuits 20 included in the third display region 230 is performed by sequentially applying an on-level scanning signal to the plurality of third scanning signal lines) Tc, a first vertical scanning period Ta, and a second vertical scanning period Tb”. Part A of
Under presumption such as that described above, as shown in
Moreover, during the first vertical scanning period Ta, the first switch control signal SWCTL1 is at a low level and the second switch control signal SWCTL2 is at a high level. Hence, the switches 252 are in an on state and the switches 262 are in an off state. By this, the second data signal lines SLb and the first data signal lines SLa are electrically connected to each other, and the first data signal lines SLa and the third data signal lines SLc go into an electrically disconnected state. As a result, data signals are supplied to the first data signal lines SLa from the source driver 500 through the second data signal lines SLb, with wiring loads on the data signal lines SL being smaller than those of the original configuration.
Furthermore, during the second vertical scanning period Tb, the first switch control signal SWCTL1 is at a high level and the second switch control signal SWCTL2 is at a high level. Hence, the switches 252 are in an off state and the switches 262 are in an off state. By this, the second data signal lines SLb are electrically disconnected from the first data signal lines SLa and the third data signal lines SLc, remarkably reducing wiring loads on the data signal lines SL over those of the original configuration. With the wiring loads on the data signal lines SL being thus remarkably reduced over those of the original configuration, data signals are supplied to the second data signal lines SLb from the source driver 500.
As above, in the present variant, too, a display device is implemented that can reduce drive time per scanning signal line compared to the known configuration while reducing power consumption.
Although description is made using an organic EL display device as an example in each of the above-described embodiments and the above-described variant, the configuration is not limited thereto, and the present disclosure can also be applied to liquid crystal display devices, inorganic EL display devices, QLED display devices, etc. In addition, the present disclosure can also be applied to display devices used for virtual reality (VR).
6: ORGANIC EL DISPLAY PANEL
20: PIXEL CIRCUIT
21: ORGANIC EL LIGHT-EMITTING ELEMENT
100: DISPLAY CONTROL CIRCUIT
200: DISPLAY UNIT
210: FIRST DISPLAY REGION
220: SECOND DISPLAY REGION
230: THIRD DISPLAY REGION
250: CONNECTION CONTROL PART (FIRST CONNECTION CONTROL PART)
252: SWITCH IN THE CONNECTION CONTROL PART (FIRST CONNECTION CONTROL PART)
260: SECOND CONNECTION CONTROL PART
262: SWITCH IN THE SECOND CONNECTION CONTROL PART
300: GATE DRIVER
400: EMISSION DRIVER
500: SOURCE DRIVER
SL, SL(1) to SL(J): DATA SIGNAL LINE
SLa, SLa(1) to SLa(J): FIRST DATA SIGNAL LINE
SLbr SLb(1) to SLb(J): SECOND DATA SIGNAL LINE
SLCf SLc(1) to SLc(J): THIRD DATA SIGNAL LINE
Filing Document | Filing Date | Country | Kind |
---|---|---|---|
PCT/JP2019/012762 | 3/26/2019 | WO |
Publishing Document | Publishing Date | Country | Kind |
---|---|---|---|
WO2020/194493 | 10/1/2020 | WO | A |
Number | Name | Date | Kind |
---|---|---|---|
6175351 | Matsuura et al. | Jan 2001 | B1 |
20050179640 | Tanaka | Aug 2005 | A1 |
20090184913 | Sato | Jul 2009 | A1 |
20090284500 | Yamashita | Nov 2009 | A1 |
20180158393 | Woo | Jun 2018 | A1 |
20190035350 | Miyata | Jan 2019 | A1 |
Number | Date | Country |
---|---|---|
H07-056143 | Mar 1995 | JP |
2003-344823 | Dec 2003 | JP |
2009-175303 | Aug 2009 | JP |
2009-276547 | Nov 2009 | JP |
2012017640 | Feb 2012 | WO |
2017141828 | Aug 2017 | WO |
Number | Date | Country | |
---|---|---|---|
20220189409 A1 | Jun 2022 | US |