Patent Application
20090102749
This application claims priority of Japanese Patent Application No. 2007-270837 filed Oct. 18, 2007 which is incorporated herein by reference in its entirety.
The present invention relates to a display device having pixels arranged in a matrix.
As organic EL displays are self-luminous so that a high contrast and a fast response can be achieved, the organic EL displays are suited for applications dealing with moving images such as TVs, which display natural images and the like. In general, multiple gray scales in organic EL elements are achieved by using control elements such as transistors to drive the organic EL elements by a constant current or a constant voltage, or by changing the light emission durations of the organic EL elements.
When the organic EL elements are driven by a constant current, the electric power consumption of transistors increases because the transistors are used in saturation regions. Therefore, the constant current driving is not suited for reducing electrical power consumption. However, when the organic EL elements are driven by a constant voltage, the power consumption of transistors can be reduced because the transistors are used in linear regions.
In digital driving, in which a constant voltage is applied, each pixel can only achieve one-bit gray scale performance. Therefore, when sub frames are used to achieve multiple gray scales, a high speed operation is required because multiple accesses to a single pixel are required for one frame period. However, in particular, when the number of pixels increases to achieve high definition display, data for sub frames must be written onto each pixel and multiple gray scales are difficult to achieve. On the other hand, even when a plurality of sub-pixels with different emission intensities are employed and digitally driven, bit data is required to be rapidly written onto the corresponding plurality of sub-pixels and high definition display is difficult to achieve.
Moreover, in either of these methods of digital driving, as the number of accesses to pixels increases when higher definition display and more multiple gray scales are required, the electric power consumption of drive circuits also increases. Specifically, the larger the display size is, the higher the electric power consumption of the drive circuits becomes. Attempts to reduce power consumption are further impeded as the frequency increases in conjunction with higher definition display.
In one aspect of the present invention, there is provided a display device including a plurality of pixels arranged in a matrix, wherein each pixel includes a plurality of sub-pixels, and the plurality of sub-pixels include a digital pixel driven by digital data and an analog pixel driven by analog data.
In another aspect of the present invention, preferably, input data is input into a hybrid data driver, and the hybrid data driver divides the input data into two pieces of data, supplies one piece of data as digital data to the digital pixel via a digital data line, and supplies the other piece of data as analog data to the analog pixel via an analog data line.
In another aspect of the present invention, the digital pixel preferably includes a static memory for storing the digital data supplied from the digital data line.
In another aspect of the invention, preferably, the digital pixel and the analog pixel are arranged in respective columns, the digital data line is provided along the column for the digital pixel, and the analog data line is provided along the column for the analog pixel.
In another aspect of the invention, preferably, the input data is digital data, the hybrid data driver includes an output register for storing the input data, and a digital processor and an analog processor for processing the input date stored in the output register, the digital processor supplies digital data based on the one piece of data of the input data to the digital data line, and the analog processor supplies analog data based on the other piece of data of the input data to the analog data line.
In another aspect of the present invention, preferably, the input data is supplied to the output register via a data register, and the data register sequentially supplies the input data for the digital pixel and the input data for the analog pixel to the output register.
With the present invention, as digital pixels can be used to achieve digital display, the electric power consumption can be reduced, while as analog pixels can be used to achieve analog display, display with multiple gray scales can be effectively achieved.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and, together with the description, serve to explain the principles of the invention, in which:
Preferred embodiments of the present invention will be described below with reference to the accompanied drawings.
Each sub-pixel 9 includes a p-channel drive transistor 2 serially connected to an organic EL element 1, a p-channel gate transistor 3, and a storage capacitor 4. The source terminal of the drive transistor 2 is connected to a power supply line 7, while the drain terminal thereof is connected to the anode of the organic EL element 1. The cathode of the organic EL element 1 is connected to a cathode electrode 8 which is shared with all the sub-pixels in the unit pixel and to which VSS is applied. In addition, the source terminal of the gate transistor 3 having the gate terminal connected to a gate line 5 and the drain terminal connected to a data line 6 is connected to one end of the storage capacitor 4 having the other end connected to the power supply line 7. The source terminal is also connected to the gate terminal of the drive transistor 2.
In each sub-pixel 9 as described above, when the gate line 5 is selected (or set to Low), a signal provided to the data line 6 is written to the storage capacitor 4. And then, after the drive transistor 2 is turned on, a current flows through the organic EL element 1, and the organic EL element 1 emits light. At this moment, the relationship between the gate voltage and the drain voltage of the drive transistor 2 determines whether the drive transistor 2 operates in a saturation region (constant current driving) or in a linear region (constant voltage driving). When the drive transistor 2 operates in the saturation region, the analog control of the drive transistor 2 can be achieved because the signals provided to the data line 6 change the current flowing through the organic EL element 1. On the other hand, when the drive transistor 2 operates in the linear region, multiple gray scales using sub frames are required because the drive transistor 2 is only controlled by the on-off operations of the drive transistor 2.
First and second sub-pixels 9-2 and 9-1 forming the unit pixel 10 shown in
A third sub-pixel 9-0 is operated by constant current driving (analog sub-pixel) because a second power supply potential VDD2 is applied to a power supply line 7-0. That is, analog signals supplied to the data line 6-0 are applied to the gate terminal of the drive transistor 2, and the current flowing through the organic EL element 1 is controlled.
For example, when six-bit digital video data is externally input, first the upper two bits of the digital video data are written onto the first and second sub-pixels 9-2 and 9-1, respectively. Next, the lower four bits of the digital video data are converted into analog signals and written onto the third sub-pixel 9-0. Thus, a six-bit gray scale display is achieved using three sub-pixels 9.
To achieve such a gray scale control as described above, the ratio of the emission intensities (maximum values) of the first, second, and third sub-pixels can be 32:16:15. As the emission intensity of the third sub-pixel is determined by the current generated by the drive transistor 2, the operating point of the transistor can be preferably set as shown in
Multiple gray scales in the third sub-pixel can be achieved by constant current driving, by setting the analog power supply potential VDD2 higher than the digital power supply potential VDD1 as shown in
As described above, the electric power consumption of the unit pixel 10 including the first, second, and third sub-pixels 9-2, 9-1, and 9-0, the emission intensity ratio of which is 32:16:15, can be calculated with reference to
On the other hand, as the electric power consumption (maximum value) of the third sub-pixel is (15/63)×I×VDD2, the electric power consumption Ph of the unit pixel 10 is Ph=I×VDD1+(15/63)×I×ΔV, provided that ΔV=VDD2−VDD1.
If all the sub-pixels are controlled by constant current driving, the electric power consumption Pa of the unit pixel 10 is Pa=I×VDD2, while if all the sub-pixels are controlled by constant voltage driving, the electric power consumption Pd of the unit pixel 10 is Pd=I×VDD1. Therefore, Pa, Pd, and Ph reduce to Pa=2×I×VDD1, Pd=I×VDD1, and Ph=(78/63)×I×VDD1=1.24×Pd, provided that ΔV=VDD (VDD2=2×VDD1). Thus, it can be understood that the electric power consumption Ph of a hybrid pixel according to an embodiment of the present invention, in which digital sub-pixels and analog sub-pixels are combined, increases by at most 24% in comparison with the electric power consumption Pd of a pixel in which all sub-pixels are driven by digital data.
In a hybrid pixel including digital sub-pixels and analog sub-pixels as shown in
Employing a greater number of sub-pixels provides some advantages, such that multiple gray scales can be achieved more easily and a lower electric power consumption of analog sub-pixels for lower bits which are controlled by a constant current can be achieved. On the other hand, the electric power consumption can be also reduced by employing sub-pixels each of which has a static memory as shown in
That is, the anode of the second organic EL element 11 having the cathode connected to a cathode electrode 8 shared with all the sub-pixels in the unit pixel and applied with VSS is connected to the drain terminal of the second drive transistor 12, the gate terminal of a first drive transistor 2, and the source terminal of a gate transistor 3. The source terminal of the second drive transistor 12 is connected to a power supply line 7.
First and second sub-pixels 9-2 and 9-1 are controlled by a first gate line 5-1, while a third sub-pixel 9-0 is controlled by a second gate line 5-0.
When the gate line 5-1 is selected and High or Low digital data is supplied to the data lines 6-2 and 6-1, the operations of the sub-pixels are determined according to the supplied data.
For example, when Low data is supplied to the gate line 5-1 and the gate line 5-1 is selected, the gate transistors 3 are turned on. Here, when Low data is supplied to the data lines 6-2 and 6-1, and the second transistors are turned on, a current flows through the first organic elements 1 so that the elements emit light. Also, the gate potentials of the second transistors 12 are increased to the first power supply potential VDD1, and the second drive transistors 12 are turned off. As the gate potentials of the first drive transistors 2 are kept at the cathode potential by the second organic EL elements 11, the same condition is maintained after the gate line 5-1 is deselected.
Similarly, when High data is supplied to the data lines 6-2 and 6-1, when the first drive transistors 2 are turned off and the potentials of the first organic EL elements 1 are decreased to the cathode potential, the second drive transistors 12 are turned on and a current flows through the second organic EL elements 11. As the second organic EL elements 11 are shaded using metal wiring, black matrix and the like, light emitted from the second organic EL elements are not released outside even when a current flows through the elements so that the contrasts of the sub-pixels are not reduced. As the gate potentials of the first drive transistors 2 are increased to the first power supply potential VDD1 by the second organic EL elements 11, the same condition is maintained after the gate line 5-1 is deselected.
As described above, in the pixel employing a static memory, video data written once is maintained even if a refresh operation is not executed, unlike in the pixel as shown in
The display system as shown in
External input data is input into the control circuit 16, and temporarily stored in the frame memory 17. When video data for the next frame is input, the control circuit 16 reads out the video data for the previous frame stored in the frame memory 17 and compares the video data with each other, and performs a control operation so as to only update the lines having some variations between the video data.
For example, when a rectangular area indicated by oblique lines moves from bottom left to top right from one frame to another as shown in
As all data between the line A and the line B is required to be updated, the control circuit 16 transmits the data for the upper two bits and the lower four bits to the hybrid data driver 15, and controls the gate driver 14 to select the first and second gate lines 5-1 and 5-0. The gate driver 14 first selects the first gate line 5-1, while the hybrid data driver 15 outputs each piece of the digital data for the upper two bits to the data lines 6-2 and 6-1, respectively.
When the writing operations to the first and second sub-pixels complete, the first gate line 5-1 is deselected and the second gate line 5-0 is selected. At this timing, the hybrid data driver 15 outputs the DA converted data for the lower four bits to the data line 6-0, and then the analog data is written onto the third sub-pixels. When this writing operation completes, the second gate line 5-0 is deselected. As there is no variation of the video data between the line B and the bottom line, the control with the same procedure as for the lines between the top line and the line A is applied to the lines between the line B and the bottom line.
As described above, unlike the unit pixel shown in
In order to write the upper two bit data onto the first and second sub-pixels, the selector 21 connects the driver output with the digital processor 19, and then the upper two bit data of the six bit data stored in the output register 18 is sequentially fetched via the decoder 22, buffered by the digital buffer 23, and output via the driver output. On the other hand, in order to write the analog data for the lower four bits onto the third sub-pixel, the selector 21 connects the driver output with the analog processor 20, and then the lower four bit data is converted into analog data by the DA converter 24, buffered by the analog buffer 25, and output via the driver output.
The decoder 22 of the digital processor 19 can fetch any bits of the six bit data stored in the output register 18. Alternatively, the decoder 22 can be used as a 64-input-1-output decoder for outputting one piece of data selected from a 64 bit table data based on the six bit data stored in the output register 18.
The DA converter 24 of the analog processor 20 can also mask any bits of the six bit data stored in the output register 18 to convert the masked data. For example, in order to apply a DA conversion only to the lower four bit data, the upper two bit data can be masked by setting “001111” to the mask data and performing an AND operation of the data in the output register and the mask data so that an analog conversion of the lower four bit data can be achieved without the influence of the upper two bit data. With this arrangement, even if there are, for example, three digital sub-pixels in a unit pixel, the table data in the digital processor 19 can be modified to output the upper three bit data without the influence of the lower three bit data. Also, setting “000111” to the mask data in the analog processor 20 can achieve a DA conversion without the influence of the upper three bit data in the output register. As such, flexible responses can be ensured in this arrangement.
Data transfer operations of the upper bits and the lower bits can be separately performed. For example, a line memory is employed in the control circuit 16 to store one line of external input data, while the upper two bit data is transferred to the hybrid data driver 15 in advance. The selector 21 then connects the driver output with the digital processor 19, the decoder 22 ignores the lower four bit data and fetches only the upper two bit data, and the data is output via the driver output. Next, the control circuit 16 transfers the lower four bit data of the one line of external input data to the hybrid data driver 15. Meanwhile, the selector 21 connects the driver output with the analog processor 20, the upper two bit data is masked, a DA conversion is applied to the data, and the converted analog data is output via the driver output.
Transferring the upper bit data and the lower bit data separately in two stages as described above makes it possible to achieve, at maximum, digital output of the upper six bit data and analog output of the lower six bit data. Therefore, the gray scale display of a total of 12 bits can be achieved. In an arrangement employing seven sub-pixels, including six digital sub-pixels and one analog sub-pixel, the upper six bit data is written onto the respective six digital sub-pixels, while the lower six bit data is written onto the analog sub-pixel. Therefore, the potential advantages of such a two-stage transfer can be fully realized.
In the structure as shown in
In addition, although the output register 18 is shared with the digital processor and the analog processor in
Furthermore, for static images, such as menu screen and text display which do not require multi-bit display, writing operations to sub-pixels with analog driving can be omitted. In that case, preferably, a precharge transistor 26, which connects a second power supply line 7-0 for a third sub-pixel which is an analog pixel with a data line 6-0, is provided around the display panel as shown in
That is, no periodic writing operation is performed to third sub-pixels 9-0, which are analog pixels. Therefore, all gate lines 5-0 and all precharge lines 27 are set to Low. Further, each of the precharge transistors 26 provided at one end of the data line 6-0 for each third sub-pixel is turned on, and the data lines 6-0 are continuously precharged with a second power supply potential VDD2. Moreover, the drive transistors 2 of the third sub-pixels 9-0 are turned off. During this precharging operation, the output of the hybrid data driver 15 is retained, or separated from the data lines 6-0 by means of a switch and the like (not shown) provided on the display array 13. With this structure, as it is not necessary for the hybrid data driver 15 to drive the data lines 6-0 while the precharge transistors 26 are turned on, the operation of the analog processor 20 can be halted. Therefore, a further electric power consumption reduction can be achieved. Also, the hybrid data driver 15 can be used to additionally control the precharge lines 27.
The invention has been described in detail with particular reference to certain preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-270837 | Oct 2007 | JP | national |
