Patent Application
20220157918
This application claims priority to Korean Patent Application No. 10-2021-0087834, filed on Jul. 5, 2021, and Korean Patent Application No. 10-2020-0155480, filed on Nov. 19, 2020, and all the benefits accruing therefrom under 35 U.S.C. § 119, the contents of which in their entirety are herein incorporated by reference.
Implementations of the invention relate generally to a display device. More particularly, implementations of the invention relate to the display device including a plurality of pads.
A display device includes a plurality of pixels and a plurality of pads. The pads are bonded to a circuit board (e.g., a driving chip or a flexible printed circuit board), and transmit signals and/or voltages to the pixels. As an adhesive (e.g., an anisotropic conductive film (“ACF”)) is applied to the pads and pressure is applied to the pads and the circuit board, the pads may be bonded to the circuit board. In order to check whether the pads are normally bonded to the circuit board, an indentation inspection process and a rework process are performed. The indentation inspection process is a process of inspecting a position of the pressure and a magnitude of the pressure. The rework process is a process of removing the circuit board and cleaning the pads.
While the rework process is performed, shapes of the pads may be deformed. For example, conductive patterns included in the pads may be pushed. As the pushed conductive patterns contact the adjacent pads, a short defect may occur between the pads.
Embodiments provide a display device including a plurality of pads.
A display device according to an embodiment includes a substrate including a pad region, a first conductive pattern disposed on the pad region of the substrate and having a quadrangle shape in a plan view, an insulating layer disposed on the substrate and covering the first conductive pattern, and a second conductive pattern disposed on the insulating layer and contacting the first conductive pattern through a plurality of contact holes defined in the insulating layer. The plurality of the contact holes is arranged along a diagonal direction of the quadrangle shape in the plan view.
According to an embodiment, the quadrangle shape may include a first side extending in a first direction and a second side extending in a second direction perpendicular to the first direction, and the diagonal direction may be between the first direction and the second direction.
According to an embodiment, a length of the first side may be less than a length of the second side.
According to an embodiment, a length of the first side may be at least three times greater than a length of each of the contact holes in the first direction.
According to an embodiment, the insulating layer may include an overlapping portion surrounding each of the contact holes and overlapping the first conductive pattern in the plan view and a non-overlapping portion surrounding the overlapping portion and which does not overlap the first conductive pattern in the plan view, and having a top which is disposed lower than a top of the overlapping portion.
According to an embodiment, a thickness of the overlapping portion may be the same as a thickness of the non-overlapping portion.
According to an embodiment, each of a thickness of the overlapping portion and a thickness of the non-overlapping portion may be about 6000 angstroms (Å) to about 7000 angstroms.
According to an embodiment, the display device may further include a third conductive pattern disposed on the second conductive pattern and directly contacting the second conductive pattern.
According to an embodiment, a material included in the second conductive pattern may be the same as a material included in the third conductive pattern.
According to an embodiment, the second conductive pattern and the third conductive pattern may each have a Ti/Al/Ti structure.
According to an embodiment, the material included in the second conductive pattern may be different from a material included in the first conductive pattern.
According to an embodiment, the first conductive pattern may include molybdenum.
According to an embodiment, the substrate may further include a display region adjacent to the pad region. The display device may further include an active pattern disposed on the substrate and overlapping the display region in the plan view, a gate electrode disposed in the same layer as the first conductive pattern and overlapping the active pattern in the plan view, a first connection electrode disposed in the same layer as the second conductive pattern and contacting the active pattern, a second connection electrode disposed in the same layer as the third conductive pattern and contacting the first connection electrode, a first electrode disposed on the second connection electrode and contacting the second connection electrode, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer.
According to an embodiment, the display device may further include a fourth conductive pattern disposed on the third conductive pattern and directly contacting the third conductive pattern.
According to an embodiment, the display device may further include a first dummy pattern disposed on the substrate, overlapping the pad region, and spaced apart from the first conductive pattern in the plan view and a second dummy pattern disposed on the first dummy pattern and contacting the first dummy pattern through a dummy contact hole defined in the insulating layer.
According to an embodiment, an area of the dummy contact hole may be different from an area of each of the plurality of the contact holes in the plan view.
According to an embodiment, the area of the dummy contact hole may be larger than the area of each of the plurality of the contact holes.
According to an embodiment, the pad region may include a central region and an outer region adjacent to the central region in the plan view. The first conductive pattern may be disposed in the central region and the first dummy pattern may be disposed in the outer region.
According to an embodiment, the first dummy pattern and the second dummy pattern may each be electrically floated.
A display device according to another embodiment includes a substrate including a pad region, a first conductive pattern disposed on the pad region of the substrate and having a quadrangle shape in a plan view, an insulating layer disposed on the substrate and covering the first conductive pattern, and a second conductive pattern disposed on the insulating layer and contacting the first conductive pattern through a plurality of contact holes defined in the insulating layer. The plurality of the contact holes includes a first contact hole, a second contact hole, and a third contact hole which are spaced apart from each other, the first contact hole and the second contact hole are arranged along a first diagonal direction of the quadrangle shape, and the second contact hole and the third contact hole are arranged along a second diagonal direction intersecting the first diagonal direction.
According to an embodiment, the quadrangle shape may include a first side extending in a first direction and a second side extending in a second direction perpendicular to the first direction, the first diagonal direction may be a direction between the first direction and the second direction, and the second diagonal direction may be a direction between a third direction and the second direction, and the third direction is opposite to the first direction.
A display device according to still another embodiment includes a substrate including a pad region, a first conductive pattern on the pad region of the substrate, a first dummy pattern disposed in the same layer as the first conductive pattern and spaced apart from the first conductive pattern, an insulating layer disposed on the substrate and covering the first conductive pattern and the first dummy pattern, a second conductive pattern disposed on the insulating layer and contacting the first conductive pattern through a plurality of contact holes defined in the insulating layer, and a second dummy pattern disposed on the insulating layer and contacting the first dummy pattern through a dummy contact hole. The dummy contact hole is defined in the insulating layer and has an area different from an area of each of the plurality of the contact holes.
According to an embodiment, the area of the dummy contact hole may be larger than the area of each of the plurality of the contact holes.
According to an embodiment, the first conductive pattern may have a quadrangle shape and the plurality of the contact holes may be arranged along a diagonal direction of the quadrangle shape in a plan view.
Therefore, the display device according to embodiments may include the plurality of pads. Each of the pads may include the first conductive pattern and the second conductive pattern contacting the first conductive pattern through the contact holes. The length (or area) of each of the contact holes may be set significantly smaller than the length (or area) of the first conductive pattern. In other words, the second conductive pattern may contact the first conductive pattern with a point. Accordingly, the width of the step difference due to the contact holes generated on the upper surface of the second conductive pattern may be minimized. Accordingly, while the rework process is performed, the shapes of the pads may not be deformed, and a short defect between the pads may be effectively prevented.
In addition, the contact holes may be arranged along the diagonal direction. Accordingly, the indentation inspection process may be easily performed. In other words, as the contact holes are arranged along the diagonal direction, the pressure applied to the terminals, the conductive balls, and the pads may be easily inspected.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the inventive concepts.
It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
It will be understood that, although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, “a first element,” “component,” “region,” “layer” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one,” unless the content clearly indicates otherwise. “At least one” is not to be construed as limiting “a” or “an.” “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
“About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, 20%, 10% or 5% of the stated value.
Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.
Referring to
A pixel PX, a gate line GL, a data line DL, and a driving voltage line PL may be disposed in the display region DA of the display device 1000. For example, the gate line GL may extend in a first direction D1 and may transmit a gate signal GS to the pixel PX. The data line DL may extend in a second direction D2 perpendicular to the first direction D1 and may provide a data voltage DATA to the pixel PX. The driving voltage line PL may extend in the second direction D2 and may provide a driving voltage ELVDD to the pixel PX. The data voltage DATA may be written to the pixel PX in response to the gate signal GS. The pixel PX may emit light having a luminance based on the data voltage DATA. As the pixel PX emits light, an image may be displayed in the display region DA.
A gate driver GDV and a common voltage line may be disposed in the non-display region NDA of the display device 1000. The gate driver GDV may be connected to the gate line GL and pads PD. The gate driver GDV may receive a gate control signal, a clock signal, etc. from the pads PD, and may generate the gate signal GS. The common voltage line may be connected to the pads PD and a second electrode (e.g., a second electrode CTE of
Referring to
The first transistor T1 may include a first terminal, a second terminal, and a gate terminal. The first terminal of the first transistor T1 may receive the driving voltage ELVDD, the second terminal of the first transistor T1 may be connected to the organic light emitting diode OLED, and the gate terminal of the first transistor T1 may be connected to the second transistor T2. The first transistor T1 may generate a driving current ID based on the data voltage DATA.
The second transistor T2 may include a first terminal, a second terminal, and a gate terminal. The first terminal of the second transistor T2 may receive the data voltage DATA, the second terminal of the second transistor T2 may be connected to the first transistor T1, and the gate terminal of the second transistor T2 may receive the gate signal GS. The second transistor T2 may transmit the data voltage DATA in response to the gate signal GS.
The storage capacitor CST may include a first terminal and a second terminal. The first terminal of the storage capacitor CST may receive the driving voltage ELVDD, and the second terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor T1. The data voltage DATA may be stored in the storage capacitor CST.
The organic light emitting diode OLED may include a first terminal and a second terminal. The first terminal of the organic light emitting diode OLED may be connected to the first transistor T1, and the second terminal of the organic light emitting diode OLED may receive the common voltage ELVSS. The organic light emitting diode OLED may generate light based on the driving current ID.
However, a connection structure of the pixel circuit PC according to the invention may not be limited to the above-described connection structure. In another embodiment, the pixel circuit PC may further include at least one more transistor. For example, the pixel circuit PC may have a 3T1C structure (e.g., a structure having three transistors and one capacitor), a 7T2C structure (e.g., a structure having seven transistors and two capacitors), or the like.
Referring back to
In addition, the pad region PA may include a central region CA and an outer region OA. The central region CA may correspond to a central portion of the display device 1000. The outer region OA may correspond to left and right portions of the display device 1000 as shown
However, an arrangement structure of the pads PD and the dummy pads DPD according to the invention is not limited thereto.
In an embodiment, the pads PD may transmit signals (e.g., voltages) from an external device to the display device 1000. For example, the pads PD may include a first pad, a second pad, a third pad, and a fourth pad. The first pad may be electrically connected to the gate driver GDV, the second pad may be electrically connected to the data line DL, the third pad may be electrically connected to the driving voltage line PL, and the fourth pad may be electrically connected to the common voltage line. However, a connection structure of the pads PD according to the invention is not limited thereto.
The dummy pads DPD may be electrically insulated from any component included in the display device 1000. In other words, the dummy pads DPD may be electrically floating.
In an embodiment, the pads PD may have substantially the same stack structure with each other. For example, each of the pads PD may have a structure in which a plurality of conductive patterns are stacked. In addition, the pads PD may be formed together with the pixel PX.
In an embodiment, the dummy pads DPD may have substantially the same stack structure with each other. For example, each of the dummy pads DPD may have a structure in which a plurality of dummy patterns are stacked. In addition, the dummy pads DPD may be formed together with the pixel PX and the pads PD.
In an embodiment, the pads PD may be electrically connected to a circuit board CB. For example, a data driver, a controller (e.g., a timing controller (“T-CON”)), a power management circuit (e.g., “PMIC”), or the like may be disposed on the circuit board CB. The data driver may generate the data voltage DATA. The controller may control the gate driver, the data driver, and the power management circuit. The power management circuit may provide power to drive the display device 1000. In an embodiment, a plurality of terminals CP and a plurality of dummy terminals DCP may be disposed on the circuit board CB. Positions where the terminals CP are disposed may correspond to positions where the pads PD are disposed in a plan view. Positions where the dummy terminals DCP are disposed may correspond to positions where the dummy pads DPD are disposed in a plan view. The circuit board CB may be bonded in the pad region PA so that the terminals CP contact the pads PD physically or electrically. In addition, the circuit board CB may be bonded in the pad region PA so that the dummy terminals DCP contact the dummy pads DPD physically or electrically. For example, through a bonding process, the circuit board CB may be bonded in the pad region PA using an anisotropic conductive film (“ACF”). The anisotropic conductive film may include a plurality of conductive balls, and the conductive balls may be disposed between the pads PD and the terminals CP and may be disposed between the dummy pads DPD and the dummy terminal DCP. As the conductive balls have conductivity, the pads PD and the terminals CP which correspond to each other may be electrically connected to each other.
The dummy pads DPD may prevent the circuit board CB from being deformed during the bonding process. For example, in order to bond the circuit board CB to the pad region PA, a pressure may be applied to the circuit board CB. In this case, the pressure applied to the outer portion of the circuit board CB (e.g., a position where the dummy terminals DCP is formed) may be relatively increased compared to the pressure applied to the center portion of the circuit board CB, and the circuit board CB may be deformed. As the dummy pads DPD support the outer portion of the circuit board CB, the dummy pads DPD may prevent the circuit board CB from being deformed.
The circuit board CB may be a driving chip or a flexible printed circuit board. For example, when the display device 1000 has a chip-on-glass (“COG”) structure or a chip-on-plastic (“COP”) structure, the circuit board CB may be the driving chip. When the display device 1000 has a chip-on-film (“COF”) structure, the circuit board CB may be the flexible printed circuit board. However, the circuit board CB according to the invention is not limited thereto.
After the bonding process, an indentation inspection process and a rework process may be performed. The indentation inspection process may be a process of inspecting the position of the pressure applied in the pad region PA, the level of the pressure, or the like. Pressure applied to the terminals CP, the conductive balls, and the pads PD may be inspected through the indentation inspection process. Accordingly, it may be checked whether the pads PD are normally connected to the terminals CP. The rework process may be a process of removing the circuit board CB and cleaning the pads PD. For example, when the pads PD are abnormally connected to the terminals CP, the circuit board CB may be removed from the pad region PA. In addition, foreign matter (e.g., the conductive balls) remaining on the pads PD may be removed through the rework process.
As the display device 1000 according to embodiments includes the pads PD, a short defect between the pads PD generated during the rework process may be effectively prevented. In addition, as the display device 1000 includes the dummy pads DPD, the indentation inspection process may be more easily performed.
Referring to
A buffer layer BFR may be disposed on the substrate SUB and may overlap the display region DA in a plan view. In other words, the buffer layer BFR may be disposed in the display region DA. In an embodiment, the buffer layer BFR may include an inorganic material. For example, the buffer layer BFR may include silicon oxide, silicon nitride, silicon oxynitride, or the like. The buffer layer BFR may prevent diffusion of metal atoms or impurities from the substrate SUB into an active pattern ACT. In addition, the buffer layer BFR may control a rate of heat supply during a crystallization process for forming the active pattern ACT.
The active pattern ACT may be disposed on the buffer layer BFR and may overlap the display region DA in a plan view. In an embodiment, the active pattern ACT may include a silicon semiconductor, an oxide semiconductor, or the like. For example, the active pattern ACT may include amorphous silicon, polycrystalline silicon, or metal oxide.
A gate insulating layer GI may cover the active pattern ACT and may overlap the display region DA in a plan view. In other words, gate insulating layer GI may be disposed in the display region DA. In an embodiment, the gate insulating layer GI may include an inorganic insulating material. For example, the gate insulating layer GI may include silicon oxide, silicon nitride, silicon oxynitride, or the like.
A first gate electrode GAT1 may be disposed on the gate insulating layer GI and may overlap the active pattern ACT in a plan view. In an embodiment, the first gate electrode GAT1 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the first gate electrode GAT1 may include silver (“Ag”), an alloy containing silver, molybdenum (“Mo”), an alloy containing molybdenum, aluminum (“Al”), an alloy containing aluminum, aluminum nitride (“AN”), tungsten (“W”), tungsten nitride (“WN”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), chromium nitride (“CrN”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), scandium (“Sc”), indium tin oxide (“ITO”), indium zinc oxide (“IZO”), or the like. The first gate electrode GAT1 may constitute the first transistor T1 together with the active pattern ACT.
A first interlayer-insulating layer ILD1 may cover the first gate electrode GAT1 and may overlap the display region DA in a plan view. In an embodiment, the first interlayer-insulating layer ILD1 may include an inorganic insulating material. For example, the first interlayer-insulating layer ILD1 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.
A second gate electrode GAT2 may be disposed on the first interlayer-insulating layer ILD1 and may overlap the first gate electrode GAT1 in a plan view. In an embodiment, the second gate electrode GAT2 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the second gate electrode GAT2 may include the same material as the first gate electrode GAT1. The second gate electrode GAT2 may form the storage capacitor CST together with the first gate electrode GAT1.
A second interlayer-insulating layer ILD2 may cover the second gate electrode GAT2 and may overlap the display region DA in a plan view. In an embodiment, the second interlayer-insulating layer ILD2 may include an inorganic insulating material. For example, the second interlayer-insulating layer ILD2 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.
A first source electrode SE1 and a first drain electrode DE1 may be disposed on the second interlayer-insulating layer ILD2 and may contact the active pattern ACT. In an embodiment, the first source electrode SE1 and the first drain electrode DE1 each may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the first source electrode SE1 and the first drain electrode DE1 each may have a Ti/Al/Ti structure.
A first via-insulating layer VIA1 may cover the first source electrode SE1 and the first drain electrode DE1 and may overlap the display region DA in a plan view. In other words, first via-insulating layer VIA1 may be disposed in the display region DA. In an embodiment, the first via-insulating layer VIA1 may include an organic insulating material. For example, the first via-insulating layer VIA1 may include a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, or the like.
A second drain electrode DE2 may be disposed on the first via-insulating layer VIA1 and may contact the first drain electrode DE1. In an embodiment, the second drain electrode DE2 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the second drain electrode DE2 may have a Ti/Al/Ti structure.
A second via-insulating layer VIA2 may cover the second drain electrode DE2 and may overlap the display region DA in a plan view. In an embodiment, the second via-insulating layer VIA2 may include an organic insulating material.
A first electrode ADE may be disposed on the second via-insulating layer VIA2 and may contact the second drain electrode DE2. In an embodiment, the first electrode ADE may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the first electrode ADE may include silver (“Ag”), an alloy containing silver, molybdenum (“Mo”), an alloy containing molybdenum, aluminum (“Al”), an alloy containing aluminum, aluminum nitride (“AN”), tungsten (“W”), tungsten nitride (“WN”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), chromium nitride (“CrN”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), scandium (“Sc”), indium tin oxide (“ITO”), indium zinc oxide (“IZO”), or the like. In an embodiment, the first electrode ADE may have an ITO/Ag/ITO structure.
A pixel defining layer PDL may be disposed on the second via-insulating layer VIA2 and/or the first electrode ADE, and may overlap the display region DA in a plan view. In an embodiment, the pixel defining layer PDL may include an organic insulating material. An opening exposing an upper surface of the first electrode ADE may be defined in the pixel defining layer PDL.
The emission layer EL may be disposed in the opening. The emission layer EL may generate light based on the driving current ID. For example, the emission layer EL may include an organic light-emitting material.
The second electrode CTE may be disposed on the emission layer EL. In an embodiment, the second electrode CTE may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. The first electrode ADE, the emission layer EL, and the second electrode CTE may constitute the organic light emitting diode OLED.
A light emitting diode included in the display device 1000 may not be limited to the organic light emitting diode OLED. In another embodiment, for example, the light emitting diode may include a micro light emitting diode (“micro-LED”), a nano light emitting diode (“nano-LED”), and a light emitting diode including at least one of a quantum dot (“QD”), or a quantum rod (“QR”).
An encapsulation layer ENC may be disposed on the second electrode CTE. The encapsulation layer ENC may include an insulating material. In an embodiment, the encapsulation layer ENC may be an encapsulation substrate. For example, the encapsulation layer ENC may be a glass substrate, a plastic substrate, or an encapsulation film. In another embodiment, the encapsulation layer ENC may have a structure in which inorganic layers and organic layers are alternately stacked. The encapsulation layer ENC may prevent foreign matter from penetrating into the emission layer EL.
A sensing electrode TPE may be disposed on the encapsulation layer ENC. In an embodiment, the sensing electrode TPE may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the sensing electrode TPE may include silver (“Ag”), an alloy containing silver, molybdenum (“Mo”), an alloy containing molybdenum, aluminum (“Al”), an alloy containing aluminum, aluminum nitride (“AN”), tungsten (“W”), tungsten nitride (“WN”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), chromium nitride (“CrN”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), scandium (“Sc”), indium tin oxide (“ITO”), indium zinc oxide (“IZO”), or the like. The sensing electrode TPE may form a capacitance, and a user's touch may be sensed based on the amount of change in the capacitance.
A first lower insulating layer 100 may be disposed on the substrate SUB and may overlap the pad region PA in a plan view. In an embodiment, the first lower insulating layer 100 may include an inorganic material. For example, the first lower insulating layer 100 may include silicon oxide, silicon nitride, silicon oxynitride, or the like. In an embodiment, the first lower insulating layer 100 may be formed together with the buffer layer BFR.
A second lower insulating layer 200 may be disposed on the first lower insulating layer 100 and may overlap the pad region PA in a plan view. In an embodiment, the second lower insulating layer 200 may include an inorganic material. The second lower insulating layer 200 may be formed together with the gate insulating layer GI.
The pads PD may be disposed on the second lower insulating layer 200 and may overlap the pad region PA in a plan view. Each of the pads PD may include a first conductive pattern 300, a second conductive pattern 500, a third conductive pattern 600, and a fourth conductive pattern 700.
The first conductive pattern 300 may be disposed on the second lower insulating layer 200 and may overlap the pad region PA in a plan view. In an embodiment, the first conductive pattern 300 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the first conductive pattern 300 may include silver (“Ag”), an alloy containing silver, molybdenum (“Mo”), an alloy containing molybdenum, aluminum (“Al”), an alloy containing aluminum, aluminum nitride (“AN”), tungsten (“W”), tungsten nitride (“WN”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), chromium nitride (“CrN”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), scandium (“Sc”), indium tin oxide (“ITO”), indium zinc oxide (“IZO”), or the like. The first conductive pattern 300 may be formed together with the first gate electrode GAT1.
In an embodiment, as shown in
An insulating layer 400 may cover the first conductive pattern 300 and may overlap the pad region PA in a plan view. The insulating layer 400 may include a first insulating layer 410 and a second insulating layer 420.
The first insulating layer 410 may cover the first conductive pattern 300 and may overlap the pad region PA in a plan view. In an embodiment, the first insulating layer 410 may include an inorganic insulating material. For example, the first insulating layer 410 may include silicon oxide, silicon nitride, silicon oxynitride, or the like. The first insulating layer 410 may be formed together with the first interlayer-insulating layer ILD1.
The second insulating layer 420 may contact the first insulating layer 410 and may overlap the pad region PA in a plan view. In an embodiment, the second insulating layer 420 may include an inorganic insulating material. For example, the second insulating layer 420 may include silicon oxide, silicon nitride, silicon oxynitride, or the like. The second insulating layer 420 may be formed together with the second interlayer-insulating layer ILD2.
In an embodiment, as shown in
In an embodiment, the contact holes CNT may include a first contact hole CNT1, a second contact hole CNT2, and a third contact hole CNT3. The first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may be arranged along a diagonal direction of the quadrangle shape RS. As used herein, the “diagonal direction of a quadrangle shape” includes any direction except for a direction of a vertical side and a direction of a horizontal side of the quadrangle shape. In detail, the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may be arranged along a first diagonal direction DD1 between the first direction D1 and the second direction D2. In an embodiment, the first diagonal direction DD1 may be a direction from a lower left vertex to an upper right vertex of the quadrangle shape RS. However, the first diagonal direction DD1 according to the invention is not limited thereto.
In an embodiment, the first length LNT1 may be greater than a length (e.g., diameter) LTC of each of the contact holes CNT at the bottom thereof and in the first direction D1. For example, the first length LNT1 may be about 3 times greater than the length LTC of each of the contact holes CNT. The first length LNT1 may be greater than about 9 micrometers (μm), and the length LTC of each of the contact holes CNT may be less than about 3 μm. In addition, in an embodiment, an area of each of the contact holes CNT may be smaller than 7 square-micrometers (μm2). In an embodiment, the first insulating layer 410 and the second insulating layer 420 may include an overlapping portion PP and a non-overlapping portion FP. The overlapping portion PP may surround the contact holes CNT and may overlap the first conductive pattern 300 in a plan view. A top of the non-overlapping portion FP may be disposed lower than a top of the overlapping portion PP. A first thickness W1 of the overlapping portion PP may be the same as a second thickness W2 of the non-overlapping portion FP in a thickness direction (i.e., fourth direction D4). The fourth direction D4 is perpendicular to a plane defined by the first direction D1 and the second direction D2. For example, each of the first thickness W1 and the second thickness W2 may be about 6000 angstroms (Å) to about 7000 angstroms. A thickness of the first insulating layer 410 may be about 1400 angstroms, and a thickness of the second insulating layer 420 may be about 5000 angstroms.
The second conductive pattern 500 may be disposed on the second insulating layer 420 and may overlap the pad region PA in a plan view. In an embodiment, the second conductive pattern 500 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. A material included in the second conductive pattern 500 may be different from a material included in the first conductive pattern 300. For example, the second conductive pattern 500 may be formed together with the first source electrode SE1 and the first drain electrode DE1 and may have a Ti/Al/Ti structure.
In an embodiment, the second conductive pattern 500 may contact the first conductive pattern 300 through the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3.
The third conductive pattern 600 may be disposed on the second conductive pattern 500 and may overlap the pad region PA in a plan view. The third conductive pattern 600 may directly contact the second conductive pattern 500. In an embodiment, the third conductive pattern 600 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. A material included in the third conductive pattern 600 may be the same as the material included in the second conductive pattern 500. For example, the third conductive pattern 600 may be formed together with the second drain electrode DE2 and may have a Ti/Al/Ti structure.
The fourth conductive pattern 700 may be disposed on the third conductive pattern 600 and may overlap the pad region PA in a plan view. The fourth conductive pattern 700 may directly contact the third conductive pattern 600. In an embodiment, the fourth conductive pattern 700 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the fourth conductive pattern 700 may include silver (“Ag”), an alloy containing silver, molybdenum (“Mo”), an alloy containing molybdenum, aluminum (“Al”), an alloy containing aluminum, aluminum nitride (“AN”), tungsten (“W”), tungsten nitride (“WN”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), chromium nitride (“CrN”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), scandium (“Sc”), indium tin oxide (“ITO”), indium zinc oxide (“IZO”), or the like. The fourth conductive pattern 700 may be formed together with the sensing electrode TPE.
The display device 1000 may include the pads PD, and each of the pads PD may include the first to fourth conductive patterns 300, 500, 600, and 700. The second conductive pattern 500 may contact the first conductive pattern 300 through the contact holes CNT.
In an embodiment, the length LTC (or area) of each of the contact holes CNT may be set significantly smaller than the first length LNT1 (or area) of the first conductive pattern 300. In other words, the second conductive pattern 500 may contact the first conductive pattern 300 with a point. Accordingly, a stepped region existing in the upper surface of the second conductive pattern 500 may be minimized, and each of the pads PD may have a substantially flat upper surface. Accordingly, while the rework process is performed, shapes of the pads PD may not be deformed, and a short defect between the pads PD may be prevented.
In addition, in an embodiment, the contact holes CNT may be arranged in the first diagonal direction DD1. Accordingly, the indentation inspection process may be easily performed. In other words, as the contact holes CNT are arranged in the first diagonal direction DD1, the pressure applied to the terminals CP, the conductive balls, and the pads PD may be easily inspected.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
The dummy pads DPD may be disposed on the second lower insulating layer 200 and may overlap the pad region PA in a plan view. Each of the dummy pads DPD may include a first dummy pattern D300, a second dummy pattern D500, a third dummy pattern D600, and a fourth dummy pattern D700.
The first dummy pattern D300 may be disposed on the second lower insulating layer 200 and may overlap the pad region PA. In an embodiment, the first dummy pattern D300 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the first dummy pattern D300 may be formed together with the first conductive pattern 300 and may include the same material as the first conductive pattern 300.
In an embodiment, as shown in
In an embodiment, as shown in
In an embodiment, a first dummy contact hole length DLTC1 of the dummy contact hole DCNT in the first direction D1 may be greater than the length LTC of each of the contact holes CNT. In addition, a second dummy contact hole length DLTC2 of the dummy contact hole DCNT in the second direction D2 may be greater than the length LTC. In an embodiment, an area of the dummy contact hole DCNT may be greater than about 500 μm2. In other words, the area of the dummy contact hole DCNT may be greater than the area of each of the contact holes CNT.
The second dummy pattern D500 may be disposed on the second insulating layer 420 and may overlap the pad region PA. In an embodiment, the second dummy pattern D500 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the second dummy pattern D500 may be formed together with the second conductive pattern 500 and may include the same material as the second conductive pattern 500.
In an embodiment, the second dummy pattern D500 may contact the first dummy pattern D300 through the dummy contact hole DCNT.
The third dummy pattern D600 may be disposed on the second dummy pattern D500 and may overlap the pad region PA. The third dummy pattern D600 may directly contact the second dummy pattern D500. In an embodiment, the third dummy pattern D600 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the third dummy pattern D600 may be formed together with the third conductive pattern 600 and may include the same material as the third conductive pattern 600.
The fourth dummy pattern D700 may be disposed on the third dummy pattern D600 and may overlap the pad region PA. The fourth dummy pattern D700 may directly contact the third dummy pattern D600. In an embodiment, the fourth dummy pattern D700 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the fourth dummy pattern D700 may be formed together with the fourth conductive pattern 700 and may include the same material as the fourth conductive pattern 700.
The display device 1000 may include the dummy pads DPD, and each of the dummy pads DPD may include the first to fourth dummy patterns D300, D500, D600, and D700. The second dummy pattern D500 may contact the first dummy pattern D300 through the dummy contact hole DCNT.
In an embodiment, the first dummy contact hole length DLTC1 (or the second dummy contact hole length DLTC2) of the dummy contact hole DCNT may be set significantly greater the length LTC of each of the contact holes CNT. In other words, the second dummy pattern D500 may contact the first dummy pattern D300 with a surface. In other words, the areas of the first insulating layer 410 and the second insulating layer 420 which are removed to form the dummy pads DPD may increase. Accordingly, the number of layers stacked to form the dummy pads DPD may be reduced and visibility of the dummy pads DPD may be improved. Therefore, the indentation inspection process performed on the dummy pads DPD may be more easily performed. Through this, the indentation state of the pads PD may be more easily checked.
Referring to
The pads PD′ may include the first conductive pattern 300, a second conductive pattern 500′, a third conductive pattern 600′, and a fourth conductive pattern 700′. The first conductive pattern 300 may be substantially the same as the first conductive pattern 300 described with reference to
In detail, in an embodiment, the contact holes CNT may include a first contact hole CNT1, a second contact hole CNT2, and a third contact hole CNT3. The first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may be arranged along a diagonal direction of the quadrangle shape RS. For example, the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may be arranged along a second diagonal direction DD2 between a third direction D3 and the second direction D2. The third direction D3 is opposite to the first direction D1. In an embodiment, the second diagonal direction DD2 may be a direction from a lower right vertex to an upper left vertex of the quadrangle shape RS. However, the second diagonal direction DD2 according to the invention is not limited thereto.
The second conductive pattern 500′ may be disposed on the first conductive pattern 300, and may contact the first conductive pattern 300 through the first to third contact holes CNT1, CNT2, and CNT3. The third conductive pattern 600′ may be disposed on the second conductive pattern 500′ and may contact the second conductive pattern 500′. The fourth conductive pattern 700′ may be disposed on the third conductive pattern 600′ and may contact the third conductive pattern 600′
Referring to
The pads PD″ may include the first conductive pattern 300, a second conductive pattern 500″, a third conductive pattern 600″, and a fourth conductive pattern 700″. The first conductive pattern 300 may be substantially the same as the first conductive pattern 300 described with reference to
In detail, in an embodiment, the contact holes CNT may include a first contact hole CNT1, a second contact hole CNT2, and a third contact hole CNT3. The first contact hole CNT1 and the second contact hole CNT2 may be arranged along a third diagonal direction DD3 of the quadrangle shape RS, and the second contact hole CNT2 and the third contact hole CNT3 may be arranged along a fourth diagonal direction DD4 of the quadrangle shape RS. Here, the third diagonal direction DD3 may be between the first diagonal direction DD1 and the first direction D1 as shown in
The second conductive pattern 500″ may be disposed on the first conductive pattern 300, and may contact the first conductive pattern 300 through the first to third contact holes CNT1, CNT2, and CNT3. The third conductive pattern 600″ may be disposed on the second conductive pattern 500″ and may contact the second conductive pattern 500″. The fourth conductive pattern 700″ may be disposed on the third conductive pattern 600″ and may contact the third conductive pattern 600″.
The display device 1000, 1100, or 1200 according to embodiments may include a plurality of pads PD, PD′, or PD″ and a plurality of dummy pads DPD.
Each of the pads PD, PD′, or PD″ may include the first conductive pattern 300 and the second conductive pattern 500, 500′, or 500″ contacting the first conductive pattern 300 through the contact holes CNT. The length LTC (or area) of each of the contact holes may be set significantly smaller than the first length LNT1 (or area) of the first conductive pattern. In other word, the second conductive pattern may contact the first conductive pattern with a point. Accordingly, a stepped region existing in the upper surface of the second conductive pattern 500, 500′, or 500″ may be minimized, and each of the pads PD, PD′, or PD″ may have a substantially flat upper surface. Accordingly, while the rework process is performed, shapes of the pads PD, PD′, or PD″ may not be deformed, and a short defect between the pads PD, PD′, or PD″ may be prevented.
In addition, the contact holes CNT may be arranged along the third diagonal direction DD3 and/or the fourth diagonal direction DD4. Accordingly, the indentation inspection process may be easily performed. In other words, as the contact holes CNT are arranged along the third diagonal direction DD3 and/or the fourth diagonal direction DD4, the pressure applied to the terminals CP, the conductive balls, and the pads PD may be easily inspected.
In addition, each of the dummy pads DPD may include the first dummy pattern D300 and the second dummy pattern D500 contacting the first dummy pattern D300 through the dummy contact hole DCNT. A length (or area) of the dummy contact hole DCNT may be set significantly greater than a length (or area) of each of the contact holes CNT. In other words, the second dummy pattern D500 may contact the first dummy pattern D300 with a surface. Accordingly, the number of layers stacked to form the dummy pads DPD may be reduced, and visibility of the dummy pads DPD may be improved. Therefore, the indentation inspection process performed on the dummy pads DPD may be more easily performed. Through this, the indentation state of the pads PD may be more easily checked.
Referring to
The electronic device 2100 may further include several ports capable of communicating with a video card, a sound card, a memory card, a USB device, or other systems.
The processor 2110 may perform specific calculations or tasks. In an embodiment, the processor 2110 may be a microprocessor, a central processing unit (“CPU”), or the like. The processor 2110 may be connected to other components through an address bus, a control bus, and a data bus. In another embodiment, the processor 2110 may also be connected to an expansion bus such as a Peripheral Component Interconnect (“PCI”) bus.
The memory device 2120 may store data necessary for the operation of the electronic device 2100. For example, the memory device 2120 may include non-volatile memory devices such as an Erasable Programmable Read-Only Memory (“EPROM”), an Electrically Erasable Programmable Read-Only Memory (“EEPROM”), a Flash Memory, a Phase Change Random Access Memory (“PRAM”), a Resistance Random Access Memory (“RRAM”), a Nano Floating Gate Memory (“NFGM”), a Polymer Random Access Memory (“PoRAM”), a Magnetic Random Access Memory (“MRAM”), and a Ferroelectric Random Access Memory (“FRAM”) and/or a volatile memory devices such as a Dynamic Random Access Memory (“DRAM”) a Static Random Access Memory (“SRAM”), mobile DRAM, or the like.
The storage device 2130 may include a solid state drive (“SSD”), a hard disk drive (“HDD”), a CD-ROM, or the like. The input/output device 2140 may include an input means such as a keyboard, a keypad, a touch pad, a touch screen, and a mouse, and an output means such as a speaker or a printer. The power supply 2150 may supply power required for the operation of the electronic device 2100. The display device 2160 may be connected to other components through the buses or other communication links.
The electronic device 2100 may include a mobile phone, a smart phone, a tablet computer, a digital TV, a 3D TV, a personal computer (“PC”), a home electronic device, a laptop computer, a Personal Digital Assistant (“PDA”), a Portable Multimedia Player (“PMP”), a digital camera, a music player, a portable game console, navigation, or the like.
Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concepts are not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as would be apparent to a person of ordinary skill in the art.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2020-0155480 | Nov 2020 | KR | national |
| 10-2021-0087834 | Jul 2021 | KR | national |
