BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates an arrangement of graphic random access memory (GRAM) cells and source drivers in a driver integrated circuit (DDI) for a display device.
FIG. 2 conceptually illustrates one embodiment of a memory mapping scheme for a DDI.
FIGS. 3A-B illustrate two different examples of a memory mapping scheme for a DDI.
FIG. 4 illustrates one embodiment of a memory mapping scheme, and a corresponding memory remapping scheme, for a DDI.
FIG. 5 illustrates one embodiment of an arrangement for remapping the physical addresses of GRAM cells in a DDI to the external addresses of source drivers in the DDI.
FIG. 6 shows a timing diagram for a memory location remapping circuit in a DDI.
DETAILED DESCRIPTION
FIG. 2 conceptually illustrates one embodiment of a memory mapping scheme for a display driver integrated circuit (DDI). In particular, FIG. 2 illustrates a memory mapping technique employed by a DDI to map externally used data addresses to physical memory addresses within a graphic random access memory (GRAM) included in the DDI.
In the memory mapping scheme illustrated in FIG. 2, it is assumed that the external addresses are provided in a matrix of b*y rows and a*x columns, which may correspond to a display device having b*y rows and a*x columns. The memory mapping scheme illustrated in FIG. 2 maps the b*y rows and a*x columns of external addresses into a*y rows and b*x columns of physical memory addresses of its GRAM.
In the example illustrated in FIG. 2, b=4, and a=3. For example only, and simply to illustrate the principles better, consider a case where y=60, and x=120. In that case, the external addresses are arranged in 4*60=240 rows and 3*120=360 columns. The memory mapping scheme illustrated in FIG. 2 maps the 4*60=240 rows and 3*120=360 columns of external addresses into 3*60=180 rows and 4*120=480 columns of physical memory addresses in the GRAM. That is, blocks of 3*4=12 external memory addresses are mapped into groups of 4*3 physical memory addresses, by taking the last of the four rows of external addresses and appending it to the last of the three columns to produce four columns of three addresses each of physical memory addresses. Using the numbers provided above, every (4m+3)th row of external addresses is relocated to a (4n′+3)th row of physical memory addresses, where m ![]()
(0, (y−1)) and n′![]()
(0, x−1)), where y=60 and x=120.
Beneficially, the mapping and remapping schemes illustrated in FIG. 2 are performed whenever data is written into, or read out of, the GRAM in the DDI.
FIGS. 3A-B illustrate two different examples of a memory mapping scheme for a DDI. For ease of illustration, it is assumed that x=y=1, but the examples can easily be extrapolated for any values of x and y. In the first example of FIG. 3A, a block of b=3 rows by a=2 columns of external addresses are mapped to a block of a=2 rows by b=3 columns. In the second example of FIG. 3B, a block of b=5 rows by a=4 columns of external addresses are mapped to a block of a=4 rows by b=5 columns of physical memory addresses. The examples shown in FIGS. 3A-B illustrate how any block of (N+1) rows by N columns of external addresses can be transformed into N columns by (N+1) rows of physical memory addresses in GRAM. Advantageously, such a transformation changes the “aspect ratio” of the GRAM without a corresponding increase in its total size. That is, through the transformation achieved by the mapping scheme described above, the width of the GRAM is increased, while the depth is correspondingly decreased. Accordingly, for a same-size GRAM, the width of the GRAM can be made to better match the corresponding dimensions of the source drivers, thus facilitating signal routing and improving the overall layout. This will be shown and explained in greater detail below with respect to FIG. 5.
It should also be understood that although the examples shown in FIGS. 3A-B illustrate cases where the blocks of external addresses are (N+1) rows by N columns, the principles can be generally extended to a case where the blocks of external addresses comprise (N+j) rows by N columns, where j is an integer greater than or equal to 1.
FIG. 4 illustrates one embodiment of a memory mapping scheme, and a corresponding memory remapping scheme, for a DDI where there are a relatively large number of memory locations. Here, there are b*y=4*60=240 rows and a*x=3*120=360 columns of external addresses. In the mapping operation (e.g., a data write operation), as shown in FIG. 4, every group of b×a external addresses is mapped to a group of a×b physical memory addresses, where in the example of FIG. 4, b=4 and a=3. As a result, the physical memory (e.g., the GRAM) is arranged into a*y=3*60=180 rows and b*x=4*120=480 columns of physical memory addresses. Conversely, in the remapping operation (e.g., a data read operation), the a*y=3*60=180 rows and b*x=4*120=480 columns of physical memory addresses are remapped to b*y=4*60=240 rows and a*x=3*120=360 columns of external addresses.
Another way of understanding FIG. 4 is to consider that each of the a*y rows of physical memory addresses includes one entire row among the original b*y rows of the external memory addresses. Now, since b>a, there are (b−a)*y “extra” rows of external addresses that need to be stored in somewhere in the a*y rows of physical memory addresses. Therefore, each of the a*y rows of physical memory addresses also includes addresses corresponding to a fraction of another row of the external addresses. In particular, each of the a*y rows of physical memory addresses also includes x addresses from one of the “extra” rows of the external addresses. Since there are a total of a*x addresses in each row of external addresses, it can be seen that each one of the (b−a)*y “extra” rows of external addresses is included within each group of a consecutive rows of physical memory addresses.
For example, in the specific example shown in FIG. 4, a=3, x=120, b=4, and y=60. In that case, the external addresses include b*y=240 rows and a*x=360 columns. In turn, the physical memory addresses include a*y=180 rows, corresponding to 180 of the 240 rows of the external addresses. The remaining “extra” 60 rows of the external addresses are then included within the 180 rows of physical memory addresses, by including in each of the 180 rows of physical memory addresses, x=120 addresses of one of the “extra” rows. In particular, after every group of a=3 addresses in each row of physical memory addresses, a new address is inserted from one of the “extra” rows of external addresses. Therefore, a total of x=120 extra addresses from one “extra” row of external addresses are included in each row of physical memory addresses. Accordingly, each row of physical memory addresses has a total of the entire 360 addresses of one entire row of external memory addresses, plus another 120 addresses from an “extra” row of external addresses, resulting in a total of 480 addresses.
A memory controller may be employed to map the external addresses to the physical memory addresses of the GRAM in the DDI. Such a controller may be provided “on-board” to the DDI, or externally thereto.
FIG. 5 illustrates one embodiment of an arrangement for remapping the physical addresses of GRAM cells 510 in a DDI to the external addresses of source drivers 520 in the DDI. FIG. 5 illustrates a plurality of GRAM cells 510 arranged in rows and columns, a plurality of source drivers 520(i), a plurality of source driver latches 530a-530c, and a memory location mapping circuit 540, where i ![]()
(1, 12). Memory location mapping circuit 540 includes a plurality of first latches 542a-542b, and a plurality of multiplexers (MUXs) 546a-546c.
In the example of FIG. 5, it is assumed that each GRAM cell 510 stores 24 bits of data for three source drivers 520, e.g., 8-bit image data for each of three column lines (e.g., source lines) of a display device, such as an active matrix LCD device, driven by source drivers 520. In turn, the three column lines drive three columns of sub-pixels of three different colors (e.g., red, green & blue) to form a column of pixels each comprising, for example, one red sub-pixel, one green sub-pixel, and one blue sub-pixel, for displaying an entire range of colors. Typically, the columns of sub-pixels are arranged in rows, with a switching terminal of each sub-pixel element in a row being connected to a corresponding row line or select line (e.g., a gate line). In that case, typically the rows of sub-pixels are selected sequentially one at a time during a row (or scan line) period by applying a selection or scanning voltage to the row line. Of course, the arrangement of three-sub-pixels into a single pixel is only exemplary, a pixel may have more or less than three sub-pixels.
In the arrangement of FIG. 5 four (4) columns of GRAM cells 510 store data for nine (9) source drivers 520 for driving nine (9) column lines corresponding to three columns of pixels of a display device, and the four columns of GRAM cells 510 have to be interfaced to the nine (9) source drivers 520. In contrast, in the arrangement of FIG. 1, four (4) columns of GRAM cells 110 store data for twelve (12) source drivers 120 for driving twelve (12) column lines corresponding to fours columns of pixels of a display device, and the four GRAM cells 510 have to be interfaced to the twelve (12) source drivers 520. So as the widths of the GRAM cells 510 are reduced, the arrangement of FIG. 5 better matches the widths of the GRAM cells to the widths of the source drivers in comparison to the arrangement of FIG. 1. This makes signal routing easier, and leads to a decrease in the area required for signal routing compared to the arrangement of FIG. 1. At the same time, the total size occupied by the GRAM device is not increased by the arrangement of FIG. 5, because even though each row of memory cells 510 in the GRAM is longer (has more cells), the number of rows is correspondingly decreased to maintain an essentially uniform total size.
In FIG. 5, image data for source nine source drivers 520 has been mapped into four columns of GRAM cells 510. That is, as a result of the mapping operation as described above, externally supplied image data for b*y rows by a*x columns of pixels has been mapped to a*y rows by b*x columns of GRAM cells 510 in the DDI, where b=4, and a=3. Accordingly, memory location remapping circuit 540 remaps the image data stored in the GRAM cells 510 to be output properly to source drivers 520 and thereby to the column lines (source lines) of a display device to be driven. In particular, memory remapping circuit 540 remaps a*y rows by b*x columns of image data in GRAM 510 to b*y rows by a*x columns of pixels. In the particular embodiment of FIG. 5, memory remapping circuit 540 remaps blocks of image data from a=3 rows by b=4 columns of GRAM cells 510 to be output as b=4 rows by a=3 columns of image data for source drivers 520.
The operation of the exemplary embodiment memory remapping circuit 540 will now be explained with reference to the timing diagram of FIG. 6. In particular, the image data of three (3) rows of GRAM cells 510 each having four (4) GRAM cells 510, is remapped to four rows or lines of image data each comprising three columns of image data for three pixels per row.
As shown in FIG. 6, a scan clock SCK operates at a scan line rate at which a line or row of data is to be provided to source drivers 520. During a first scan line (or row) period, data in the first row of GRAM cells 510 is output by the GRAM device. In response to a MUX_SELECT signal (not shown in FIG. 5) and the rising edge of SCK, each of MUXs 546a-546c selects the image data input on line D0 from one of the first three columns of GRAM cells 510 and provides the selected data to a corresponding one of the source driver latches 530a-530c where it is subsequently latched for a remaining portion of the first scan line period by a source driver latch signal S_LATCH (also not shown in FIG. 5). Accordingly, during the first scan line period, the image data X1Y1, X2Y1, and X3Y1 is provided to source driver latches 530a-530c and thereby to source driver 520(i). Also during the first scan line period a first latch signal F_LATCH latches the image data X1Y4 from the fourth column of GRAM cells 510.
During a second scan line (or row) period, data in the second row of GRAM cells 510 is output by the GRAM device. In response to the MUX_SELECT signal and the rising edge of SCK, each of MUXs 546a-546c selects the image data input on line D0 from one of the first three columns of GRAM cells 510 and provides the selected data to a corresponding one of the source driver latches 530a-530c where it is subsequently latched for a remaining portion of the second scan line period by the source driver latch signal S_LATCH. Accordingly, during the second scan line period, the image data X1Y2, X2Y2, and X3Y2 is provided to source driver latches 530a-530c and thereby to source driver 520(i). Also during the second scan line period, first latch signal F_LATCH latches the image data X2Y4 from the fourth column of GRAM cells 510.
Next, during a third scan line (or row) period, data in the third row of GRAM cells 510 is output by the GRAM device. In response to the MUX_SELECT signal and the rising edge of SCK, each of MUXs 546a-546c selects the image data input on line D0 from one of the first three columns of GRAM cells 510 and provides the selected data to a corresponding one of the source driver latches 530a-530c where it is subsequently latched for a remaining portion of the third scan line period by the source driver latch signal S_LATCH. Accordingly, during the third scan line period, the image data X1Y3, X2Y3, and X3Y3 is provided to source driver latches 530a-530c and thereby to source driver 520(i). Also during the third scan line period, first latch signal F_LATCH latches the image data X3Y4 from the fourth column of GRAM cells 510.
Finally, during a fourth scan line (or row) period, no data is output by the GRAM device. Furthermore, no SCK pulse is present during the fourth scan line period. The MUX-SELECT signal has an opposite logic state as it did during the first, second and third scan line periods. In response to the MUX_SELECT signal, each of MUXs 546a-546c selects the image data input on line D1 from one of the three first latches 544a-544c and provides the selected data to a corresponding one of the source driver latches 530a-530c where it is subsequently latched for a remaining portion of the fourth scan line period by the source driver latch signal S_LATCH. Accordingly, during the fourth scan line period, the image data X1Y4, X2Y4, and X3Y4 is provided to source driver latches 530a-530c and thereby to source driver 520(i).
Thus, during the first through fourth scan line periods, source driver latch 530a receives in sequence the data X1Y1, X1Y2, X1Y3 and X1Y4. Similarly, during the first through fourth scan line periods, source driver latch 530b receives in sequence the data X2Y1, X2Y2, X2Y3 and X1Y4, and source driver latch 530c receives in sequence the data X3Y1, X3Y2, X3Y3 and X3Y4. Accordingly, memory remapping circuit 540 remaps a*y rows by b*x columns of image data in GRAM 510 to b*y rows by a*x columns of pixels.
Although the specific embodiments described in the figures above describe cases where b*y rows and a*x columns of external addresses are mapped to a*y rows and b*x columns of physical memory addresses where b=a+1, and then remapped back again, in general the principles may be extended to a case where b=a+j, where j can be any integer greater than or equal to 1, that is, where b>a.
Also, although the embodiments described above pertained to DDIs where the graphics memory device is GRAM, the principles are extendable to other graphics memory devices in a DDI, such as FLASH memory devices. Furthermore, in some embodiments, the source drivers may be provided externally to the DDI.
While preferred embodiments are disclosed herein, many variations are possible which remain within the concept and scope of the invention. Such variations would become clear to one of ordinary skill in the art after inspection of the specification, drawings and claims herein. The invention therefore is not to be restricted except within the scope of the appended claims.
Patent Application
20080049038
