1. Field of the Invention
The present invention relates to a display device including a display unit having a light emitting element and a pixel circuit for each of pixels, and a drive unit driving the pixel circuit, and to a method for driving the same. The present invention also relates to an electronic device having the display device.
2. Description of the Related Art
In recent years, in the field of a display device for displaying an image, a display device using, as a light emitting element of a pixel, an optical element of a current driving type whose light emission luminance changes according to the value of a flowing current, for example, an organic EL (Electro Luminance) element is developed and is being commercialized.
An organic EL element is a spontaneous light emitting element different from a liquid crystal element or the like. Consequently, in a display device using an organic EL element (organic EL display device), a light source (backlight) is unnecessary. As compared with a liquid crystal display device necessitating a light source, visibility of an image is higher, power consumption is lower, and response of the element is faster.
As driving methods of the organic EL display device, as in the liquid crystal display device, there are a simple (passive) matrix method and an active matrix method. The simple (passive) matrix method has, although the structure is simple, a disadvantage in that a large-sized high-resolution display device is difficult to be realized. Consequently, at present, the active matrix method is actively developed. In the active matrix method, current flowing in a light emitting element disposed for each pixel is controlled by an active element (generally, TFT (Thin Film Transistor)) provided in a drive circuit arranged for each of the light emitting elements.
Generally, a current-voltage (I-V) characteristic of the organic EL element deteriorates with time (time-dependent degradation). In a pixel circuit for current-driving an organic EL element, when the I-V characteristic of the organic EL element changes with time, the voltage dividing ratio between the organic EL element and a drive transistor connected in series with the organic EL element changes, so that voltage Vgs between the gate and the source of a drive transistor also changes. As a result, the value of current flowing in the drive transistor changes, so that the value of current flowing in the organic EL element also changes, and the light emission luminance also changes according to the current value.
There is a case that a threshold voltage Vth of the drive transistor and mobility μ change with time, or differ among pixel circuits due to variations in manufacturing processes. In the case where the threshold voltage Vth of the drive transistor and mobility μ differ among pixel circuits, the value of current flowing in the drive transistor varies among pixel circuits. Consequently, even when the same voltage is applied to the gate of the drive transistor, the light emission luminance of the organic EL element varies, and uniformity of a screen deteriorates.
A display device is developed, which has a function of compensating fluctuations in the I-V characteristic of an organic EL element and a function of correcting fluctuations in a threshold voltage Vth and mobility μ of a drive transistor in order to maintain the light emission luminance of the organic EL element without being influenced by variations with time in the I-V characteristic of the organic EL element and variations with time in the threshold voltage Vth of the drive transistor and the mobility μ (see, for example, Japanese Unexamined Patent Application Publication Nos. 2007-171827, 2007-108381, 2007-133283, and 2007-133284).
Each pixel 120 includes a pixel 120R for red, a pixel 120G for green, and a pixel 120B for blue. As illustrated in
First, Vth correction is prepared. Concretely, the power source scan circuit 150 decreases the voltage of the drain line DSL from Vcc to Vini (T1). The source voltage Vs decreases to Vini, and light of the organic EL element 121R or the like goes out. At this time, the gate voltage Vg also decreases due to coupling via the retention capacitor Cs. Next, while the voltage of the signal line DTL is Vofs, the write scan circuit 140 increases the voltage of the gate line WSL from Voff to Von (T2). As a result, the transistor Tws is turned on, and the gate voltage Vg of the transistor TDr decreases to Vofs.
Next, Vth is corrected. Concretely, while the voltage of the signal line DTL is Vofs, the power source scan circuit 150 increases the voltage of the drain line DSL from Vini to Vcc (T3). Current Ids flows between the drain and source of the transistor TDr, so that the retention capacitor Cs and an element capacitor (not illustrated) such as the organic EL element 121R or the like are charged, and the source voltage Vs rises. After lapse of a predetermined period, the write scan circuit 140 decreases the voltage of the gate line WSL from Von to Voff (T4). The transistor Tws is turned off, the gate of the transistor TDr floats, and correction of Vth is temporarily stopped.
In a period in which Vth correction stops, the voltage of the signal line DTL is sampled in another row (pixel) different from a row (pixel) subjected to the Vth correction. In the case where the Vth correction is insufficient, that is, in the case where a potential difference Vgs between the gate and the source of the transistor TDr is larger than threshold voltage Vth of the transistor TDr, also in the Vth correction stop period, in the row (pixel) subjected to the Vth correction, current Ids flows between the drain and source of the transistor TDr, the source voltage Vs rises, and the gate voltage Vg also rises by the coupling via the retention capacitor Cs. Since reverse bias is applied to the organic EL element 121R or the like, the organic EL element 121R or the like does not emit light.
After completion of the Vth correction stop period, Vth is corrected again. Concretely, when the voltage of the signal line DTL is Vofs and Vth correction is possible, the write scan circuit 140 increases the voltage of the gate line WSL from Voff to Von (T5) and connects the gate of the transistor TDr to the signal line DTL. In the case where the source voltage Vs is lower than Vofs−Vth (in the case where the Vth correction has not been completed), the current Ids flows between the drain and source of the transistor TDr until the transistor TDr cuts off (until the voltage difference Vgs becomes Vth). As a result, the retention capacitor Cs is charged to Vth, and the potential difference Vgs becomes Vth. After that, before the horizontal drive circuit 130 switches the voltage of the signal line DTL from Vofs to Vsig, the write scan circuit 140 decreases the voltage of the gate line WSL from Von to Voff (T6). The gate of the transistor TDr floats so that the potential difference Vgs may be maintained at Vth irrespective of the magnitude of the voltage of the signal line DTL. By setting the potential difference Vgs to Vth as described above, also in the case where the threshold voltage Vth of the transistor TDr varies among the pixel circuits 122, light emission luminance of the organic EL elements 121R or the like may be prevented from varying.
After that, in the Vth correction stop period, the horizontal drive circuit 130 switches the voltage of the signal line DTL from Vofs to Vsig.
After completion of the Vth correction stop period, writing and μ correction are performed. Concretely, while the voltage of the signal line DTL is Vsig, the write scan circuit 140 increases the voltage of the gate line WSL from Voff to Von (T7) and connects the gate of the transistor TDr to the signal line DTL. As a result, the voltage of the gate of the transistor TDr becomes Vsig. The voltage of the anode of the organic EL element 121R or the like is still smaller than threshold voltage Vel of the organic EL element 121R or the like at this stage, and the organic EL element 121R or the like cuts off. Consequently, the current Ids flows to an element capacitor (not illustrated) of the organic EL element 121R or the like, and the element capacitor is charged. The source voltage Vs rises only by ΔV, and the potential difference Vgs becomes Vsig−Vofs+Vth−ΔV. In such a manner, μ correction is performed at the same time with the writing. The larger the mobility μ of the transistor TDr is, the larger ΔV becomes. Therefore, by decreasing the potential difference Vgs only by ΔV before light emission, the variations in the mobility μ per pixel may be eliminated.
Finally, the write scan circuit 140 decreases the voltage of the gate line WSL from Von to Voff (T8). The gate of the transistor TDr floats, the current Ids flows between the drain and source of the transistor TDr, and the source voltage Vs rises. As a result, the organic EL element 121R or the like emits light with desired luminance.
As described above, the potential difference Vg between the gate and the source of the transistor TDr finally becomes Vsig−Vofs+Vth−ΔV, and variations in the mobility μ of each pixel is corrected with ΔV. However, ΔV itself does not contribute to correction of the mobility μ. The difference (ΔΔV) between ΔV (ΔVa) of a transistor TDr having the largest mobility μ in all of the transistors TDr and ΔV (ΔVb) of a transistor TDr having the smallest mobility μ in all of the transistors TDr is used as a correction amount for realizing uniformity of luminance in an actual screen.
Each of
It is therefore desirable to provide a display device capable of reliably making μ correction function even in the case where light emission luminance is low, a method of driving the same, and an electronic device.
According to an embodiment of the present invention, there is provided a display device including a display unit having a light emitting element and a pixel circuit for each of pixels, and a drive unit driving the pixel circuit. The pixel circuit includes at least a transistor connected in series to the light emitting element. The drive unit has a first drive unit, a second drive unit, and a control unit. The first drive unit supplies a first voltage capable of applying a voltage equal to or larger than a threshold voltage of the light emitting element to the light emitting element, from a source or a drain of the transistor, which is on the side opposite to the light emitting element. The second drive unit supplies a second voltage having a magnitude according to the video signal and a third voltage having a predetermined magnitude from the gate side of the transistor. The control unit corrects the potential difference between the gate and the source of the transistor to a threshold voltage of the transistor, after that, while the second drive unit outputs the third voltage, outputs a control signal starting correction of mobility of the transistor and, subsequently, while the second drive unit outputs the second voltage, outputs a control signal starting writing of a voltage according to the second voltage to the gate of the transistor.
According to an embodiment of the present invention, there is provided an electronic device having the above-mentioned display device.
According to an embodiment of the present invention, there is provided a method of driving the display device that has the structure mentioned above executing the steps of correcting the potential difference between the gate and the source of the transistor to a threshold voltage of the transistor, after that, while the second drive unit outputs the third voltage, starting correction of mobility of the transistor and, subsequently, while the second drive unit outputs the second voltage, starting writing of a voltage according to the second voltage to the gate of the transistor.
The display device for which the above-mentioned driving method is used has: a display unit having a light emitting element and a pixel circuit for each of pixels; and a drive unit driving the pixel circuit. The pixel circuit includes at least a transistor connected in series to the light emitting element. The drive unit has a first drive unit and a second drive unit. The first drive unit supplies a first voltage capable of applying a voltage equal to or larger than a threshold voltage of the light emitting element to the light emitting element, from a source or a drain of the transistor, which is on the side opposite to the light emitting element. The second drive unit supplies a second voltage having a magnitude according to the video signal and a third voltage having a predetermined magnitude from the gate side of the transistor.
In the display device, the method of driving the same, and the electronic device of the embodiment of the present invention, the potential difference between the gate and the source of the transistor is corrected to a threshold voltage of the transistor. After that, while the second drive unit outputs the third voltage, correction of mobility of the transistor is started. Subsequently, while the second drive unit outputs the second voltage, writing of a voltage according to the second voltage to the gate of the transistor starts. In such a manner, correction of mobility of the transistor and writing of the voltage according to the second voltage to the gate of the transistor (hereinbelow, simply referred to as writing to the gate) are performed separately. Therefore, time necessary to correct mobility of the transistor may be set freely. Since mobility of the transistor is corrected by using the third voltage having the predetermined magnitude, the mobility of the transistor may be corrected irrespective of the light emission luminance.
In the display device, the method of driving the same, and the electronic device of the embodiment of the present invention, the potential difference between the gate and the source of the transistor is corrected to a threshold voltage of the transistor. After that, while the second drive unit outputs the third voltage, correction of mobility of the transistor is started. Subsequently, while the second drive unit outputs the second voltage, writing of a voltage according to the second voltage to the gate of the transistor starts. Therefore, time necessary to correct mobility of the transistor may be set freely. Further, mobility of the transistor is corrected irrespective of the light emission luminance. Consequently, even in the case where the light emission luminance is low, μ correction may be made function reliably.
Other and further objects, features and advantages of the invention will appear more fully from the following description.
Embodiments of the present invention will be described in detail hereinbelow with reference to the drawings.
The display unit 10 has a configuration in which a plurality of pixels 11 are arranged in a matrix on an entire surface of the display unit 10, and displays an image based on a video signal 20a input from the outside by active matrix drive. Each pixel 11 includes a pixel 11R for red, a pixel 11G for green, and a pixel 11B for blue.
Each of organic EL elements 12R, 12G, and 12B (hereinbelow, simply referred to as the organic EL element 12R or the like) has, for example, although not illustrated, a configuration in which an anode, an organic layer, and a cathode are stacked in order on a substrate 11. The organic layer has a stack-layer structure obtained by stacking, for example, in order from the side of the anode, a hole injection layer for increasing hole injection efficiency, a hole transport layer for increasing hole transport efficiency to a light emission layer, a light emission layer for emitting light by recombination of electrons and holes, and an electron transport layer for increasing efficiency of transporting electrons to the light emission layer.
The pixel circuit 13 includes a transistor Tws for sampling, a retention capacitor Cs, and a transistor TDr for driving, and has a circuit configuration of 2Tr1C. Each of the transistors Tws and TDr is configured by, for example, an n-channel MOS-type thin film transistor (TFT). The transistor TDr corresponds to a concrete example of a “transistor” of the present invention.
The peripheral circuit unit 20 has a timing control circuit 21 (control unit), a horizontal drive circuit 22 (second drive unit), a write scan circuit 23, and a power source scan circuit 24 (first drive unit). The timing control circuit 21 includes a display signal generation circuit 21A and a display signal retention control circuit 21B. The peripheral circuit unit 20 is provided with a gate line WSL, a drain line DSL, a signal line DTL, and a cathode line CTL. The cathode line CTL is connected to the ground and is set at the ground voltage.
On the basis of the video signal 20a input from the outside, the display signal generation circuit 21A generates a display signal 21a for displaying an image on the display unit 10, for example, screen by screen (field by field).
The display signal retention control circuit 21B stores and retains the display signal 21a output from the display signal generation circuit 21A in a field memory such as an SRAM (Static Random Access Memory) screen by screen (field by field). The display signal retention control circuit 21B also plays the role of controlling the horizontal drive circuit 22, the write scan circuit 23, and the power source scan circuit 24 for driving the pixels 11 so as to operate interlockingly. Concretely, the display signal retention control circuit 21B outputs a control signal 21b to the write scan circuit 23, outputs a control signal 21c to the power source scan circuit 24, and outputs a control signal 21d to the display signal drive circuit 21C.
The horizontal drive circuit 22 is possible to output three kinds of voltages (Vofs1, Vofs2 (third voltage), and Vsig (second voltage)) in accordance with the control signal 21d output from the display signal retention control circuit 21B. Concretely, the horizontal drive circuit 22 supplies the three kinds of voltages (Vofs1, Vofs2, and Vsig) to the pixel 11 selected by the write scan circuit 23 via the signal line DTL connected to the pixels 11 in the display unit 10.
In this case, Vofs2 is a voltage value higher than Vofs1 and is, for example, a voltage value in the range of the maximum voltage of Vsig or less. Vsig is a voltage value corresponding to the video signal 20a. The minimum voltage of Vsig has a voltage value lower than Vofs1, and the maximum voltage of Vsig has a voltage value higher than Vofs1.
The write scan circuit 23 is possible to output two kinds of voltages (Von and Voff) in accordance with the control signal 21b output from the display signal retention control circuit 21B. Concretely, the write scan circuit 23 supplies the two kinds of voltages (Von and Voff) to the pixel 11 to be driven via the gate line WSL connected to the pixels 11 in the display unit 10 and controls the transistor Tws for sampling.
At this time, Von is a value equal to or higher than the on-voltage of the transistor Tws. Von is a voltage value output from the write scan circuit 23 in a “Vth correction period”, a “μ correction period”, a “signal write period” or the like which will be described later. Voff is a value lower than the on-voltage of the transistor Tws and is also a value lower than Von. Voff is a voltage value output from the write scan circuit 23 in a “Vth correction preparation period”, “Vth correction stop period”, a “light emission period”, or the like which will be described later.
The power source scan circuit 24 is possible to output two kinds of voltages (Vini and Vcc (first voltage)) in accordance with the control signal 21c output from the display signal retention control circuit 21B. Concretely, the power source scan circuit 24 supplies the two kinds of voltages (Vini and Vcc) to the pixel 11 to be driven via the drain line DSL connected to the pixels 11 of the display unit 10, and controls light-on and light-off of the organic EL element 12R or the like.
Vini denotes a voltage value lower than a voltage (Vel+Vca) obtained by adding the threshold voltage Vel of the organic EL element 12R or the like and the voltage Vca of the cathode of the organic EL element 12R or the like. Vcc denotes a voltage value equal to or higher than the voltage (Vel+Vca).
With reference to
The cathode line CTL is connected to a voltage source (not illustrated). The voltage source supplies a predetermined voltage (for example, ground voltage) to the cathode line CTL. The voltage source is connected also to the horizontal drive circuit 22, the write scan circuit 23, and the power source scan circuit 24, supplies Vofs1, Vofs2, and Vsig to the horizontal drive circuit 22, supplies Von and Voff to the write scan circuit 23, and supplies Vcc and Vss to the power source scan circuit 24.
The operation (operation from light-off to light-on) of the display device 1 of the embodiment will now be described. In the embodiment, an operation of compensating fluctuations in the I-V characteristic of the organic EL element 12R or the like and an operation of correcting fluctuations in the threshold voltage Vth and mobility μ of the transistor TDr are included to maintain the light emission luminance of the organic EL element 12R or the like constant without being influenced by variations with time in the I-V characteristic of the organic EL element 12R or the like and variations with time in the threshold voltage Vth and the mobility μ of the transistor TDr.
First, Vth correction is prepared. Concretely, when the voltage of the gate line WSL is Voff, the voltage of the signal line DTL is Vofs1, and the voltage of the drain line DSL is Vcc (that is, the organic EL element 12R or the like emits light), the power source scan circuit 24 decreases the voltage of the drain line DSL from Vcc to Vini in accordance with the control signal 21c (T1). The source voltage Vs decreases to Vini, and light of the organic EL element 12R or the like goes out. At this time, the gate voltage Vg also decreases due to coupling via the retention capacitor Cs. Next, while the voltage of the drain line DSL is Vini and the voltage of the signal line DTL is Vofs1, the write scan circuit 23 increases the voltage of the gate line WSL from Voff to Von in accordance with the control signal 21b (T2). As a result, the gate voltage Vg drops to Vofs1. After that, when the voltage of the drain line DSL is Vini and the voltage of the signal line DTL is Vofs1, the write scan circuit 23 increases the voltage of the gate line WSL from Voff to Von in accordance with the control signal 21b.
Next, Vth is corrected. Concretely, while the voltage of the signal line DTL is Vofs1, the power source scan circuit 24 increases the voltage of the drain line DSL from Vss to Vcc in accordance with the control signal 21c (T3). Current Ids flows between the drain and source of the transistor TDr, and the source voltage Vs rises. After that, before the horizontal drive circuit 22 switches the voltage of the signal line DTL from Vofs1 to Vsig in accordance with the control signal 21d, the write scan circuit 23 decreases the voltage of the gate line WSL from Von to Voff in accordance with the control signal 21b (T4). The gate of the transistor TDr floats, and correction of Vth is temporarily stopped.
In a period in which Vth correction stops (that is, the voltage of the gate line WSL is Voff and the voltage of the drain line DSL is Vcc), the voltage of the signal line DTL is sampled in another row (pixel) different from a row (pixel) subjected to the Vth correction. Concretely, the horizontal drive circuit 22 switches the voltage of the signal line DTL from Vofs1 to Vsig during the period in which the Vth correction stops and, after that, performs an operation of switching the voltage from Vsig to Vofs1 and Vofs2 step by step. During the period in which the voltage of the signal line DTL is Vsig, Vofs1, or Vofs2, the write scan circuit 23 increases the voltage of the gate line WSL connected to another row (pixel) different from the row (pixel) subjected to the Vth correction from Voff to Von and, after that, switches the voltage from Von to Voff.
In the case where the Vth correction is insufficient, that is, in the case where the potential difference Vgs between the gate and the source of the transistor TDr is larger than threshold voltage Vth of the transistor TDr, also in the Vth correction stop period, in the row (pixel) subjected to the Vth correction, the current Ids flows between the drain and source of the transistor TDr, the source voltage Vs rises, and the gate voltage Vg also rises by the coupling via the retention capacitor Cs.
After completion of the Vth correction stop period, Vth is corrected again. Concretely, when the voltage of the drain line DSL is Vcc, the voltage of the signal line DTL is Vofs1, and Vth correction is possible, the write scan circuit 23 increases the voltage of the gate line WSL from Voff to Von in accordance with the control signal 21b (T5) and connects the gate of the transistor TDr to the signal line DTL. In the case where the source voltage Vs is lower than Vofs−Vth (in the case where the Vth correction has not been completed), the current Ids flows between the drain and source of the transistor TDr until the transistor TDr cuts off (until the voltage difference Vgs becomes Vth). As a result, the gate voltage Vg becomes Vofs1 and the source voltage Vs rises. As a result, the retention capacitor Cs is charged to Vth, and the potential difference Vgs becomes Vth. After that, before the horizontal drive circuit 22 switches the voltage of the signal line DTL from Vofs1 to Vsig, the write scan circuit 23 decreases the voltage of the gate line WSL from Von to Voff (T6). The gate of the transistor TDr floats so that the potential difference Vgs is maintained at Vth irrespective of the magnitude of the voltage of the signal line DTL. By setting the potential difference Vgs to Vth as described above, also in the case where the threshold voltage Vth of the transistor TDr varies among the pixel circuits 13, light emission luminance of the organic EL elements 12R or the like may be prevented from varying.
After that, in the Vth correction stop period (that is, in the period in which the voltage of the gate line WSL is Voff and the voltage of the drain line DSL is Vcc), the horizontal drive circuit 22 switches the voltage of the signal line DTL step by step from Vofs1 to Vsig and Vofs2 in accordance with the control signal 21d.
After completion of the second Vth correction stop period, μ correction is performed. Concretely, while the voltage of the signal line DTL is Vofs2, the write scan circuit 23 increases the voltage of the gate line WSL from Voff to Von in accordance with the control signal 21b (T7) and connects the gate of the transistor TDr to the signal line DTL. As a result, the voltage of the gate of the transistor TDr becomes the voltage Vofs2 of the signal line DTL. The voltage of the anode of the organic EL element 12R or the like is smaller than threshold voltage Vel of the organic EL element 12R or the like at this stage, and the organic EL element 12R or the like cuts off. Consequently, the current Ids flows to an element capacitor (not illustrated) of the organic EL element 12R or the like, and the element capacitor is charged. The source voltage Vs rises only by ΔV, and the potential difference Vgs becomes Vofs2−Vofs1+Vth−ΔV. In such a manner, μ correction is performed. The larger the mobility μ of the transistor TDr is, the larger ΔV becomes. Therefore, by decreasing the potential difference Vgs only by ΔV before light emission, the variations in the mobility μ per pixel may be eliminated.
After that, the write scan circuit 23 decreases the voltage of the gate line WSL from Von to Voff in accordance with the control signal 21b. Subsequently, when the voltage from the drain line DSL is Vcc and the voltage of the gate line WSL is Voff, the horizontal drive circuit 22 switches the voltage of the signal line DTL step by step from Vofs2 to Vofs1 and Vsig in accordance with the control signal 21d.
Following the μ correction, signal writing is performed. Concretely, while the voltage of the signal line DTL is Vsig, the write scan circuit 23 increases the voltage of the gate line WSL from Voff to Von in accordance with the control signal 21b (T8) and connects the gate of the transistor TDr to the signal line DTL. The voltage of the gate of the transistor TDr becomes the voltage Vsig of the signal line DTL (or the voltage corresponding to the Vsig). The voltage of the anode of the organic EL element 12R or the like is still smaller than the threshold voltage Vel of the organic EL element 12R or the like even at this stage, and the organic EL element 12R or the like is in a cutoff state. Consequently, the current Ids flows to an element capacitor (not illustrated) of the organic EL element 12R or the like, and the element capacitor is charged. The source voltage Vs rises only by ΔV, and the potential difference Vgs becomes Vsig−Vofs1+Vth−ΔV. In such a manner, the signal writing operation is performed. In the case where the μ correction was not sufficiently performed in the preceding μ correction period (that is, in the case where the μ correction time Ts is not sufficiently long), the μ correction is performed also in the signal writing period.
Finally, the write scan circuit 23 decreases the voltage of the gate line WSL from Von to Voff in accordance with the control signal 21b (T9). The gate of the transistor TDr floats, the current Ids flows between the drain and source of the transistor TDr, and the source voltage Vs rises. As a result, a voltage equal to or higher than the threshold voltage Vel is applied to the organic EL element 12R or the like, and the organic EL element 12R or the like emits light with desired luminance.
In the display device 1 of the embodiment, as described above, the pixel circuit 13 is on/off controlled in each of the pixels 11, and drive current flows in the organic EL element 12R or the like in each of the pixels 11, so that recombination of holes and electrons occurs and light emits. The light is multi-reflected between the anode and the cathode, passes the cathode or the like, and is taken to the outside. As a result, an image is displayed on the display unit 10.
As described above, the potential difference Vg between the gate and the source of the transistor TDr finally becomes Vsig−Vofs+Vth−ΔV, and variations in the mobility μ in each of the pixels are corrected with ΔV. However, ΔV itself does not contribute to correction of the mobility μ. The difference (ΔΔV) between ΔV (ΔVa) of a transistor TDr having the largest mobility μ in all of the transistors TDr and ΔV (ΔVb) of a transistor TDr having the smallest mobility μ in all of the transistors TDr is used as a correction amount for realizing uniformity of luminance in an actual screen.
It may be said from
On the other hand, in
The μ correction time Ts may be changed by changing the timing of starting the signal writing (the timing of increasing the voltage of the gate line WSL from Voff to Von). For example, it may be also changed by changing the arrangement order of three kinds of voltages (Vofs1, Vofs2, and Vsig) output from the horizontal drive circuit 22. In the above, as illustrated in
Application examples of the display device 1 described in the foregoing embodiment will be described below. The display device 1 of the embodiment is applicable to a display device of an electronic device in all of fields for displaying a video signal input from the outside or a video signal generated internally as an image or a video image, such as a television device, a digital camera, a notebook-sized personal computer, a portable terminal device such as a cellular phone, a video camera, or the like.
The display device 1 of the embodiment is assembled as, for example, a module as illustrated in
Although the present invention has been described above by the embodiment and the application examples, the present invention is not limited to the embodiment and the like but may be variously modified.
For example, in the embodiment and the like, the case where the display device 1 is of an active matrix type has been described. However, the configuration of the pixel circuit 13 for active matrix drive is not limited to that described in the foregoing embodiment and the like. As necessary, a capacitive element and a transistor may be added to the pixel circuit 13. In this case, according to a change in the pixel circuit 13, a necessary drive circuit may be provided in addition to the horizontal drive circuit 22, the write scan circuit 23, and the power source scan circuit 24.
In the embodiment and the like, the driving of the horizontal drive circuit 22, the write scan circuit 23, and the power source scan circuit 24 is controlled by the signal retention control circuit 21B. However, the driving of the circuits may be controlled by another circuit. The horizontal drive circuit 22, the write scan circuit 23, and the power source scan circuit 24 may be controlled by hardware (circuit) or software (program).
Although the pixel circuit 13 has the circuit configuration of 2Tr1C in the foregoing embodiment and the like, as long as the circuit configuration that a transistor is connected in series to the organic EL element 12R or the like is included, a circuit configuration other than the circuit configuration of 2Tr1C may be employed.
Although the case where the transistors Tws and TDr are thin film transistors (TFTs) of the n-channel MOS type has been described in the foregoing embodiment and the like, they may be p-channel transistors (for example, TFTs of the n-channel MOS type). In this case, it is preferable to connect the source or drain of the transistor TDr, which is not connected to the drain line DSL, and the other end of the retention capacitor Cs to the cathode of the organic EL element 12R or the like, and connect the anode of the organic EL element 12R or the like to the cathode line CTL.
Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.
Number | Date | Country | Kind |
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2008-197912 | Jul 2008 | JP | national |
This application is a continuation of U.S. patent application Ser. No. 12/507,998, filed Jul. 23, 2009, the entirety of which is incorporated herein by reference to the extent permitted by law. The present application claims the benefit of priority to Japanese Patent Application No. JP 2008-197912 filed in the Japan Patent Office on Jul. 31, 2008, the entirety of which is incorporated by reference herein to the extent permitted by law.
Number | Date | Country | |
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Parent | 12507998 | Jul 2009 | US |
Child | 13625349 | US |