Patent Grant
11928998
Embodiments of the invention relate to a display device, and more particularly to a display device that performs multi-frequency driving (“MFD”).
Reduction of power consumption is desirable in a display device employed in a portable device, such as a smartphone, a tablet computer, etc. Recently, a low frequency driving technique which drives or refreshes a display panel at a frequency lower than a normal driving frequency (e.g., about 60 Hz, about 100 Hz, about 120 Hz, etc.) may be used to reduce the power consumption of the display device.
In a display device to which the low frequency driving technique is applied, when a still image is not displayed in an entire region of a display panel, or when the still image is displayed only in a partial region of the display panel, the entire region of the display panel may be driven at a normal driving frequency. Thus, in this case, the low frequency driving may not be performed, and the power consumption may not be reduced.
Embodiments provide a display device with reduced power consumption by performing multi-frequency driving (“MFD”) and with improved display quality by reducing a luminance difference between a high frequency region and a low frequency region.
Embodiments provide a method of operating a display device for reducing power consumption by performing MFD and reducing a luminance difference between a high frequency region and a low frequency region.
According to an embodiment, a display device includes a display panel including a first partial panel region and a second partial panel region, and a panel driver which drives the display panel. In such an embodiment, the panel driver determines a first driving frequency for the first partial panel region and a second driving frequency for the second partial panel region. In such an embodiment, in a case where the second driving frequency is lower than the first driving frequency, the panel driver provides data voltages to the first and second partial panel regions in a first frame period, provides the data voltages to the first partial panel region in a second frame period, determines a voltage level of a blank voltage for the second partial panel region, and provides the blank voltage to the second partial panel region in the second frame period.
In an embodiment, in the first frame period, data writing and biasing operations for pixels of the first and second partial panel regions may be performed based on the data voltages. In such an embodiment, in the second frame period, the data writing and biasing operations for the pixels of the first partial panel region may be performed based on the data voltages, and biasing operations for the pixels of the second partial panel region may be performed based on the blank voltage.
In embodiments, in the first frame period, by the data writing and biasing operations, voltages generated by subtracting threshold voltages of driving transistors of the pixels of the first and second partial panel regions from the data voltages may be stored in storage capacitors of the pixels of the first and second partial panel regions, and first on-biases based on the data voltages may be applied to the driving transistors of the pixels of the first and second partial panel regions. In such an embodiment, in the second frame period, by the data writing and biasing operations, the voltages generated by subtracting the threshold voltages of the driving transistors of the pixels of the first partial panel region from the data voltages may be stored in the storage capacitors of the pixels of the first partial panel region, and the first on-biases based on the data voltages may be applied to the driving transistors of the pixels of the first partial panel region. In such an embodiment, in the second frame period, by the biasing operations, second on-biases based on the blank voltage may be applied to the driving transistors of the pixels of the second partial panel region.
In an embodiment, the panel driver may determine the voltage level of the blank voltage for the second partial panel region as a voltage level of the data voltage corresponding to a gray level higher than a black gray level.
In an embodiment, the panel driver may divide input image data for the display panel into first partial image data for the first partial panel region and second partial image data for the second partial panel region, and may determine the voltage level of the blank voltage for the second partial panel region by analyzing the second partial image data for the second partial panel region.
In an embodiment, the panel driver may determine a maximum gray level of gray levels represented by the second partial image data for the second partial panel region, and may determine the voltage level of the blank voltage for the second partial panel region as a voltage level of the data voltage corresponding to the maximum gray level.
In embodiments, the panel driver may determine a maximum gray level of gray levels represented by the second partial image data for the second partial panel region, and may determine the voltage level of the blank voltage for the second partial panel region as a voltage level of the data voltage corresponding to a gray level higher than a black gray level and lower than the maximum gray level.
In an embodiment, the panel driver may determine an average gray level of gray levels represented by the second partial image data for the second partial panel region, and may determine the voltage level of the blank voltage for the second partial panel region as a voltage level of the data voltage corresponding to the average gray level.
In an embodiment, the panel driver may divide input image data for the display panel into first partial image data for the first partial panel region and second partial image data for the second partial panel region, and may determine the voltage level of the blank voltage for the second partial panel region by analyzing the first partial image data for the first partial panel region.
In an embodiment, the panel driver may determine the voltage level of the blank voltage for the second partial panel region based on a maximum gray level or an average gray level of gray levels represented by the first partial image data for the first partial panel region.
In an embodiment, each pixel in the first and second partial panel regions may include a driving transistor which generates a driving current, a switching transistor which transfers the data voltage or the blank voltage to a source of the driving transistor in response to a gate writing signal, a compensation transistor which diode-connects the driving transistor in response to a gate compensation signal, a storage capacitor which stores a voltage generated by subtracting a threshold voltage of the driving transistor from the data voltage, a first initialization transistor which provides a first initialization voltage to the storage capacitor and a gate of the driving transistor in response to a gate initialization signal, a first emission transistor which couples a line of a power supply voltage to the source of the driving transistor in response to an emission signal, a second emission transistor which couples a drain of the driving transistor to an organic light emitting diode in response to the emission signal, a second initialization transistor which provides a second initialization voltage to the organic light emitting diode in response to the gate writing signal for a next pixel row, and the organic light emitting diode which emits light based on the driving current.
In an embodiment, at least one selected from the driving, switching, compensation, first initialization, first emission, second emission and second initialization transistors may be implemented with a p-type metal-oxide-semiconductor (“PMOS”) transistor, and at least one selected from the driving, switching, compensation, first initialization, first emission, second emission and second initialization transistors may be implemented with an n-type metal-oxide-semiconductor (“NMOS”) transistor.
In an embodiment, the panel driver may include a data driver which provides the data voltages or the blank voltage to the display panel, a scan driver which provides a gate initialization signal, a gate writing signal and a gate compensation signal to the display panel, an emission driver which provides an emission signal to the display panel, and a controller which controls the data driver, the scan driver and the emission driver, determines the first and second driving frequencies for the first and second partial panel regions, and determines the voltage level of the blank voltage for the second partial panel region.
In an embodiment, the controller may include a still image detector which divides input image data for the display panel into first partial image data for the first partial panel region and second partial image data for the second partial panel region, and determines whether each of the first and second partial image data represent a still image, a driving frequency decider which determines the first driving frequency for the first partial panel region according to whether the first partial image data represent the still image, and determines the second driving frequency for the second partial panel region according to whether the second partial image data represent the still image, and a blank voltage decider which determines the voltage level of the blank voltage.
In an embodiment, in a case where the first partial image data represent a moving image and the second partial image data represent the still image, the driving frequency decider may determine the first driving frequency as a normal driving frequency, and determine the second driving frequency as a low frequency lower than the normal driving frequency. In such an embodiment, the scan driver may provide the gate initialization signal, the gate writing signal and the gate compensation signal to each pixel of the first partial panel region at the normal driving frequency. In such an embodiment, the scan driver may provide the gate writing signal at the normal driving frequency to each pixel of the second panel region, and may provide the gate initialization signal and the gate compensation signal at the low frequency to each pixel of the second panel region.
In an embodiment, the display device may be a foldable display device, and a boundary between the first partial panel region and the second partial panel region may correspond to a folding line of the foldable display device.
According to an embodiment, a method of operating a display device includes: determining a first driving frequency for a first partial panel region of a display panel and a second driving frequency for a second partial panel region of the display panel; providing data voltages to the first and second partial panel regions in a first frame period in a case where the second driving frequency is lower than the first driving frequency; providing the data voltages to the first partial panel region in a second frame period in the case where the second driving frequency is lower than the first driving frequency; determining a voltage level of a blank voltage for the second partial panel region in the case where the second driving frequency is lower than the first driving frequency; and providing the blank voltage to the second partial panel region in the second frame period in the case where the second driving frequency is lower than the first driving frequency.
In an embodiment, the voltage level of the blank voltage for the second partial panel region may be determined as a voltage level of the data voltage corresponding to a gray level higher than a black gray level.
In an embodiment, input image data for the display panel may be divided into first partial image data for the first partial panel region and second partial image data for the second partial panel region, and the voltage level of the blank voltage for the second partial panel region may be determined by analyzing the second partial image data for the second partial panel region.
In an embodiment, input image data for the display panel may be divided into first partial image data for the first partial panel region and second partial image data for the second partial panel region, and the voltage level of the blank voltage for the second partial panel region may be determined by analyzing the first partial image data for the first partial panel region.
As described above, in embodiments of a display device and a method of operating the display device, a first driving frequency for a first partial panel region of a display panel and a second driving frequency for a second partial panel region of the display panel may be determined. In such embodiments, in a case where the second driving frequency is lower than the first driving frequency, data voltages may be provided to the first and second partial panel regions in a first frame period. In such embodiments, in a second frame period, the data voltages may be provided to the first partial panel region, a voltage level of a blank voltage for the second partial panel region may be determined, and the blank voltage may be provided to the second partial panel region. Accordingly, since the first and second partial panel regions are driven at different driving frequencies from each other, power consumption of the display device may be reduced. In such embodiments, a biasing operation for pixels in the second partial panel region may be performed based on not a black data voltage but the blank voltage, and thus a luminance difference between the first and second partial panel regions driven at the different driving frequencies may be reduced.
The above and other features of the invention will become more apparent by describing in further detail embodiments thereof with reference to the accompanying drawings.
The invention now will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. This invention may, however, be embodied in many different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.
It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
It will be understood that, although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, “a first element,” “component,” “region,” “layer” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a”, “an,” “the,” and “at least one” do not denote a limitation of quantity, and are intended to include both the singular and plural, unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element,” unless the context clearly indicates otherwise. “At least one” is not to be construed as limiting “a” or “an.” “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The term “lower,” can therefore, encompasses both an orientation of “lower” and “upper,” depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
“About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, 20%, 10% or 5% of the stated value.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.
Hereinafter, embodiments of the invention will be described in detail with reference to the accompanying drawings.
Referring to
The display panel 110 may include a first partial panel region PPR1 and a second partial panel region PPR2. In one embodiment, for example, the display panel 110 may be divided into the first partial panel region PPR1 and the second partial panel region PPR2, and each of the first and second partial panel regions PPR1 and PPR2 includes two or more scan lines, or two or more pixel rows connected to the two or more scan lines.
In an embodiment, the first partial panel region PPR1 and the second partial panel region PPR2 may have fixed partial regions within the display panel 110. In one embodiment, for example, the display device 100 may be a foldable display device, and a boundary between the first partial panel region PPR1 and the second partial panel region PPR2 may correspond to a folding line of the foldable display device.
In an embodiment, as illustrated in
In an embodiment, the first partial panel region PPR1 and the second partial panel region PPR2 may be dynamically changed within the display panel 110. In one embodiment, for example, as illustrated in
Although
The display panel 110 may include a plurality of data lines, a plurality of scan lines, a plurality of emission lines and a plurality of pixels PX coupled thereto. In such an embodiment, each of the first partial panel region PPR1 and the second partial panel region PPR2 may include the plurality of pixels PX. In an embodiment, the plurality of scan lines may include a plurality of gate initialization lines, a plurality of gate writing lines and a plurality of gate compensation lines. In such an embodiment, each pixel PX may include at least one capacitor, at least two transistors and an organic light emitting diode (“OLED”), and the display panel 110 may be an OLED display panel. In an embodiment, each pixel PX may be a hybrid oxide polycrystalline (“HOP”) pixel suitable for low frequency driving capable of reducing power consumption. In one embodiment, for example, in the HOP pixel, at least one first transistor may be implemented with a low-temperature polycrystalline silicon (“LTPS”) p-type metal-oxide-semiconductor (“PMOS”) transistor, and at least one second transistor may be implemented with an oxide n-type metal-oxide-semiconductor (“NMOS”) transistor.
In one embodiment, for example, as illustrated in
At least one selected from the driving transistor T1, the switching transistor T2, the compensation transistor T3, the first initialization transistor T4, the first emission transistor T5, the second emission transistor T6 and the second initialization transistor T7 may be implemented with a PMOS transistor, and at least one selected from the driving transistor T1, the switching transistor T2, the compensation transistor T3, the first initialization transistor T4, the first emission transistor T5, the second emission transistor T6 and the second initialization transistor T7 may be implemented with an NMOS transistor. In one embodiment, for example, as illustrated in
Referring back to
The scan driver 130 may generate scan signals GI, GW and GC based on a scan control signal SCTRL received from the controller 150, and may sequentially provide the scan signals GI, GW and GC to the plurality of pixels PX on a row-by-row basis through the plurality of scan lines. In an embodiment, the scan signals GI, GW and GC may include the gate initialization signals GI, the gate writing signals GW and the gate compensation signals GC. In one embodiment, for example, with respect to the pixels PX in each row, the scan driver 130 may apply the gate initialization signal GI to the pixels PX, and then may apply the gate writing signal GW and the gate compensation signal GC to the pixels PX. In an embodiment, in the holding period, the scan driver 130 may not apply the gate initialization signal GI and the gate compensation signal GC to the pixels PX driven at the low frequency, and may apply only the gate writing signal GW to the pixels PX driven at the low frequency. In an embodiment, the scan control signal SCTRL may include, but not limited to, a scan start signal and a scan clock signal. In an embodiment, the scan driver 130 may be integrated or formed in a peripheral portion of the display panel 110. In an alternative embodiment, the scan driver 130 may be implemented with one or more integrated circuits.
The emission driver 140 may generate the emission signals EM based on an emission control signal EMCTRL received from the controller 150, and may sequentially provide the emission signals EM to the plurality of pixels PX on a row-by-row basis through the plurality of emission lines. In an embodiment, the emission control signal EMCTRL may include, but not limited to, an emission start signal and an emission clock signal. In an embodiment, the emission driver 140 may be integrated or formed in a peripheral portion of the display panel 110. In an alternative embodiment, the emission driver 140 may be implemented with one or more integrated circuits.
The controller (e.g., a timing controller (“TCON”)) 150 may receive the input image data IDAT and a control signal CTRL from an external host (e.g., a graphic processing unit (GPU) or a graphic card). In an embodiment, the control signal CTRL may include, but not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. The controller 150 may generate the output image data ODAT, the data control signal DCTRL, the scan control signal SCTRL and the emission control signal EMCTRL based on the input image data IDAT and the control signal CTRL. The controller 150 may control an operation of the data driver 120 by providing the output image data ODAT and the data control signal DCTRL to the data driver 120, may control an operation of the scan driver 130 by providing the scan control signal SCTRL to the scan driver 130, and may control an operation of the emission driver 140 by providing the emission control signal EMCTRL to the emission driver 140.
In an embodiment, the panel driver 190 of the display device 100 may determine a first driving frequency for the first partial panel region PPR1 and a second driving frequency for the second partial panel region PPR2. In an embodiment, the first and second driving frequencies may be different from each other, and the panel driver 190 may perform multi-frequency driving (“MFD”) that drives the first and second partial panel regions PPR1 and PPR2 at the first and second driving frequencies, which are different from each other. In one embodiment, for example, in a case where a moving image is displayed in the first partial panel region PPR1, and a still image is displayed in the second partial panel region PPR2, the panel driver 190 may determine the first driving frequency for the first partial panel region PPR1 as a normal driving frequency (e.g., about 60 Hz, about 100 Hz, about 120 Hz, etc.), may determine the second driving frequency as the low frequency lower than the normal driving frequency, may drive the first partial panel region PPR1 at the normal driving frequency, and may drive the second partial panel region PPR2 at the low frequency. In an embodiment, the controller 150 of the panel driver 190 may include a still image detector 160 and a driving frequency decider 170 to determine the first and second driving frequencies for the first and second partial panel regions PPR1 and PPR2.
The still image detector 160 may divide the input image data IDAT for the display panel 110 into first partial image data for the first partial panel region PPR1 and second partial image data for the second partial panel region PPR2, and may determine whether each of the first and second partial image data represent a still image. In an embodiment, the still image detector 160 may determine whether the first partial image data represent the still image by comparing the first partial image data in a previous frame period and the first partial image data in a current frame period, and may determine whether the second partial image data represent the still image by comparing the second partial image data in the previous frame period and the second partial image data in the current frame period.
The driving frequency decider 170 may determine the first driving frequency for the first partial panel region PPR1 according to whether the first partial image data represent the still image, and may determine the second driving frequency for the second partial panel region PPR2 according to whether the second partial image data represent the still image. In an embodiment, the driving frequency decider 170 may determine the first driving frequency for the first partial panel region PPR1 as the normal driving frequency (e.g., about 60 Hz, about 100 Hz, about 120 Hz, etc.) when the first partial image data do not represent the still image (or when the first partial image data represent a moving image), and may determine the first driving frequency for the first partial panel region PPR1 as the low frequency lower than the normal driving frequency when the first partial image data represent the still image. In such an embodiment, the driving frequency decider 170 may determine the second driving frequency for the second partial panel region PPR2 as the normal driving frequency when the second partial image data do not represent the still image (or when the second partial image data represent the moving image), and may determine the second driving frequency for the second partial panel region PPR2 as the low frequency lower than the normal driving frequency when the second partial image data represent the still image. In an embodiment, in a case where the second partial image data represent the still image, the driving frequency decider 170 may determine a flicker value (that represents a level of a flicker perceived by a user) according to a gray level (or luminance) of the second partial image data by using a flicker lookup table that stores flicker values corresponding to respective gray levels, and may determine the second driving frequency according to the flicker value. In such an embodiment, determining the flicker value may be performed on a pixel-by-pixel basis, a segment-by-segment basis, or a partial panel region-by-partial panel region basis.
In a case where all of the first and second driving frequencies for the first and second partial panel regions PPR1 and PPR2 are determined as the normal driving frequency by the still image detector 160 and the driving frequency decider 170, the panel driver 190 may drive the first and second partial panel regions PPR1 and PPR2 at the normal driving frequency. In one embodiment, for example, as illustrated in
In an embodiment, the gate initialization signal GI may be first applied to each pixel PX, and then the gate writing signal GW and the gate compensation signal GC along with the data voltage VDATA may be applied to each pixel PX. While the gate writing signal GW, the gate compensation signal GC and the data voltage VDATA are applied to each pixel PX, a data writing and biasing operation for the pixel PX may be performed based on the data voltage VDATA as illustrated in
In a case where the first driving frequency for the first partial panel region PPR1 and the second driving frequency for the second partial panel region PPR2 are determined as the normal driving frequency and the low frequency lower than the normal driving frequency, respectively, by the still image detector 160 and the driving frequency decider 170, respectively, the panel driver 190 may drive the first partial panel region PPR1 at the normal driving frequency, and may drive the second partial panel region PPR2 at the low frequency. In one embodiment, for example, in a case where the normal driving frequency is about 60 Hz, and the low frequency is about 30 Hz, as illustrated in
However, to drive the second partial panel region PPR2 at the low frequency, a period allocated for the second partial panel region PPR2 within the first frame period FP1 may be set as the data writing period DWP, and a period allocated for the second partial panel region PPR2 within the second frame period FP2 may be set as a holding period HP. Although
In an embodiment shown in
However, with respect to the second partial panel region PPR2, in the holding period HP for the second partial panel region PPR2 in the second frame period FP2, the scan driver 130 may not provide the gate initialization signal GI and the gate compensation signal GC to each pixel PX of the second partial panel region PPR2, the data driver 120 may not provide the data voltage VDATA to each pixel PX of the second partial panel region PPR2, and the data driver 120 may provide the blank voltage VBLANK as the voltage V_DL of the data line DL to each pixel PX of the second partial panel region PPR2. In an embodiment, in the holding period HP for the second partial panel region PPR2 in the second frame period FP2, the scan driver 130 may provide the gate writing signal GW to each pixel PX of the second partial panel region PPR2. Since the gate writing signal GW is provided to each pixel PX of the second partial panel region PPR2 in each frame period FP1 and FP2, and the gate initialization and compensation signals GI and GC are not provided to each pixel PX of the second partial panel region PPR2 only in the first frame period FP1, the gate writing signal GW may be provided to each pixel PX of the second partial panel region PPR2 at the normal driving frequency, and the gate initialization and compensation signals GI and GC may be provided to each pixel PX of the second partial panel region PPR2 at the low frequency.
In the holding period HP in which the gate initialization and compensation signals GI and GC are not provided to each pixel PX of the second partial panel region PPR2 and the gate writing signal GW and the blank voltage VBLANK are provided to each pixel PX of the second partial panel region PPR2, a biasing operation for the pixel PX may be performed based on the blank voltage VBLANK as illustrated in
In a case where the blank voltage VBLANK has a voltage level of the data voltage VDATA corresponding to a black gray level (e.g., the minimum gray level of 0 or 0 G), or a voltage level of a black data voltage VBLACK, the second on-bias based on the blank voltage VBLANK may be different from the first on-bias based on the data voltage VDATA, the hysteresis of the driving transistor T1 of the pixel PX to which the second on-bias is applied may be different from the hysteresis of the driving transistor T1 of the pixel PX to which the first on-bias is applied. In one embodiment, for example, as illustrated in
In an embodiment of the display device 100 according to the invention, as shown in
In an alternative embodiment, the input image data IDAT for the display panel 110 may be divided into the first partial image data for the first partial panel region PPR1 and the second partial image data for the second partial panel region PPR2, and the blank voltage decider 180 may determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 by analyzing the second partial image data for the second partial panel region PPR2. In one embodiment, for example, the blank voltage decider 180 may determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 based on a maximum gray level or an average gray level of gray levels represented by the second partial image data. In another alternative embodiment, the blank voltage decider 180 may determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 by analyzing the first partial image data for the first partial panel region PPR1. In one embodiment, for example, the blank voltage decider 180 may determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 based on a maximum gray level or an average gray level of gray levels represented by the first partial image data.
As described above, in embodiments of the display device 100 according to the invention, the first driving frequency for the first partial panel region PPR1 of the display panel 110 and the second driving frequency for the second partial panel region PPR2 of the display panel 110 may be determined. In a case where the second driving frequency is lower than the first driving frequency, the data voltages VDATA may be provided to the first and second partial panel regions PPR1 and PPR2 in the first frame period FP1. Further, in the second frame period FP2, the data voltages VDATA may be provided to the first partial panel region PPR1, the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 may be determined, and the blank voltage VBLANK may be provided to the second partial panel region PPR2. Accordingly, in such an embodiment, the first and second partial panel regions PPR1 and PPR2 are driven at different driving frequencies from each other, such that power consumption of the display device 100 may be reduced. In such an embodiment, the biasing operation for the pixels PX in the second partial panel region PPR2 may be performed based on not the black data voltage VBLACK but the blank voltage VBLANK, and thus the luminance difference between the first and second partial panel regions PPR1 and PPR2 when driven at the different driving frequencies from each other may be reduced.
Referring to
In a case where the second driving frequency is lower than the first driving frequency, for example in a case where the first driving frequency for the first partial panel region PPR1 is determined as the normal driving frequency, the second driving frequency for the second partial panel region PPR2 is determined as the low frequency, the panel driver 190 may provide data voltages VDATA to the first and second partial panel regions PPR1 and PPR2 in a first frame period (S330). In one embodiment, for example, as illustrated in
In an embodiment, as illustrated in
The panel driver 190 may provide the data voltages VDATA to the first partial panel region PPR1 in a second frame period (S350). In one embodiment, for example, as illustrated in
The panel driver 190 may determine a voltage level of a blank voltage VBLANK for the second partial panel region PPR2 (S370). In an embodiment, the panel driver 190 may determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 as a voltage level of the data voltage VDATA corresponding to a gray level higher than a black gray level. In one embodiment, for example, the panel driver 190 may determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 as a voltage level of the data voltage VDATA corresponding to a 128-gray level (128G).
The panel driver 190 may provide the blank voltage VBLANK to the second partial panel region PPR2 in the second frame period (S390). In one embodiment, for example, as illustrated in
In the holding period HP for the second partial panel region PPR2 within the second frame period FP2, if the gate writing signals GW[k+1], GW[k+2], . . . and the blank data VBLANK are applied to the pixels PX of the second partial panel region PPR2, as illustrated in
A method of
Referring to
In a case where the second driving frequency is lower than the first driving frequency, the panel driver 190 may provide data voltages VDATA to the first and second partial panel regions PPR1 and PPR2 in a first frame period (S430). Thus, in the first frame period, data writing and biasing operations for pixels PX of the first and second partial panel regions PPR1 and PPR2 may be performed based on the data voltages VDATA, and first on-biases based on the data voltages VDATA may be applied to driving transistors of the pixels PX.
The panel driver 190 may provide the data voltages VDATA to the first partial panel region PPR1 in a second frame period (S450). Thus, in the second frame period, the data writing and biasing operations for the pixels PX of the first partial panel region PPR1 may be performed based on the data voltages VDATA, and the first on-biases based on the data voltages VDATA may be applied to the driving transistors of the pixels PX of the first partial panel region PPR1.
The panel driver 190 may divide input image data IDAT for the display panel 110 into first partial image data for the first partial panel region PPR1 and second partial image data for the second partial panel region PPR2, may analyze the second partial image data for the second partial panel region PPR2 (S460), and may determine a voltage level of a blank voltage VBLANK for the second partial panel region PPR2 based on a result of the analysis (S470). In one embodiment, for example, as illustrated in
In some embodiments, the panel driver 190 may determine the maximum gray level MGV of gray levels represented by the second partial image data by using the histogram 500 of the second partial image data, and may determine the voltage level of the blank voltage VBALNK for the second partial panel region PPR2 as a voltage level of the data voltage VDATA corresponding to the maximum gray level MGV. In an embodiment of
In an alternative embodiment, the panel driver 190 may determine the maximum gray level MGV of gray levels represented by the second partial image data by using the histogram 500 of the second partial image data, and may determine the voltage level of the blank voltage VBALNK for the second partial panel region PPR2 as a voltage level of the data voltage VDATA corresponding to a gray level higher than the black gray level 0G and lower than the maximum gray level MGV. In one embodiment, for example, the panel driver 190 may determine the voltage level of the blank voltage VBALNK for the second partial panel region PPR2 as a voltage level of the data voltage VDATA corresponding to a 75-gray level that is a middle value between the 0-gray level 0G and the 150-gray level 150G.
In another alternative embodiment, the panel driver 190 may determine an average gray level of gray levels represented by the second partial image data by using the histogram 500 of the second partial image data, and may determine the voltage level of the blank voltage VBALNK for the second partial panel region PPR2 as a voltage level of the data voltage VDATA corresponding to the average gray level.
The panel driver 190 may provide the blank voltage VBLANK to the second partial panel region PPR2 in the second frame period (S490). Thus, in the second frame period, biasing operations for the pixels PX of the second partial panel region PPR2 may be performed based on the blank data VBLANK, and second on-biases based on the blank data VBLANK may be applied to the driving transistors of the pixels PX of the second partial panel region PPR2. Since the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 is determined by analyzing the second partial image data for the second partial panel region PPR2, a difference between the first on-bias based on the data voltage VDATA and the second on-bias based on the blank voltage VBLANK may be reduced, and a hysteresis difference between the driving transistors of the first and second partial panel regions PPR1 and PPR2 may be reduced.
A method of
Referring to
In a case where the second driving frequency is lower than the first driving frequency, the panel driver 190 may provide data voltages VDATA to the first and second partial panel regions PPR1 and PPR2 in a first frame period (S630). Thus, in the first frame period, data writing and biasing operations for pixels PX of the first and second partial panel regions PPR1 and PPR2 may be performed based on the data voltages VDATA, and first on-biases based on the data voltages VDATA may be applied to driving transistors of the pixels PX.
The panel driver 190 may provide the data voltages VDATA to the first partial panel region PPR1 in a second frame period (S650). Thus, in the second frame period, the data writing and biasing operations for the pixels PX of the first partial panel region PPR1 may be performed based on the data voltages VDATA, and the first on-biases based on the data voltages VDATA may be applied to the driving transistors of the pixels PX of the first partial panel region PPR1.
The panel driver 190 may divide input image data IDAT for the display panel 110 into first partial image data for the first partial panel region PPR1 and second partial image data for the second partial panel region PPR2, may analyze the first partial image data for the first partial panel region PPR1 (S660), and may determine a voltage level of a blank voltage VBLANK for the second partial panel region PPR2 based on a result of the analysis (S670). In one embodiment, for example, the panel driver 190 may generate a histogram of the first partial image data, and may determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 by using the histogram of the first partial image data. In an embodiment, the panel driver 190 may determine the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 based on a maximum gray level or an average gray level of gray levels represented by the first partial image data.
The panel driver 190 may provide the blank voltage VBLANK to the second partial panel region PPR2 in the second frame period (S690). Thus, in the second frame period, biasing operations for the pixels PX of the second partial panel region PPR2 may be performed based on the blank data VBLANK, and second on-biases based on the blank data VBLANK may be applied to the driving transistors of the pixels PX of the second partial panel region PPR2. Since the voltage level of the blank voltage VBLANK for the second partial panel region PPR2 is determined by analyzing the second partial image data for the second partial panel region PPR2, a difference between the first on-bias based on the data voltage VDATA and the second on-bias based on the blank voltage VBLANK may be reduced, and a hysteresis difference between the driving transistors of the first and second partial panel regions PPR1 and PPR2 may be reduced.
Referring to
The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (“AP”), a microprocessor or a central processing unit (“CPU”), etc. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, etc. In an embodiment, the processor 1110 may be further coupled to an extended bus such as a peripheral component interconnection (“PCI”) bus.
The memory device 1120 may store data for operations of the electronic device 1100. In one embodiment, for example, the memory device 1120 may include a non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase change random access memory (“PRAM)” device, a resistance random access memory (“RRAM”) device, a nano floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, etc., and/or a volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile DRAM device, etc.
The storage device 1130 may be a solid state drive (“SSD”) device, a hard disk drive (“HDD”) device, a CD-ROM device, etc. The I/O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 1150 may supply power for operations of the electronic device 1100. The display device 1160 may be coupled to other components through the buses or other communication links.
In an embodiment of the display device 1160, a first driving frequency for a first partial panel region of a display panel and a second driving frequency for a second partial panel region of the display panel may be determined. In a case where the second driving frequency is lower than the first driving frequency, data voltages may be provided to the first and second partial panel regions in a first frame period. In such an embodiment, in a second frame period, the data voltages may be provided to the first partial panel region, a voltage level of a blank voltage for the second partial panel region may be determined, and the blank voltage may be provided to the second partial panel region. Accordingly, since the first and second partial panel regions are driven at different driving frequencies, power consumption of the display device may be reduced. In such an embodiment, a biasing operation for pixels in the second partial panel region may be performed based on not a black data voltage but the blank voltage, and thus a luminance difference between the first and second partial panel regions driven at the different driving frequencies may be reduced.
Embodiments of the invention may be applied to any display device 1160, and any electronic device 1100 including the display device 1160. In one embodiment, for example, the inventions may be applied to a mobile phone, a smart phone, a wearable electronic device, a tablet computer, a television (“TV”), a digital TV, a three-dimensional (“3D”) TV, a personal computer (“PC”), a home appliance, a laptop computer, a personal digital assistant (“PDA”), a portable multimedia player (“PMP”), a digital camera, a music player, a portable game console, a navigation device, etc.
The invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art.
While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2020-0091894 | Jul 2020 | KR | national |
This application is a continuation of U.S. patent application Ser. No. 17/202,769, filed on Mar. 16, 2021, which claims priority to Korean Patent Application No. 10-2020-0091894, filed on Jul. 23, 2020, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference.
| Number | Name | Date | Kind |
|---|---|---|---|
| 20030048246 | Ham | Mar 2003 | A1 |
| 20070030219 | Park et al. | Feb 2007 | A1 |
| 20070229447 | Takahara | Oct 2007 | A1 |
| 20090273555 | Song | Nov 2009 | A1 |
| 20100134401 | Shin et al. | Jun 2010 | A1 |
| 20130038621 | Choi et al. | Feb 2013 | A1 |
| 20130113811 | Choi et al. | May 2013 | A1 |
| 20150170607 | Shin | Jun 2015 | A1 |
| 20150243204 | Park et al. | Aug 2015 | A1 |
| 20160063914 | Lee et al. | Mar 2016 | A1 |
| 20160078846 | Liu et al. | Mar 2016 | A1 |
| 20160111055 | Na | Apr 2016 | A1 |
| 20160275903 | Park | Sep 2016 | A1 |
| 20170018234 | Na et al. | Jan 2017 | A1 |
| 20170116946 | Nakatani et al. | Apr 2017 | A1 |
| 20180040289 | Lee et al. | Feb 2018 | A1 |
| 20180286314 | Cho et al. | Oct 2018 | A1 |
| 20190005862 | Zhang | Jan 2019 | A1 |
| 20190033919 | Hirakata et al. | Jan 2019 | A1 |
| 20200211475 | Park et al. | Jul 2020 | A1 |
| 20200394984 | Park | Dec 2020 | A1 |
| 20210118378 | Son et al. | Apr 2021 | A1 |
| 20210201800 | Ahn et al. | Jul 2021 | A1 |
| Number | Date | Country |
|---|---|---|
| 100923347 | Oct 2009 | KR |
| 1020190085209 | Jul 2019 | KR |
| 102005872 | Aug 2019 | KR |
| Entry |
|---|
| Extended European Search Report—European Application No. 21186774.2 dated Nov. 15, 2021, citing references listed within. |
| European Office Action for Application No. 21 186 774.2-1210 dated Jan. 17, 2024. |
| Number | Date | Country | |
|---|---|---|---|
| 20230196959 A1 | Jun 2023 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17202769 | Mar 2021 | US |
| Child | 18108838 | US |
