Patent Grant
11587518
This application is a 371 of international application PCT/IB2018/059811 filed on Dec. 10, 2018 which is incorporated herein by reference.
One embodiment of the present invention relates to a display device, a semiconductor device, and an electronic device.
Furthermore, one embodiment of the present invention relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. One embodiment of the present invention relates to a driving method thereof or a manufacturing method thereof.
In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A memory device, a display device, an electro-optical device, a power storage device, a semiconductor circuit, and an electronic device include a semiconductor device in some cases.
A silicon-based semiconductor material is widely known as a semiconductor thin film that can be used in a transistor; in addition, an oxide semiconductor has been attracting attention as another material. As an example of the oxide semiconductor, not only single-component metal oxides such as indium oxide and zinc oxide but also multi-component metal oxides are known. Among the multi-component metal oxides, in particular, an In—Ga—Zn oxide (hereinafter also referred to as IGZO) has been actively studied.
From the studies on IGZO, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are not single crystal nor amorphous, have been found in an oxide semiconductor (see Non-Patent Document 1 to Non-Patent Document 3). Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for fabricating a transistor using an oxide semiconductor having a CAAC structure. Moreover, Non-Patent Document 4 and Non-Patent Document 5 show that a fine crystal is included even in an oxide semiconductor which has lower crystallinity than the CAAC structure or the nc structure.
In addition, a transistor that uses IGZO for an active layer has an extremely low off-state current (see Non-Patent Document 6), and an LSI and a display utilizing the characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8).
In addition, a driver circuit has been reported in which data corresponding to a gamma value of a display element can be output owing to a high-resolution digital-analog converter circuit included in the driver circuit (see Non-Patent Document 9).
In addition, Patent Document 1 discloses a semiconductor device in which a display element included in a display device can be driven at a high voltage.
[Patent Document 1] Japanese Published Patent Application No. 2011-227479
[Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp. 183-186.
[Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, pp. 04ED18-1-04ED18-10.
[Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, pp. 151-154.
[Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, pp. Q3012-Q3022.
[Non-Patent Document 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, pp. 155-164.
[Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, pp. 021201-1-021201-7.
[Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, pp. T216-T217.
[Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, pp. 626-629.
[Non-Patent Document 9] Seong-Young Ryu et al., “Journal of the SID”, 2016, volume 24, issue 5, pp. 277-285.
An object of one embodiment of the present invention is to provide a novel display device. Another object of one embodiment of the present invention is to provide a novel method for driving a display device. Another object of one embodiment of the present invention is to provide a semiconductor device that suppresses an increase in power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device that holds data without being influenced by temperature change.
Note that the description of a plurality of objects does not preclude the existence of each object. One embodiment of the present invention does not necessarily achieve all these objects. Objects other than those listed above will be apparent from the description of the specification, the drawings, the claims, and the like, and such objects could be objects of one embodiment of the present invention.
One embodiment of the present invention is a display device including a pixel; the pixel is supplied with a first data potential and a second data potential included in the range of a first potential or higher to a second potential or lower. The first data potential has a function of making the pixel display an image with a first gray level. The pixel has a function of performing calculation with the first data potential and the second data potential to generate a third data potential. The third data potential has a function of making the pixel display an image with a second gray level. A reference potential of the first data potential is an intermediate potential between the first potential and the second potential, and a gray level width that can be displayed by the second data potential is larger than a gray level width that can be displayed by the first data potential.
In the above embodiment, the display device includes the pixel, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring. The pixel includes a first transistor, a second transistor, a first capacitor, a second capacitor, and a display element. A gate of the first transistor is electrically connected to the third wiring. One of a source and a drain of the first transistor is electrically connected to the first wiring. The other of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor, one electrode of the second capacitor, and one electrode of the display element. A gate of the second transistor is electrically connected to the fourth wiring. One of a source and a drain of the second transistor is electrically connected to the second wiring. The other of the source and the drain of the second transistor is electrically connected to the other electrode of the second capacitor. The fifth wiring is electrically connected to the other electrode of the first capacitor and the other electrode of the display element.
In the above embodiment, the display device preferably includes a liquid crystal element as the display element included in the pixel.
In the above embodiment, in the display device, the first transistor or the second transistor preferably includes a metal oxide in a semiconductor layer.
One embodiment of the present invention is a semiconductor device including a display device, a source driver, a first wiring, and a second wiring. The display device includes a pixel. The source driver includes a digital-analog converter circuit, a buffer circuit, a first switch, a second switch, a third switch, a fourth switch, and a switch control circuit. The pixel is electrically connected to the first wiring and the second wiring. The digital-analog converter circuit includes a first output terminal, a second output terminal, and a third output terminal. The first output terminal is electrically connected to a first input terminal included in the buffer circuit. An output terminal of the buffer circuit is electrically connected to one electrode of the third switch, one electrode of the fourth switch, and a second input terminal included in the buffer circuit. The second output terminal is electrically connected to one electrode of the first switch. The third output terminal is electrically connected to one electrode of the second switch. The first wiring is electrically connected to the other electrode of the fourth switch. The second wiring is electrically connected to the other electrode of the first switch, the other electrode of the second switch, and the other electrode of the third switch. The switch control circuit can control the first switch, the second switch, the third switch, and the fourth switch independently. The first output terminal can output a voltage in the range of a first potential to a second potential. The second output terminal can output the first potential. The third output terminal outputs the second potential.
An electronic device including the above-described semiconductor device and a temperature sensor is preferable.
According to one embodiment of the present invention, a novel display device can be provided. According to one embodiment of the present invention, a novel method for driving a display device can be provided. According to one embodiment of the present invention, a semiconductor device that suppresses an increase in power consumption can be provided. According to one embodiment of the present invention, a semiconductor device that holds data without being influenced by temperature change can be provided.
Note that the description of the effects do not disturb the existence of other effects. One embodiment of the present invention does not have to have all of these effects. Effects other than these will be apparent from the description of the specification, the drawings, the claims, and the like and effects other than these can be derived from the description of the specification, the drawings, the claims, and the like.
FIGS. 16A1-16C2 are cross-sectional views each illustrating a structure example of a transistor.
FIGS. 17A1-17C2 are cross-sectional views each illustrating a structure example of a transistor.
FIGS. 18A1-18C2 are cross-sectional views each illustrating a structure example of a transistor.
FIGS. 19A1-19C2 are cross-sectional views each illustrating a structure example of a transistor.
Embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following description, and it will be readily appreciated by those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Thus, the present invention should not be construed as being limited to the description in the following embodiments.
Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and explanation thereof is omitted. Furthermore, the same hatching pattern is applied to portions having similar functions, and the portions are not especially denoted by reference numerals in some cases.
Note that in each drawing described in this specification, the size, the layer thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, they are not limited to the illustrated scale.
Note that in this specification, a high power supply voltage and a low power supply voltage are sometimes referred to as an H level (or VDD) and an L level (or GND), respectively.
In this specification, the embodiments described below can be combined as appropriate. In the case where a plurality of structure examples are described in one embodiment, the structure examples can be combined as appropriate.
In this specification and the like, a metal oxide is an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor, and the like. For example, in the case where a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is referred to as an oxide semiconductor in some cases. In the case where an OS transistor is mentioned, the OS transistor can also be referred to as a transistor including a metal oxide or an oxide semiconductor. In this specification and the like, a metal oxide containing nitrogen is also referred to as a metal oxide in some cases.
The case where the display element is a liquid crystal element is described below. For example, a liquid crystal element has a response characteristic called the gamma value. The gamma value is a numerical value representing a response characteristic of a gray level with respect to a voltage supplied to a liquid crystal element, and it is known that different response characteristics are exhibited depending on a low gray level range, a middle gray level range, and a high gray level range. As a method for correcting the above different response characteristics, there is a correction method in which a gamma correction coefficient for converting the transmittance of a liquid crystal element into a linear characteristic is multiplied. Another method is known in which the response characteristics of a liquid crystal element are controlled as they are by finely controlling a voltage supplied to the liquid crystal element and corresponding to one gray level. Note that in order to finely control a voltage supplied to a liquid crystal element, the resolution of a digital-analog converter circuit included in a display device needs to be increased. In addition, in the low gray level range or the high gray level range, the amount of change in transmittance with respect to the voltage is small. Accordingly, in order to further finely control the transmittance in the low gray level range or the high gray level range, the resolution of a potential supplied to a liquid crystal element is increased or the maximum potential supplied to a liquid crystal element is increased, whereby the transmittance in the low gray level range or the high gray level range can be improved.
First, a semiconductor device is briefly described. Detailed description will be made with reference to
In
As an example, display data in the range of a digital input code “0” to a digital input code “2n” is supplied to the source driver as digital data. The digital input code “0” is converted into a data potential VL1 by a digital-analog converter circuit, and the digital input code “2n” is converted into a data potential VH1 by the digital-analog converter circuit. That is, a source driver output range Data1 is from the data potential VL1 to the data potential VH1. Note that it is preferable that n be a positive integer that is greater than or equal to 1 and 1 less than a power of 2.
In the liquid crystal element shown in
The transmittance of a liquid crystal element changes depending on a potential difference supplied to both ends of the liquid crystal element. Thus, as the data potential Data1a, a voltage lower than or equal to the data potential VH1 is supplied using the potential VCOM as a reference potential. As the data potential Data1b, a voltage higher than or equal to the data potential VL1 is supplied using the potential VCOM as a reference potential. For example, the data potential Data1a is displayed using the digital input code “n” to the digital input code “2n”, and the data potential Data1b is displayed using the digital input code “0” to a digital input code “n”. As an example, the digital input code “n” exhibits the same potential as the potential VCOM and the minimum gray level G0. Both of the data potential VL1 and the data potential VH1 can exhibit the gray level G1. That is, the gray level that can be displayed in the case where the data potential Data1b or the data potential Data1a is the source driver output range Data1 is in the range of the minimum gray level G0 to the gray level G1.
Furthermore, a data potential Data2a or a data potential Data2b is preferably supplied to the pixel. When the pixel performs calculation with a plurality of supplied data potentials, a data potential supplied to the liquid crystal element can be increased. As an example, the voltage range of the supplied data potential Data2a or data potential Data2b is preferably the same scale as the source driver output range Data1.
As an example, the data potential Data1a is subjected to calculation with the data potential Data2a, whereby the display element can display the maximum gray level G2. As another example, in the case where inversion is performed centering around the potential VCOM, the data potential Data1b is subjected to calculation with the data potential Data2b, whereby display at the maximum gray level G2 can be performed. Note that the calculation in the pixel is not limited to addition and subtraction can be performed. Furthermore, in the calculation, the data potential Data2a or the data potential Data2b can be multiplied by a coefficient.
Thus, the liquid crystal element can display up to “n” gray levels owing to the data potential Data1a or the data potential Data1b. Furthermore, the pixel performs calculation with the data potential Data2a or the data potential Data2b, whereby the range of the gray levels that can be displayed is expanded to the gray level corresponding to a digital input code “3n”. In other words, by calculation with a plurality of supplied data potentials, the pixel can display the gray level range that is wider than the gray level range that can be displayed in the source driver output range.
The power consumption of the source driver can be reduced when the source driver output range is reduced. When the source driver output range corresponds to a region with a small amount of transmittance change with respect to the voltage of the liquid crystal element, display at a gray level with a small amount of transmittance change can be finely controlled. Furthermore, in the case where the display mode of the liquid crystal element is normally white, the data potential Data2a or the data potential Data2b to be subjected to calculation is supplied to the pixel, so that the liquid crystal element can be supplied with a potential high enough to control the high gray level range. Thus, the contrast of an image displayed on the display device can be improved.
In
A data potential Data3a represents a data potential generated by calculation with the data potential Data1a and the data potential Data2a, and a data potential Data3b represents a data potential generated by calculation with the data potential Data1b and the data potential Data2b. Note that
First, an example is described in which the source driver supplies, to the pixel, the data potential Data1a and the data potential Data2a that represent positive gray levels.
The source driver supplies, to the pixel, any one of the display data in the range of the digital input code “n” corresponding to the potential VCOM to the digital input code “2n” corresponding to the data potential VH1. The display data is converted into the data potential Data1a by the digital-analog converter circuit to be supplied to the pixel.
Then, the source driver supplies, to the pixel, any one of the display data in the range of the digital input code “0” corresponding to the data potential VL1 to the digital input code “2n” corresponding to the data potential VH1. The display data is converted into the data potential Data2a by the digital-analog converter circuit to be supplied to the pixel. Note that in order to distinguish the first data writing from the second data writing to the pixel, the voltage range of the second data writing is from a data potential VL2 to a data potential VH2. Thus, the pixel performs calculation with the data potential Data1a and the data potential Data2a to generate the data potential Data3a, which is supplied to the liquid crystal element.
Next, how the source driver supplies, to the pixel, the data potential Data1b and the data potential Data2b that represent negative gray levels is described.
The source driver supplies, to the pixel, any one of the display data in the range of the digital input code “n” corresponding to the potential VCOM to the digital input code “0” corresponding to the data potential VL1. The display data is converted into the data potential Data1b by the digital-analog converter circuit to be supplied to the pixel.
Then, the source driver supplies, to the pixel, any one of the display data in the range of the digital input code “0” corresponding to the data potential VH2 to a digital input code “−2n” corresponding to the data potential VL2. The display data is converted into the data potential Data2b by the digital-analog converter circuit to be supplied to the pixel. Note that in order to distinguish the first data writing from the second data writing to the pixel, the voltage range of the second data writing is from the data potential VL2 to the data potential VH2. Thus, the pixel performs calculation with the data potential Data1b and the data potential Data2b to generate the data potential Data3b, which is supplied to the liquid crystal element.
In this embodiment, writing of the display data to the pixel is performed twice, whereby display data exceeding the source driver output range can be supplied to the display element. Note that the number of times the display data is supplied to the pixel is not limited to two. The display data may be supplied to the pixel a plurality of times. For example, one of the display data supplied to the pixel a plurality of times may function as a correction table of the temperature at which the display device is used. For example, in the case where the display element is a liquid crystal element, when the display device is used in a low-temperature environment, a larger potential supplied to the liquid crystal element enables the display element to be driven more smoothly.
The source driver 24 includes a buffer circuit 24a, a digital-analog converter circuit 24b, a level shifter circuit 24c, a latch circuit 24d, a switch control circuit 24e, a switch S1, a switch S2, a switch S3, and a switch S4. The digital-analog converter circuit 24b includes a wiring 24f, a wiring 24g, resistors R1 to Rn, a first output terminal, a second output terminal, and a third output terminal. Note that n is a positive integer.
The gate driver 25 includes a plurality of shift register circuits 25a, a plurality of shift register circuits 25b, a plurality of buffer circuits 25c, and a plurality of buffer circuits 25d. Note that for simplification of description,
The display device 26 includes a plurality of pixels 26a, a plurality of wirings GL1, a plurality of wirings GL2, a plurality of wirings SL1, a plurality of wirings SL2, and a wiring COM. Each of the plurality of pixels 26a includes a transistor M1, a transistor M2, a capacitor C1, a capacitor C2, and a display element LC. Note that for simple description of the display device 26,
First, electrical connections in the pixel 26a are described. A gate of the transistor M1 is electrically connected to the wiring GL1. One of a source and a drain of the transistor M1 is electrically connected to the wiring SL1. The other of the source and the drain of the transistor M1 is electrically connected to one electrode of the capacitor C1, one electrode of the capacitor C2, and one electrode of the liquid crystal element LC. A gate of the transistor M2 is electrically connected to the wiring GL2. One of a source and a drain of the transistor M2 is electrically connected to the wiring SL2. The other of the source and the drain of the transistor M1 is electrically connected to the other electrode of the capacitor C2. The wiring COM is electrically connected to the other electrode of the capacitor C1 and the other electrode of the liquid crystal element LC. A node ND1 is formed by the connection of the other of the source and the drain of the transistor M1, the one electrode of the capacitor C1, the one electrode of the capacitor C2, and the one electrode of the liquid crystal element LC. A node ND2 is formed by the connection of the other of the source and the drain of the transistor M2 and the other electrode of the capacitor C2.
Next, electrical connections in the source driver 24 are described. A data bus DData is electrically connected to the level shifter circuit 24c through the latch circuit 24d. The level shifter circuit 24c is electrically connected to the digital-analog converter circuit 24b. In the digital-analog converter circuit 24b, the first output terminal is electrically connected to an input terminal of the buffer circuit 24a, the second output terminal is electrically connected to one electrode of the switch S1, and the third output terminal is electrically connected to one electrode of the switch S2. An output terminal of the buffer circuit 24a is electrically connected to one electrode of the switch S3 and one electrode of the switch S4. The wiring SL1 is electrically connected to the other electrode of the switch S4. The wiring SL2 is electrically connected to the other electrode of the switch S1, the other electrode of the switch S2, and the other electrode of the switch S3. The switch control circuit 24e is electrically connected to the switch S1, the switch S2, the switch S3, and the switch S4.
Next, electrical connections in the gate driver 25 are described. The shift register circuit 25a is electrically connected to the buffer circuit 25c and the switch control circuit 24e. The shift register circuit 25b is electrically connected to the buffer circuit 25d. The buffer circuit 25c is electrically connected to the wiring GL1. The buffer circuit 25d is electrically connected to the wiring GL2.
A plurality of wirings CTL are electrically connected to the gate driver 25 and the switch control circuit 24e. A clock signal, a start pulse signal, a pulse width control signal, and the like are supplied to the wirings CTL. The wirings CTL are described in detail with reference to
Next, the operation of the gate driver 25 is described. The shift register circuit 25a can supply a first scan signal to the wiring GL1 of the display device 26 through the buffer circuit 25c. The shift register circuit 25b can supply a second scan signal to the wiring GL2 of the display device 26 through the buffer circuit 25d. Although not illustrated, the first scan signal or the second scan signal is also supplied to the switch control circuit 24e as a data write signal to the pixel 26a.
Next, the operation of the source driver 24 is described. The latch circuit 24d is supplied with the display data as digital data through the data bus DData. The display data is supplied to the digital-analog converter circuit 24b through the level shifter circuit 24c. Note that the digital-analog converter circuit 24b may have a function of the level shifter circuit 24c.
The digital-analog converter circuit 24b can convert supplied display data into a data potential. In this case, the data potential preferably has linearity with respect to the display data. For example, when a plurality of resistors are connected in series between the wiring 24g supplied with a data potential VL and the wiring 24f supplied with a data potential VH as shown in
The switch control circuit 24e can control turning on or off of the switch S1 to the switch S4 independently. The switch control circuit 24e is supplied with data write signals to the pixel 26a from the shift register circuit 25a and the shift register circuit 25b included in the gate driver 25. Thus, the switch control circuit 24e can control turning on or off of the switch S1 to the switch S4 in accordance with the timing of data writing to the pixel 26a. Thus, the switch control circuit 24e can control the timing of supplying the data potential to the pixel 26a. For example, a data write signal to the pixel 26a can be generated from a clock signal, a start pulse signal, a pulse width control signal, or the like supplied to the wiring CTL and can delay the timing for a predetermined period of time.
The operations of the pixel 26a and the switch control circuit 24e are described in detail with reference to timing charts in
First, with reference to
At Time T1, the first scan signal is supplied to the wiring GL1, and the second scan signal is supplied to the wiring GL2. The first scan signal and the second scan signal are supplied to the switch control circuit 24e. In the case where the switch S1 and the switch S4 are turned off by the switch control circuit 24e, the wiring SL1 or the wiring SL2 is brought into a floating state in some cases. A period indicated by a dashed arrow in
The transistor M1 is brought into an on state by the state of the first scan signal. The node ND1 is supplied with the data potential Data1a through the wiring SL1. The transistor M2 is brought into an on state by the second scan signal. The node ND2 is supplied with a second data potential through the wiring SL2. The data potential VL corresponding to the first data potential is supplied to the node ND1 using the potential VCOM supplied to the wiring COM as a reference potential. In addition, the data potential Data1a that uses the data potential VL supplied to the node ND1 as a reference potential is supplied to the node ND2.
Note that at Time T1, it is preferable that the switch control circuit 24e control the switch S1 to be in an on state, the switch S2 to be in an off state, the switch S3 to be in an off state, and the switch S4 to be in an on state. In addition, it is preferable that the switch control circuit 24e control the switch S1 to the switch S4 later than input of the first scan signal or the second scan signal. In other words, a delay period (Delay) of output timing of a data potential supplied to the wiring SL1 or the wiring SL2 is controlled in accordance with the timing of turning on or off the transistor M1 or the transistor M2, whereby correct data can be written independently of the characteristics variation and the like of the transistor M1 or the transistor M2. Although there is a period in which data of the node ND1 or the node ND2 is undetermined until the data potential is supplied to the wiring SL1 or the wiring SL2, it does not matter. This is because the data of the node ND1 or the node ND2 should be determined by Time T2. Furthermore, in controlling delay, the delay period is preferably changed in accordance with the temperature.
At time T2, the transistor M1 is brought into an off state by the state of the first scan signal, and the transistor M2 is kept in an on state by the state of the second scan signal. The switch control circuit 24e controls the switch S1 to be in an off state, the switch S2 to be in an off state, the switch S3 to be in an on state, and the switch S4 to be in an off state. The node ND1 is brought into a floating state in which the data potential Data1a is held. The second data potential is supplied to the node ND2 through the wiring SL2. In this case, the data potential Data2a that uses the data potential VL as a reference potential is supplied as the second data potential. In accordance with charge conservation of a capacitor, the data potential Data1a held in the node ND1 is subjected to calculation with the data potential Data2a through the capacitor C2, and the data potential Data3a is generated. The data potential Data3 is calculated by the following Formula 1. Hereinafter, a transistor being brought into an off state means that a signal supplied to a gate of the transistor is changed to “L”, and a transistor being brought into an on state means that a signal supplied to a gate of the transistor is changed to “H”.
Data3=Data1+(C2/(C1+C2))×Data2 (Formula 1)
Note that the capacitance values of the capacitor C1 and the capacitor C2 are preferably the same. Alternatively, when the capacitor C2 has a capacitance value different from that of the capacitor C1, the capacitor C2 can be multiplied by a coefficient in the calculation. For a specified delay period from Time T2, the wiring SL1 preferably holds the supplied data potential. With the delay period, data writing to the node ND1 is surely performed.
At Time T3, the transistor M2 is brought into an off state by the state of the second scan signal, and the transistor M1 is kept in an off state by the state of the first scan signal. When the transistor M2 is brought into an off state, the node ND2 is brought into a floating state. For a specified period from Time T3, the wiring SL2 preferably holds the supplied data potential. With the delay period, data writing to the node ND2 is surely performed. Thus, the potential of the data potential Data2a is held in the node ND2, and the data potential Data3a is held in the node ND1. Accordingly, the data potential Data3a using the potential VCOM as a reference potential is supplied to the liquid crystal element LC.
With reference to
At Time T1, the first scan signal is supplied to the wiring GL1, and the second scan signal is supplied to the wiring GL2. The first scan signal and the second scan signal are supplied to the switch control circuit 24e.
The transistor M1 is brought into an on state by the state of the first scan signal. The node ND1 is supplied with the data potential Data1b through the wiring SL1. The transistor M2 is brought into an on state by the state of the second scan signal. The node ND2 is supplied with the second data potential through the wiring SL2. The data potential VH corresponding to the second data potential is supplied to the node ND1 using the potential VCOM supplied to the wiring COM as a reference potential. In addition, the data potential Data1b using the data potential VH supplied to the node ND1 as a reference potential is supplied to the node ND2.
Note that at Time T1, it is preferable that the switch control circuit 24e control the switch S1 to be in an off state, the switch S2 to be in an on state, the switch S3 to be in an off state, and the switch S4 to be in an on state. In addition, it is preferable that the switch control circuit 24e control the switch S1 to the switch S4 later than input of the first scan signal or the second scan signal.
At time T2, the transistor M1 is brought into an off state by the state of the first scan signal, and the transistor M2 is kept in an on state by the state of the second scan signal. The switch control circuit 24e controls the switch S1 to be in an off state, the switch S2 to be in an off state, the switch S3 to be in an on state, and the switch S4 to be in an off state. The node ND1 is brought into a floating state in which the data potential Data1b is held. The second data potential is supplied to the node ND2 through the wiring SL2. In this case, the data potential Data2b that uses the data potential VH as a reference potential is supplied as the second data potential. In accordance with charge conservation of a capacitor, the data potential Data1b held in the node ND1 is subjected to calculation with the data potential Data2b through the capacitor C2, and the data potential Data3b is generated.
At Time T3, the transistor M1 is kept in an off state by the state of the first scan signal, and the transistor M2 is brought into an off state by the state of the second scan signal. When the transistor M2 is brought into an off state, the node ND2 is brought into a floating state. Thus, the potential of the data potential Data2b is held in the node ND2, and the data potential Data3b is held in the node ND1. Accordingly, the data potential Data3b using the potential VCOM as a reference potential is supplied to the liquid crystal element LC.
Thus, in
For example, in the case where display with a positive gray level is performed with the source driver output range Data1, the digital input code “0” is converted into the data potential VCOM by the digital-analog converter circuit, and the digital input code “n” is converted into the data potential VH1 by the digital-analog converter circuit.
Furthermore, the data potential Data2a is preferably supplied to the pixel. The data potential Data2a is converted in the voltage range of the data potential VCOM to the data potential VH2. When the pixel performs calculation with a plurality of supplied data potentials, a data potential supplied to the liquid crystal element can be increased. The voltage range of the supplied data potential Data2a is preferably the same scale as the source driver output range Data1. Thus, the maximum gray level G2 the display device 26 can display corresponds to the digital input code “2n” at the maximum. Note that the written expression data potential VH1 or data potential VH2 is for distinguishing first wiring from second writing, and the source driver output range is the same.
In the case where display with a negative gray level is performed with the source driver output range Data1, the digital input code “0” is converted into the data potential VH1 by the digital-analog converter circuit, and the digital input code “−n” is converted into the data potential VCOM by the digital-analog converter circuit. That is, in the first data writing, the data potential VH1 is supplied as a reference potential.
Furthermore, the data potential Data2b is preferably supplied to the pixel. When the pixel performs calculation with a plurality of supplied data potentials, a data potential supplied to the liquid crystal element can be increased. The voltage range of the supplied data potential Data2b is preferably the same scale as the source driver output range Data1. The data potential Data2b is supplied using the data potential VH2 as a reference potential. Thus, a maximum gray level G2a the display device 26 can display corresponds to the digital input code “−2n” at the maximum.
As illustrated in
Thus, the liquid crystal element can display up to a gray level corresponding to the digital input code “n” owing to the data potential Data1. Furthermore, the pixel performs calculation with the data potential Data2a or the data potential Data2b, whereby the range of the gray levels that can be displayed is expanded to the gray level corresponding to the digital input code “2n”. In other words, by calculation with a plurality of supplied data potentials, the pixel can display the gray level range that is wider than the gray level range that can be displayed in the source driver output range.
The power consumption of the source driver can be reduced when driving is performed by inverting the potential VCOM supplied to the liquid crystal element and the source driver output range is reduced. When the source driver output range corresponds to a region with a small amount of transmittance change with respect to the voltage of the liquid crystal element, display at a gray level with a small amount of transmittance change can be finely controlled. Furthermore, the data potential Data2a or the data potential Data2b to be subjected to calculation is supplied to the pixel, so that the liquid crystal element can be supplied with a potential high enough to control the high gray level range. Thus, the contrast of an image displayed on the display device can be improved.
Note that the number of times the display data is supplied to the pixel is not limited to two. The display data may be supplied to the pixel a plurality of times. For example, one of the display data supplied to the pixel a plurality of times may function as a correction table of the temperature at which the display device is used. When the display device is used in a low-temperature environment, a larger potential supplied to the liquid crystal element enables the display element to be driven more smoothly.
The inversion control circuit 25e is electrically connected to the wiring TCOM, the shift register circuit 25a, and the shift register circuit 25b. The inversion control circuit 25e is supplied with the first scan signal or the second scan signal from the shift register circuit 25a or the shift register circuit 25b. The inversion control circuit 25e generates, from the supplied scan signal, an inversion signal that is supplied to the wiring TCOM. That is, the inversion control circuit 25e can invert the potential VCOM in the liquid crystal element. The inversion signal supplied to the wiring TCOM may be supplied from a processor, a display controller, or the like, for example.
Note that degradation of a liquid crystal material or display unevenness such as flicker can be suppressed when the polarity of the data voltage applied with respect to the potential VCOM in the liquid crystal element is inverted at regular intervals and driving is performed. As an example of the inversion driving, source line inversion driving, gate line inversion driving, dot inversion driving, and the like as well as frame inversion driving can be given.
Frame inversion driving is a driving method in which the polarity of a voltage applied to a liquid crystal element is inverted every one frame period. Note that one frame period corresponds to a period for displaying an image for one pixel. Although there is no particular limitation on the length of the period, it is preferable that the one frame period be at least less than or equal to 1/60 seconds so that a person viewing an image does not perceive a flicker.
It is desirable that the period is further shortened and the frequency is increased to reduce motion blur. It is desirable that the period is 1/120 seconds or shorter (the frequency is 120 Hz or higher). It is more desirable that the period is 1/180 seconds or shorter (the frequency is 180 Hz or higher). In the case where the frame frequency is increased in this manner, when the increased frame frequency does not match the frame frequency of the original image data, image data needs to be interpolated. In this case, image data is interpolated by using a motion vector, so that display at a high frame frequency can be achieved. In this manner, the motion of the image is smoothly displayed and display with few afterimages can be performed.
Note that in this specification, display devices including liquid crystal elements as display elements are classified into a direct-view type, a projection type, and the like depending on a method for displaying an image. Moreover, liquid crystal display devices can be classified into a transmissive type, a reflective type, and a transflective type according to whether a pixel transmits or reflects illumination light. As an example of the liquid crystal element, an element that controls the transmission or non-transmission of light utilizing an optical modulation action of a liquid crystal is given. The element can include a pair of electrodes and a liquid crystal layer. Note that the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). Examples of a liquid crystal used for the liquid crystal element are a nematic liquid crystal, a cholesteric liquid crystal, a smectic liquid crystal, a discotic liquid crystal, a thermotropic liquid crystal, a lyotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a polymer dispersed liquid crystal (PDLC), a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, a main-chain liquid crystal, a side-chain high-molecular liquid crystal, and a banana-shaped liquid crystal.
Examples of a display method of the liquid crystal display device are a TN (Twisted Nematic) mode, an STN (Super Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Birefringence) mode, an ECB (Electrically Controlled Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, a guest-host mode, and a blue phase mode.
A pixel 26b illustrated in
A pixel 26c illustrated in
In this embodiment, a structure example of a semiconductor device in which the influence of temperature change is suppressed is described with reference to
The frame memory 23 includes, for example, the memory device 23a and the memory device 23b, and thus can be used for comparison processing for determining whether display data corresponds to a still image or a moving image; filtering processing for improving image quality; image data synthesizing processing for overlapping an image, text information, and the like to each other; image data synthesizing processing for overlapping different images to each other; or the like. Note that image data is preferably supplied to the frame memory 23 from the CPU 27 or the like.
The CPU 27 can collect temperature information such as environmental temperature at which the display device 26, a component such as the frame memory 23, or the display device 20 is used from the temperature sensor 19 or the like and supply it to the semiconductor device 10.
A memory circuit such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) may be used for the memory device 23a and the memory device 23b. Note that a transistor with a low off-state current is used for the memory circuit, whereby a still image and the like can be held for a long period. As the memory device including a transistor with a low off-state current, a DOSRAM (registered trademark) “Dynamic Oxide Semiconductor RAM”, a NOSRAM (registered trademark) “Nonvolatile Oxide Semiconductor RAM”, and the like can be given.
In the display device 20 illustrated in
For example, in the case where the semiconductor device 100a is used in a high-temperature environment, the off-state current of the transistor might be increased. Accordingly, when the back gate of the transistor included in the gate driver 25 is controlled, a change in threshold voltage of the transistor can be controlled. That is, even in the case of the use in a high-temperature environment, an increase in the off-state current of the transistor included in the gate driver 25 can be suppressed. In addition, the threshold voltage of the transistor might vary due to characteristic variation, voltage stress, or the like. With the semiconductor device 10, the influence of the transistor variation, variation in threshold voltage, or the like can be reduced. Thus, an increase in the power consumption of the semiconductor device 100a can be suppressed.
The transistor included in the voltage reference circuit 12 is characterized by including a metal oxide in a semiconductor layer, like the transistors included in the display device 26 and the gate driver 25. Thus, the voltage reference circuit 12 functions as a sensor for the semiconductor device 10. Therefore, in accordance with the usage environment of an electronic device including the semiconductor device 100b, or the like, a feedback loop that controls the threshold voltage of the transistors included in the semiconductor device 100b can be formed.
<<Semiconductor Device 10>>
The semiconductor device 10 illustrated in
The band gap reference circuit 11 includes an output terminal 11a, an output terminal 11b, and an output terminal 11c. A first current is output to the output terminal 11a, a first potential is output to the output terminal 11b, and a second potential is output to the output terminal 11c.
The voltage reference circuit 12 includes an input terminal 12a, an input terminal 12c, an input terminal 12d, and an output terminal 12b. The voltage reference circuit 12 includes a first transistor including a metal oxide in a semiconductor layer. The first transistor is described in detail with reference to
The selection circuit 13 includes an input terminal 13a, an input terminal 13b, an input terminal 13d, and an output terminal 13c. The input terminal 13a is electrically connected to the output terminal 11b, and the input terminal 13b is electrically connected to the output terminal 11c. The operation mode control circuit 17 is electrically connected to the input terminal 13d. Thus, the selection circuit 13 outputs, to the output terminal 13c, either the first potential supplied to the input terminal 13a or the second potential supplied to the input terminal 13b, in accordance with a temperature sensed by the operation mode control circuit 17. Note that the temperature selection conditions may be managed more finely and the selection circuit 13 may output a different potential depending on the temperature. Note that the operation mode control circuit 17 may include a temperature sensor for sensing the temperature. Alternatively, a structure may be employed in which a temperature sensor is connected to the operation mode control circuit 17 or a structure may be employed in which temperature information is supplied from a CPU or the like.
The difference detection circuit 14 detects and outputs a voltage difference between the threshold voltage of the first transistor and the output voltage of the selection circuit 13 as a difference voltage. The difference detection circuit 14 can perform detection easily by using an amplifier. Note that the difference detection circuit 14 may be composed of an analog-digital converter circuit.
The voltage controlled oscillator 15 can convert the input difference voltage into a frequency. The voltage controlled oscillator 15 preferably converts the voltage into a frequency by using a VCO circuit (Voltage Controlled Oscillator) or the like. Accordingly, the level of the output frequency of the voltage controlled oscillator 15 is controlled in accordance with the voltage level.
The negative voltage generation circuit 16 includes an input terminal 16a, an output terminal 16b, a level shifter circuit 16c, and a charge pump circuit 16d. As an input frequency, the output frequency is supplied to the level shifter circuit 16c through the input terminal 16a. The level shifter circuit 16c can adjust the amplitude voltage of an input frequency supplied to the charge pump circuit 16d. The level shifter circuit 16c can generate a positive-phase signal and an inverted signal which are to be supplied to the charge pump circuit 16d. The charge pump circuit 16d can generate a negative voltage in accordance with the supplied input frequency.
The negative voltage generated by the charge pump circuit 16d can be supplied to the input terminal 12c of the voltage reference circuit 12. Thus, the voltage supplied to the back gate of the first transistor by the voltage reference circuit 12 can be controlled such that the threshold voltage of the first transistor converges to the same voltage as the output voltage of the selection circuit 13.
The amplifier 18 can convert a signal of the negative voltage generated by the charge pump circuit 16d into a low-impedance output signal and output it. An output of the amplifier 18 is supplied to the gate driver 25, the pixel 26a, or the like.
For example, in the case where a transistor including a metal oxide in a semiconductor layer is used for the gate driver, the pixel of the display device, or the like, the threshold voltage of the transistor can be controlled by a signal VBG which is output as a voltage to the back gate of the transistor by the semiconductor device 10. Therefore, even when the gate driver or the display device is used in an environment with a large temperature change, the threshold voltage of the transistor is adjusted to be the threshold voltage selected by the operation mode control circuit 17 by the signal VBG supplied to the back gate of the transistor. Thus, the off-state current of the transistor is kept low. Furthermore, data deterioration caused by the use of the memory device in a high-temperature environment and display defects in a pixel which are caused by the use of the display device in a high-temperature environment can be reduced. Furthermore, an increase in power consumption or standby power of the gate driver or the display device used in a high-temperature environment can be suppressed.
The reference voltage current generation circuit 11e includes an amplifier 30, transistors 31a to 31d, and resistors 32a to 32c. The transistors 31a to 31d are preferably p-channel transistors. The amplifier 30 preferably has a voltage follower connection. The output terminal of the band gap reference circuit 11d is electrically connected to a non-inverting input terminal of the amplifier 30. An output terminal of the amplifier 30 is electrically connected to an inverting input terminal.
The output terminal of the amplifier 30 is electrically connected to a gate of each of the transistors 31a to 31d. A source of each of the transistors 31a to 31d is connected to a wiring VDD1 so that a current mirror circuit is formed. A drain of the transistor 31a is electrically connected to the resistors 32a to 32c connected in series. A drain of the transistor 31b is electrically connected to the resistors 32b and 32c connected in series. A drain of the transistor 31c is electrically connected to the resistor 32c. Note that the current mirror circuit may be formed using n-channel transistors.
The transistors 31a to 31d preferably have the same channel length. Furthermore, when the transistors 31a to 31c have the same channel width, the amounts of current flowing through the transistors 31a to 31c can be the same. Thus, a given voltage can be easily generated by changing the resistance value.
As an example, a reference voltage can be generated when the transistor 31a allows current to flow through the resistors 32a to 32c connected in series. When the reference voltage is supplied to the inverting input terminal, the amplifier 30 functions as a voltage follower. As another example, the first potential can be generated when the transistor 31b allows current to flow through the resistors 32b and 32c connected in series. The first potential is output to the output terminal 11b. Furthermore, as another example, the second potential can be generated when the transistor 31c allows current to flow through the resistor 32c. The second potential is output to the output terminal 11c.
The reference voltage current generation circuit lle includes the transistor 31d that generates the first current. Note that the channel width of the transistor 31d may be the same as or different from those of the transistors 31a to 31c. The first current flowing through the transistor 31d is output to the output terminal 11a.
Thus, an example is shown in which the reference voltage current generation circuit 11e outputs a second voltage and a first voltage higher than the second voltage. As another example, the threshold voltage of the first transistor may be controlled more finely by increasing the number of stages of the current mirror and setting combinations of resistors more finely.
A drain and a gate of the transistor 33 are electrically connected to the input terminal 12a and the output terminal 12b. A source of the transistor 33 is electrically connected to a wiring GND. A back gate of the transistor 33 is electrically connected to one electrode of the resistor 34, one of a source and a drain of the transistor 35, a back gate of the transistor 35, and the input terminal 12c. The other electrode of the resistor 34 is electrically connected to the wiring VDD1. The other of the source and the drain of the transistor 35 is electrically connected to the wiring GND. Note that a potential supplied to the wiring GND is a low potential for operating the shift register circuit 25a and is not limited to 0 V.
The first current is supplied to the drain and the gate of the transistor 33 through the input terminal 12a. Thus, the threshold voltage of the transistor 33 is output to the output terminal 12b. It is known that the threshold voltage of the transistor 33 is shifted by a voltage supplied to the back gate of the transistor 33. Thus, when a negative voltage generated by the charge pump circuit 16d is supplied to the back gate of the transistor 33 through the input terminal 12c, a feedback loop with the transistor 33 as a center is formed. When a selection voltage selected in accordance with the temperature detected by the operation mode control circuit 17 is the same as the output voltage of the output terminal 12b of the voltage reference circuit 12, the feedback adjustment converges in the selection circuit 13 and the adjustment ends.
The transistor 35 can initialize the back gate potential of the transistor 33. The resistor 34 can generate the back gate potential of the transistor 33 using a voltage supplied to the wiring VDD1 as reference. A capacitor, a diode, or the like may be used instead of the resistor 34. The negative voltage generation circuit 16 described later is preferably capable of finely adjusting a negative voltage supplied to the back gate of the transistor 33, because the negative voltage is generated with the use of the charge pump circuit 16d. Consequently, when current flows through a resistor, the negative voltage supplied to the back gate of the transistor 33 can be finely adjusted.
The input frequency is supplied to the level shifter circuit 16c through the input terminal 16a. The level shifter 36a can generate a positive-phase signal supplied to the charge pump circuit 16d and the level shifter 36b can generate an inverted signal supplied to the charge pump circuit 16d.
The charge pump circuit 16d includes a transistor 37a, a transistor 37b, a capacitor 37c, a transistor 38a, a transistor 38b, a capacitor 38c, a transistor 39, an input terminal 16e, an input terminal 16f, the output terminal 16b, a wiring VDD2, and the wiring GND. Note that the transistor 37a, the transistor 37b, the transistor 38a, the transistor 38b, and the transistor 39 each preferably include a metal oxide in a semiconductor layer.
The input terminal 16e is electrically connected to a gate of the transistor 37a, a gate of the transistor 37b, and a gate of the transistor 39. The input terminal 16f is electrically connected to a gate of the transistor 38a and a gate of the transistor 38b. The wiring VDD2 is electrically connected to one of a source and a drain of the transistor 37a. The wiring GND is electrically connected to one of a source and a drain of the transistor 37b. The other of the source and the drain of the transistor 37a is electrically connected to one of a source and a drain of the transistor 38a and one electrode of the capacitor 37c. The other of the source and the drain of the transistor 37b is electrically connected to one of a source and a drain of the transistor 38b and the other electrode of the capacitor 37c. The other of the source and the drain of the transistor 38a is electrically connected to one of a source and a drain of the transistor 39 and one electrode of the capacitor 38c. The other of the source and the drain of the transistor 39 is electrically connected to the wiring GND. The other of the source and the drain of the transistor 38b is electrically connected to the output terminal 16b, the level shifter 36a, the level shifter 36b, the other electrode of the capacitor 38c, and a back gate of each of the transistor 37a, the transistor 37b, the transistor 38a, the transistor 38b, and the transistor 39.
A positive voltage is supplied to the wiring VDD2. A voltage lower than the positive voltage supplied to the wiring VDD2 is supplied to the wiring GND. Note that a reference potential of the circuit is preferably supplied to the wiring GND. Hereinafter, the case where 0 V that is a ground potential is supplied is described as an example. The voltage supplied to the wiring VDD2 is preferably lower than or equal to the voltage supplied to the wiring VDD1. Furthermore, the voltage supplied to the wiring VDD2 is preferably lower than the voltage supplied to the wiring VDD1.
An output of the level shifter 36a brings the transistor 37a, the transistor 37b, and the transistor 39 into an on state. In this case, an output of the level shifter 36b is in an inverted state of the output of the level shifter 36a, and thus the transistor 38a and the transistor 38b are brought into an off state. Thus, a positive voltage is supplied to the one electrode of the capacitor 37c from the wiring VDD2, and 0 V is supplied to the other electrode of the capacitor 37c from the wiring GND, for example. Thus, a voltage corresponding to a potential difference between the wiring VDD2 and 0V is held in the capacitor 37c.
Next, the output of the level shifter 36a is inverted, and the transistor 37a, the transistor 37b, and the transistor 39 are brought into an off state. In this case, the output of the level shifter 36b is in an inverted state of the output of the level shifter 36a, and the transistor 38a and the transistor 38b are brought into an on state. Thus, the capacitor 37c and the capacitor 38c form a combined capacitor, and the voltage held in the capacitor 37c becomes a smoothed potential. In this case, a node formed by the other electrode of the capacitor 37c and the other electrode of the capacitor 38c through the transistor 38b is a floating node, and thus a potential of the floating node is a reference potential of the smoothed potential.
Next, the output of the level shifter 36a brings the transistor 37a, the transistor 37b, and the transistor 39 into an on state. In this case, the output of the level shifter 36b is in an inverted state of the output of the level shifter 36a, and the transistor 38a and the transistor 38b are brought into an off state.
Here, the capacitor 38c is focused on and described. The smoothed potential is held in the capacitor 38c. Then, in the case where the potential of the one electrode of the capacitor 38c is changed to 0 V supplied to the wiring GND, the potential of the one electrode of the capacitor 38c becomes a reference potential, and the smoothed potential is generated as a negative voltage in the other electrode of the capacitor 38c.
The generated negative voltage is supplied to the output terminal 16b, and further supplied to the back gate of each of the transistor 37a, the transistor 37b, the transistor 38a, the transistor 38b, and the transistor 39. Furthermore, the generated negative voltage is supplied as negative power supply of the level shifter 36a and the level shifter 36b.
As described above, by using the semiconductor device 10 described in this embodiment, a semiconductor device can be provided in which the threshold voltages of transistors are controlled by a feedback loop in accordance with the usage environment of a gate driver, a display device, an electronic device, or the like, and data can be held without being influenced by temperature change. Furthermore, an increase in power consumption can be suppressed.
<<Gate driver 25>>
With the gate driver 25 illustrated in
The input terminal IN1 of the shift register circuit 25a(1) is electrically connected to a wiring LIN to which a start pulse SP1 is supplied through the wiring SP. The input terminal IN2 of the shift register circuit 25a(1) is electrically connected to the wiring CK6 supplied with a sixth clock signal. The input terminal IN3 of the shift register circuit 25a(1) is electrically connected to the wiring CK7 supplied with a seventh clock signal. The input terminal IN4 of the shift register circuit 25a(1) is electrically connected to a wiring RIN supplied with a return signal. The input terminal IN5 of the shift register circuit 25a(1) is electrically connected to the wiring INIRES supplied with an initialization signal.
The output terminal OP1 is supplied with a selection signal SET and is electrically connected to the input terminal INS of the buffer circuit 25c(1). The output terminal OP2 is supplied with a non-selection signal RESET and is electrically connected to the input terminal INR of the buffer circuit 25c(1). The wiring CK1 to the wiring CK5 are electrically connected to the input terminal INC(a) to the input terminal INC(e), respectively. The wiring BGL is electrically connected to the shift register circuit 25a(1) and the buffer circuit 25c(1).
Next, a structure example of the shift register circuit 25a is described with reference to a circuit diagram in
The input terminal IN1 is electrically connected to a gate of the transistor M3, a gate of the transistor M9, and a gate of the transistor M10. The input terminal IN2 is electrically connected to a gate of the transistor M6. The input terminal IN3 is electrically connected to a gate of the transistor M7. The input terminal IN4 is electrically connected to a gate of the transistor M8. The input terminal INS is electrically connected to a gate of the transistor M11.
The output terminal OP1 is electrically connected to one of a source and a drain of the transistor M3 and one of a source and a drain of the transistor M4. The output terminal OP2 is electrically connected to a gate of the transistor M4, a gate of the transistor M5, one of a source and a drain of the transistor M7, one of a source and a drain of the transistor M8, one of a source and a drain of the transistor M11, and one electrode of the capacitor C3.
The wiring VDD is electrically connected to the other of the source and the drain of the transistor M3, one of a source and a drain of the transistor M6, the other of the source and the drain of the transistor M8, and the other of the source and the drain of the transistor M11. The wiring GND is electrically connected to one of a source and a drain of the transistor M5, one of a source and a drain of the transistor M10, and the other electrode of the capacitor C3.
The other of the source and the drain of the transistor M4 is electrically connected to the other of the source and the drain of the transistor M5. The other of the source and the drain of the transistor M6 is electrically connected to the other of the source and the drain of the transistor M7. One of a source and a drain of the transistor M9 is electrically connected to the other of the source and the drain of the transistor M10.
Back gates of the transistor M3, the transistor M6, the transistor M7, the transistor M8, and the transistor M11 are electrically connected to respective gates. Back gates of the transistor M4, the transistor M5, the transistor M9, and the transistor M10 are electrically connected to the wiring BGL.
When a signal VBG supplied to the wiring BGL is supplied to the back gates of the transistor M4, the transistor M5, the transistor M9, and the transistor M10, an increase in off-state current can be suppressed.
Next, a structure example of the buffer circuit 25c(a) is described as an example with reference to a circuit diagram in
A gate of the transistor M12 is electrically connected to the wiring VDD. One of a source and a drain of the transistor M12 is electrically connected to the input terminal INS. The other of the source and the drain of the transistor M12 is electrically connected to a gate of the transistor M13 and one electrode of the capacitor C4. One of a source and a drain of the transistor M13 is electrically connected to the input terminal INC. The other of the source and the drain of the transistor M13 is electrically connected to the wiring GL1, one of a source and a drain of the transistor M14, and the other electrode of the capacitor C4. A gate of the transistor M14 is electrically connected to the wiring INR. The other of the source and the drain of the transistor M14 is electrically connected to the wiring BGL. The gates of the transistor M12, the transistor M13, and the transistor M14 are electrically connected to respective back gates.
In the case where the non-selection signal RESET is supplied to the wiring INR, the signal VBG supplied to the wiring BGL is supplied to the wiring GL1 through the transistor M14. Therefore, an increase in off-state current of the transistor M1 can be suppressed by the signal VBG. That is, deterioration of the display data of the pixel 26a is suppressed, which enables favorable display to be kept.
A structure example different from that in
In the case where the transistor M14 is in an off state, the back gate of the transistor M14 is controlled by the signal VBG, whereby an increase in off-state current of the transistor M14 can be suppressed. Therefore, an increase in power consumption of the buffer circuit 25c can be suppressed.
Note that
<<Pixel>>
Note that a display region may be divided into a plurality of display regions, and wirings of the divided display regions may be connected to different wirings BGL. The output voltage VBG of the semiconductor device 10 is supplied to the wiring BGL. When the output voltage VBG is supplied to the wiring BGL, the influence such as characteristics variation or a shift in the threshold voltage of a transistor due to voltage stress or the like can be reduced. Moreover, when the output voltage VBG and a scan signal supplied for bringing the transistor M1 and the transistor M2 into an off state are supplied to the transistor M1 and the transistor M2, the off-state current of the transistor M1 and the transistor M2 can be suppressed from increasing.
In the structure of the pixel circuit of
Examples of transistors which can be used instead of the transistors described in the above are described with reference to drawings.
The display device 26 can be fabricated using a transistor with any of various structures, such as a bottom-gate transistor or a top-gate transistor. Therefore, a material for a semiconductor layer or the transistor structure can be easily changed depending on the existing production line.
<<Bottom-Gate Tansistor>>
The transistor 810 includes an insulating layer 855 over a channel formation region in the semiconductor layer 856. The transistor 810 also includes an electrode 857a and an electrode 857b which are over the insulating layer 852 and partly in contact with the semiconductor layer 856. The electrode 857a can function as one of a source electrode and a drain electrode. The electrode 857b can function as the other of the source electrode and the drain electrode. Part of the electrode 857a and part of the electrode 857b are formed over the insulating layer 855.
The insulating layer 855 can function as a channel protective layer. With the insulating layer 855 provided over the channel formation region, the semiconductor layer 856 can be prevented from being exposed at the time of forming the electrode 857a and the electrode 857b. Thus, the channel formation region in the semiconductor layer 856 can be prevented from being etched at the time of forming the electrode 857a and the electrode 857b. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided.
The transistor 810 includes an insulating layer 853 over the electrode 857a, the electrode 857b, and the insulating layer 855 and also includes an insulating layer 854 over the insulating layer 853.
In the case where an oxide semiconductor is used for the semiconductor layer 856, a material capable of removing oxygen from part of the semiconductor layer 856 to generate oxygen vacancies is preferably used at least for portions of the electrode 857a and the electrode 857b which are in contact with the semiconductor layer 856. The carrier concentration in the regions of the semiconductor layer 856 where oxygen vacancies are generated is increased, so that the regions become n-type regions (also referred to as n+ regions in some cases). Accordingly, the regions can function as a source region and a drain region. When an oxide semiconductor is used for the semiconductor layer 856, examples of the material capable of removing oxygen from the semiconductor layer 856 to generate oxygen vacancies include tungsten and titanium.
Formation of the source region and the drain region in the semiconductor layer 856 makes it possible to reduce contact resistance between the semiconductor layer 856 and each of the electrode 857a and the electrode 857b. Accordingly, the electrical characteristics of the transistor, such as the field-effect mobility and the threshold voltage, can be improved.
In the case where a semiconductor such as silicon is used for the semiconductor layer 856, a layer that functions as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 856 and the electrode 857a and between the semiconductor layer 856 and the electrode 857b. The layer that functions as an n-type semiconductor or a p-type semiconductor can function as the source region or the drain region in the transistor.
The insulating layer 854 is preferably formed using a material that has a function of preventing or reducing diffusion of impurities into the transistor from the outside. Note that the insulating layer 854 can be omitted as necessary.
A transistor 811 shown in
In general, a back gate electrode is formed using a conductive layer and positioned such that a channel formation region in a semiconductor layer is positioned between a gate electrode and the back gate electrode. Thus, the back gate electrode can function in a manner similar to that of the gate electrode. The potential of the back gate electrode may be the same as the potential of the gate electrode or may be a ground potential (GND potential) or a given potential. When the potential of the back gate electrode is changed independently of the potential of the gate electrode, the threshold voltage of the transistor can be changed. For example, the output voltage of the semiconductor device 10 in
The electrode 858 and the electrode 850 can each function as a gate electrode. Thus, the insulating layer 852, the insulating layer 853, and the insulating layer 854 can each function as a gate insulating layer. The electrode 850 may be provided between the insulating layer 853 and the insulating layer 854.
In the case where one of the electrode 858 and the electrode 850 is referred to as a “gate electrode”, the other is referred to as a “back gate electrode”. For example, in the transistor 811, in the case where the electrode 850 is referred to as a “gate electrode”, the electrode 858 is referred to as a “back gate electrode”. In the case where the electrode 850 is used as a “gate electrode”, the transistor 811 can be regarded as a kind of top-gate transistor. One of the electrode 858 and the electrode 850 may be referred to as a “first gate electrode”, and the other may be referred to as a “second gate electrode”.
By providing the electrode 858 and the electrode 850 with the semiconductor layer 856 therebetween and setting the potentials of the electrode 858 and the electrode 850 to the same potential, a region of the semiconductor layer 856 through which carriers flow is enlarged in the film thickness direction; thus, the number of transferred carriers is increased. As a result, the on-state current of the transistor 811 is increased and the field-effect mobility is increased.
Therefore, the transistor 811 is a transistor having high on-state current for its occupation area. That is, the occupation area of the transistor 811 can be small for required on-state current. According to one embodiment of the present invention, the occupation area of a transistor can be reduced. Therefore, according to one embodiment of the present invention, a semiconductor device having a high degree of integration can be provided.
The gate electrode and the back gate electrode are formed using conductive layers and thus each have a function of preventing an electric field generated outside the transistor from affecting the semiconductor layer in which the channel is formed (in particular, an electric field blocking function against static electricity and the like). When the back gate electrode is formed larger than the semiconductor layer such that the semiconductor layer is covered with the back gate electrode, the electric field blocking function can be enhanced.
When the back gate electrode is formed using a light-blocking conductive film, light can be prevented from entering the semiconductor layer from the back gate electrode side. Therefore, photodegradation of the semiconductor layer can be prevented, and deterioration in electrical characteristics of the transistor, such as a shift of the threshold voltage, can be prevented.
According to one embodiment of the present invention, a transistor with favorable reliability can be provided. Moreover, a semiconductor device with favorable reliability can be provided.
A transistor 821 shown in
With the insulating layer 855, the semiconductor layer 856 can be prevented from being exposed at the time of forming the electrode 857a and the electrode 857b. Thus, the semiconductor layer 856 can be prevented from being reduced in thickness at the time of forming the electrode 857a and the electrode 857b.
The distance between the electrode 857a and the electrode 858 and the distance between the electrode 857b and the electrode 858 are longer in the transistor 820 and the transistor 821 than in the transistor 810 and the transistor 811. Thus, the parasitic capacitance generated between the electrode 857a and the electrode 858 can be reduced. Moreover, the parasitic capacitance generated between the electrode 857b and the electrode 858 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided.
A transistor 826 shown in
In each of the structures shown in
The length of each of the gate electrode and the back gate electrode in the channel width direction is longer than the length of the semiconductor layer 856 in the channel width direction. In the channel width direction, the whole of the semiconductor layer 856 is covered with the gate electrode and the back gate electrode with the insulating layers 852, 855, 853, and 854 positioned therebetween.
In this structure, the semiconductor layer 856 included in the transistor can be electrically surrounded by electric fields of the gate electrode and the back gate electrode.
The transistor device structure in which the semiconductor layer 856 in which the channel formation region is formed is electrically surrounded by electric fields of the gate electrode and the back gate electrode, as in the transistor 821 or the transistor 826, can be referred to as a Surrounded channel (S-channel) structure.
With the S-channel structure, an electric field for inducing a channel can be effectively applied to the semiconductor layer 856 by one or both of the gate electrode and the back gate electrode, which enables the transistor to have an improved current drive capability and high on-state current characteristics. In addition, the transistor can be miniaturized because the on-state current can be increased. The S-channel structure can also increase the mechanical strength of the transistor.
<<Top-Gate Transistor>>
A transistor 842 shown in
Part of the insulating layer 852 that does not overlap with the electrode 858 is removed, and an impurity is introduced into the semiconductor layer 856 using the electrode 858 and the remaining insulating layer 852 as masks, so that an impurity region can be formed in the semiconductor layer 856 in a self-aligned manner. The transistor 842 includes a region where the insulating layer 852 extends beyond end portions of the electrode 858. The semiconductor layer 856 in a region into which the impurity is introduced through the insulating layer 852 has a lower impurity concentration than the semiconductor layer 856 in a region into which the impurity is introduced not through the insulating layer 852. An LDD (Lightly Doped Drain) region is formed in the region of the semiconductor layer 856 that does not overlap with the electrode 858.
A transistor 843 shown in
As in a transistor 844 shown in
Also in the transistor 842 to the transistor 847, after the formation of the electrode 858, the impurity is introduced into the semiconductor layer 856 using the electrode 858 as a mask, so that an impurity region can be formed in the semiconductor layer 856 in a self-aligned manner. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device having a high degree of integration can be provided.
The transistor 843, the transistor 845, and the transistor 847 each have the above-described S-channel structure. However, one embodiment of the present invention is not limited to this, and the transistor 843, the transistor 845, and the transistor 847 do not necessarily have the S-channel structure.
Next, a resistor that can be used as the temperature sensor for detecting the temperature information supplied to the operation mode control circuit 17 in
The oxide semiconductor 401 has a property in that the resistivity changes with temperature. In the resistor 400, current is fed between the conductor 402 and the conductor 403 and the resistance of the oxide semiconductor 401 is measured, whereby a temperature can be detected.
The oxide semiconductor 401 used for the resistor 400 is formed using the same oxide semiconductor as that of the semiconductor layer 856 used for the transistor. The resistivity of the oxide semiconductor 401 is so high that the oxide semiconductor 401 cannot function satisfactorily as a resistor. Therefore, the oxide semiconductor 401 is preferably subjected to treatment for reducing the resistivity after the oxide semiconductor 401 is etched to have the shape shown in
An example of the above-described treatment for reducing the resistivity is plasma treatment with a rare gas such as He, Ar, Kr, or Xe. The plasma treatment may be performed using a mixed gas of the rare gas and nitrogen oxide, ammonium, nitrogen, or hydrogen. By the plasma treatment, an oxygen vacancy is formed in the oxide semiconductor 401, so that the resistivity thereof can be reduced.
Another example of the above-described treatment for reducing the resistivity is treatment in which a film containing much hydrogen such as silicon nitride is formed to be in contact with the oxide semiconductor 401. By adding hydrogen to the oxide semiconductor 401, the resistivity thereof can be reduced.
By any of the treatments for reducing the resistivity, the resistivity of the oxide semiconductor 401 at room temperature can be higher than or equal to 1×10−3 Ωcm and lower than or equal to 1×104 Ωcm.
This embodiment can be implemented in appropriate combination with any of the other embodiments.
In this embodiment, examples of electronic devices each including the semiconductor device, the display device, and/or the memory device described in the above embodiment are described.
In this embodiment, electronic devices each including a display device fabricated using one embodiment of the present invention are described.
The camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, and the like. A detachable lens 8006 is attached to the camera 8000.
Although the lens 8006 of the camera 8000 here is detachable from the housing 8001 for replacement, the lens 8006 may be integrated with the housing 8001.
The camera 8000 can take images at the press of the shutter button 8004. The display portion 8002 functions as a touch panel and images can also be taken at the touch of the display portion 8002.
The housing 8001 of the camera 8000 includes a mount including an electrode, so that the finder 8100, a stroboscope, or the like can be connected to the housing.
The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.
The housing 8101 includes a mount for engagement with the mount of the camera 8000 so that the finder 8100 can be attached to the camera 8000. The mount includes an electrode, and a video or the like received from the camera 8000 through the electrode can be displayed on the display portion 8102.
The button 8103 functions as a power button. The on/off state of the display portion 8102 can be switched with the button 8103.
The display device of one embodiment of the present invention can be used in the display portion 8002 of the camera 8000 and the display portion 8102 of the finder 8100.
Note that although the camera 8000 and the finder 8100 are separate and detachable electronic devices in
The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. A battery 8206 is incorporated in the mounting portion 8201.
The cable 8205 supplies electric power from the battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like and can display received video information, such as image data, on the display portion 8204. The movement of the eyeball and the eyelid of a user is captured by a camera provided in the main body 8203 and then coordinates of the sight line of the user are calculated using the information to utilize the sight line of the user as an input means.
A plurality of electrodes may be provided in a portion of the mounting portion 8201 the user touches. The main body 8203 may have a function of sensing current flowing through the electrodes with the movement of the user's eyeball to recognize the user's sight line. The main body 8203 may have a function of sensing current flowing through the electrodes to monitor the user's pulse. The mounting portion 8201 may include various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor to have a function of displaying the user's biological information on the display portion 8204. The main body 8203 may sense the movement of the user's head or the like to change a video displayed on the display portion 8204 in synchronization with the movement.
The display device of one embodiment of the present invention can be used in the display portion 8204.
A user can see display on the display portion 8302 through the lenses 8305. Note that it is suitable that the display portion 8302 be curved and placed. When the display portion 8302 is curved and placed, a user can feel a high realistic sensation. Note that although the structure in which one display portion 8302 is provided is described in this embodiment as an example, the structure is not limited thereto, and two display portions 8302 may be provided. In that case, one display portion is placed for one eye of the user, so that three-dimensional display using parallax or the like is possible.
Note that the display device of one embodiment of the present invention can be used in the display portion 8302. The display device including the semiconductor device of one embodiment of the present invention has an extremely high resolution; thus, even when a video is magnified by the lenses 8305 as in
Next,
Electronic devices illustrated in
The electronic devices illustrated in
The details of the electronic devices illustrated in
The electronic devices described in this embodiment are characterized by including the display portion for displaying some sort of information. Note that the semiconductor device of one embodiment of the present invention can also be used for an electronic device that does not include a display portion.
At least part of the structure examples, the drawings corresponding thereto, and the like described in this embodiment can be implemented in combination with the other structure examples, the other drawings, and the like as appropriate.
At least part of this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.
In this embodiment, electronic devices of one embodiment of the present invention are described with reference to drawings.
Electronic devices exemplified below include a display device of one embodiment of the present invention in a display portion. Thus, the electronic devices achieve high resolution. In addition, the electronic devices can achieve both high resolution and a large screen.
The display portion of the electronic device of one embodiment of the present invention can display a video with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or more. In addition, as a screen size of the display portion, the diagonal can be greater than or equal to 20 inches, greater than or equal to 30 inches, greater than or equal to 50 inches, greater than or equal to 60 inches, or greater than or equal to 70 inches.
Examples of the electronic devices include a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game console, a portable information terminal, and an audio reproducing device, in addition to electronic devices with a relatively large screen, such as a television device, a desktop or laptop personal computer, a monitor of a computer or the like, digital signage, and a large game machine such as a pachinko machine.
The electronic device of one embodiment of the present invention or a lighting device can be incorporated along a curved inside/outside wall surface of a house or a building or a curved interior/exterior surface of a car.
The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, the electronic device can display a video, information, or the like on a display portion. In addition, when the electronic device includes the antenna and a secondary battery, the antenna may be used for contactless power transmission.
The electronic device of one embodiment of the present invention may include a sensor (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, a chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radioactive rays, flow rate, humidity, gradient, oscillation, odor, or infrared rays).
The electronic device of one embodiment of the present invention can have a variety of functions. For example, it can have a function of displaying a variety of information (a still image, a moving image, a text image, and the like) on the display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of executing a variety of software (programs), a wireless communication function, and a function of reading out a program or data stored in a recording medium.
The display device of one embodiment of the present invention can be used for the display portion 7500.
Operation of the television device 7100 illustrated in
Note that the television device 7100 has a structure in which a receiver, a modem, and the like are provided. A general television broadcast can be received with the receiver. In addition, when connected to a communication network with or without wires via the modem, one-way (from a transmitter to a receiver) or two-way (between a transmitter and a receiver or between receivers) data communication can also be performed.
The display device of one embodiment of the present invention can be used for the display portion 7500.
Digital signage 7300 illustrated in
The display device of one embodiment of the present invention can be used for the display portion 7500 in
A larger area of the display portion 7500 can increase the amount of information that can be provided at a time. In addition, the larger display portion 7500 attracts more attention, so that the effectiveness of the advertisement can be increased, for example.
It is preferable to use a touch panel for the display portion 7500 because in addition to display of a still image or a moving image on the display portion 7500, intuitive operation by a user is possible. Moreover, for an application for providing information such as route information or traffic information, usability can be enhanced by intuitive operation.
Furthermore, as illustrated in
Furthermore, it is possible to make the digital signage 7300 or the digital signage 7400 execute a game with the use of the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). Thus, an unspecified number of users can join in and enjoy the game concurrently.
At least part of this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.
In this embodiment, described is the composition of a CAC (Cloud-Aligned Composite)-OS applicable to the OS transistor described in the above embodiments.
The CAC-OS has, for example, a composition in which elements included in a metal oxide are unevenly distributed. Materials including unevenly distributed elements each have a size of greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, or a similar size. Note that in the following description of a metal oxide, a state in which one or more metal elements are unevenly distributed and regions including the metal element(s) are mixed is referred to as a mosaic pattern or a patch-like pattern. The regions each have a size of greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, or a similar size.
Note that a metal oxide preferably contains at least indium. In particular, indium and zinc are preferably contained. In addition, one kind or a plurality of kinds selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be contained.
For instance, a CAC-OS in an In—Ga—Zn oxide (an In—Ga—Zn oxide in the CAC-OS may be particularly referred to as CAC-IGZO) has a composition in which materials are separated into indium oxide (hereinafter InOX1 (X1 is a real number greater than 0)) or indium zinc oxide (hereinafter InX2ZnY2OZ2 (X2, Y2, and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter GaOX3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter GaX4ZnY4OZ4 (X4, Y4, and Z4 are real numbers greater than 0)), for example, so that a mosaic pattern is formed, and mosaic-like InOX1 or InX2ZnY2OZ2 is evenly distributed in the film (which is hereinafter also referred to as cloud-like).
That is, the CAC-OS is a composite metal oxide with a composition in which a region including GaOX3 as a main component and a region including InX2ZnY2OZ2 or InOX1 as a main component are mixed. Note that in this specification, for example, when the atomic ratio of In to an element Min a first region is greater than the atomic ratio of In to an element M in a second region, the first region has higher In concentration than the second region.
Note that IGZO is a common name, which may specify a compound containing In, Ga, Zn, and O. Typical examples of IGZO include a crystalline compound represented by InGaO3(ZnO)m1 (m1 is a natural number) and a crystalline compound represented by In(1+x0)Ga(1−x0)O3(ZnO)m0(−1≤x0≤1; m0 is a given number).
The above crystalline compounds have a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis alignment and are connected in the a-b plane direction without alignment.
On the other hand, the CAC-OS relates to the material composition of a metal oxide. In a material composition of a CAC-OS including In, Ga, Zn, and O, nanoparticle regions including Ga as a main component are observed in part of the CAC-OS and nanoparticle regions including In as a main component are observed in part thereof. These nanoparticle regions are randomly dispersed to form a mosaic pattern. Therefore, the crystal structure is a secondary element for the CAC-OS.
Note that in the CAC-OS, a stacked-layer structure including two or more films with different atomic ratios is not included. For example, a two-layer structure of a film including In as a main component and a film including Ga as a main component is not included.
A boundary between the region including GaOX3 as a main component and the region including InX2ZnY2OZ2 or InOX1 as a main component is not clearly observed in some cases.
Note that in the case where one kind or a plurality of kinds selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like are contained instead of gallium, the CAC-OS refers to a composition in which some regions that include the metal element(s) as a main component and are observed as nanoparticles and some regions that include In as a main component and are observed as nanoparticles are randomly dispersed in a mosaic pattern.
The CAC-OS can be formed by a sputtering method under conditions where a substrate is not heated, for example. In the case of forming the CAC-OS by a sputtering method, one or more selected from an inert gas (typically, argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. The ratio of the flow rate of an oxygen gas to the total flow rate of the deposition gas at the time of deposition is preferably as low as possible, and for example, the flow ratio of an oxygen gas is preferably higher than or equal to 0% and less than 30%, further preferably higher than or equal to 0% and less than or equal to 10%.
The CAC-OS is characterized in that no clear peak is observed in measurement using θ/2θ scan by an Out-of-plane method, which is an X-ray diffraction (XRD) measurement method. That is, X-ray diffraction shows no alignment in the a-b plane direction and the c-axis direction in the measured region.
In an electron diffraction pattern of the CAC-OS which is obtained by irradiation with an electron beam with a probe diameter of 1 nm (also referred to as a nanometer-sized electron beam), a ring-like region with high luminance and a plurality of bright spots in the ring-like region are observed. Therefore, the electron diffraction pattern indicates that the crystal structure of the CAC-OS includes an nc (nano-crystal) structure with no alignment in the plan-view direction and the cross-sectional direction.
Moreover, for example, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the CAC-OS in the In—Ga—Zn oxide has a composition in which regions including GaOx3 as a main component and regions including InX2ZnY2OZ2 or InOX1 as a main component are unevenly distributed and mixed.
The CAC-OS has a structure different from that of an IGZO compound in which metal elements are evenly distributed, and has characteristics different from those of the IGZO compound. That is, in the CAC-OS, regions including GaOX3 or the like as a main component and regions including InX2ZnY2OZ2 or InOX1 as a main component are phase-separated from each other and form a mosaic pattern.
The conductivity of a region including InX2ZnY2OZ2 or InOX1 as a main component is higher than that of a region including GaOX3 or the like as a main component. In other words, when carriers flow through regions including InX2ZnY2OZ2 or InOX1 as a main component, the conductivity of a metal oxide is exhibited. Accordingly, when regions including InX2ZnY2OZ2 or InOX1 as a main component are distributed in a metal oxide like a cloud, high field-effect mobility (μ) can be achieved.
In contrast, the insulating property of a region including GaOX3 or the like as a main component is higher than that of a region including InX2ZnY2OZ2 or InOX1 as a main component. In other words, when regions including GaOX3 or the like as a main component are distributed in a metal oxide, leakage current can be suppressed and favorable switching operation can be achieved.
Accordingly, when a CAC-OS is used for a semiconductor element, the insulating property derived from GaOX3 or the like and the conductivity derived from InX2ZnY2OZ2 or InOX1 complement each other, whereby high on-state current (Ion) and high field-effect mobility (μ) can be achieved.
A semiconductor element including a CAC-OS has high reliability. Thus, the CAC-OS is suitably used in a variety of semiconductor devices typified by a display.
This embodiment can be implemented in appropriate combination with any of the other embodiments.
Unless otherwise specified, an on-state current in this specification refers to a drain current of a transistor in an on state. Unless otherwise specified, the on state (sometimes abbreviated as on) refers to a state where the voltage between its gate and source (VG) is higher than or equal to the threshold voltage (Vth) in an n-channel transistor, and a state where VG is lower than or equal to Vth in a p-channel transistor. For example, the on-state current of an n-channel transistor refers to a drain current when VG is higher than or equal to Vth. Furthermore, the on-state current of a transistor depends on a voltage between a drain and a source (VD) in some cases.
Unless otherwise specified, an off-state current in this specification refers to a drain current of a transistor in an off state. Unless otherwise specified, the off state (sometimes abbreviated as off) refers to a state where VG is lower than Vth in an n-channel transistor, and a state where VG is higher than Vth in a p-channel transistor. For example, the off-state current of an n-channel transistor refers to a drain current when VG is lower than Vth. The off-state current of a transistor depends on VG in some cases. Thus, “the off-state current of a transistor is lower than 10−21 A” may mean that there is VG at which the off-state current of the transistor is lower than 10−21 A.
Furthermore, the off-state current of a transistor depends on VD in some cases. Unless otherwise specified, the off-state current in this specification may refer to an off-state current at VD with an absolute value of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Alternatively, the off-state current may refer to an off-state current at VD used in a semiconductor device or the like including the transistor.
Note that a voltage refers to a potential difference between two points, and a potential refers to electrostatic energy (electric potential energy) of a unit charge at a given point in an electrostatic field. Note that in general, a potential difference between a potential of one point and a reference potential (e.g., a ground potential) is simply called a potential or a voltage, and a potential and a voltage are used as synonymous words in many cases. Therefore, in this specification, a potential may be rephrased as a voltage and a voltage may be rephrased as a potential unless otherwise specified.
In this specification and the like, when there is a description which explicitly states that X and Y are connected, the case where X and Y are electrically connected and the case where X and Y are directly connected are regarded as being disclosed in this specification and the like.
Here, X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).
An example of the case where X and Y are directly connected is the case where X and Y are connected without an element that enables electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load).
In an example of the case where X and Y are electrically connected, at least one element that enables electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load) can be connected between X and Y. Note that a switch has a function of controlling whether current flows or not by being in a conduction state (an on state) or a non-conduction state (an off state). Alternatively, the switch has a function of selecting and changing a current path. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.
A semiconductor device that can be used for the frame memory described as an example in the above embodiment is described in this embodiment. The semiconductor device described below as an example can function as a memory device.
In this embodiment, a DOSRAM (registered trademark) is described as an example of a memory device using an oxide semiconductor. The name “DOSRAM” stands for a Dynamic Oxide Semiconductor Random Access Memory. A DOSRAM refers to a memory device in which a memory cell is a 1T1C (one transistor and one capacitor) cell where a writing transistor is a transistor formed using an oxide semiconductor.
A layered structure example of a DOSRAM 1000 is described with reference to
As illustrated in
In the cell array portion 1003, two transistors Tw1 share a semiconductor layer. The semiconductor layer and the bit line BL are electrically connected to each other through a conductor that is not illustrated.
The layered structure illustrated in
Metal oxides, insulators, conductors, and the like in
Here, the semiconductor layer of the transistor Tw1 is formed using a metal oxide (oxide semiconductor). An example is illustrated in which the semiconductor layer is formed of three metal oxide layers. The semiconductor layer is preferably formed using a metal oxide containing In, Ga, and Zn.
Here, when an element that can form an oxygen vacancy or an element that can be bonded to an oxygen vacancy is added to a metal oxide, the carrier density is increased and the resistance is reduced in some cases. For example, when a semiconductor layer with a metal oxide is selectively reduced in resistance, a source region or a drain region can be provided in the semiconductor layer.
Typical examples of an element that reduces the resistance of a metal oxide include boron and phosphorus. Moreover, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, a rare gas, or the like may be used. Typical examples of the rare gas element include helium, neon, argon, krypton, xenon, and the like. The concentration of the element can be measured by secondary ion mass spectrometry (SIMS) or the like.
In particular, boron and phosphorus are preferably used because an apparatus used in a manufacturing line for amorphous silicon or low-temperature polysilicon can be used. Using the apparatus in the existing production line can reduce capital investment.
The transistor including the semiconductor layer having selectively reduced resistance can be formed using a dummy gate, for example. Specifically, the dummy gate is provided over the semiconductor layer, and an element that reduces the resistance of the semiconductor layer is added to the semiconductor layer using the dummy gate as a mask. That is, the element is added to a region of the semiconductor layer that does not overlap with the dummy gate, so that a low-resistance region is formed. As a method for adding the element, an ion implantation method by which an ionized source gas is subjected to mass separation and then added, an ion doping method by which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like can be used.
Examples of a conductive material used for the conductors include a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus; silicide such as nickel silicide; a metal such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium; a metal nitride containing the above metal as its component (tantalum nitride, titanium nitride, molybdenum nitride, or tungsten nitride); and the like. A conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.
Examples of an insulating material used for the insulators include aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and aluminum silicate. Note that in this specification and the like, an oxynitride refers to a compound whose oxygen content is higher than nitrogen content, and a nitride oxide refers to a compound whose nitrogen content is higher than oxygen content.
C1: capacitor, C2: capacitor, C3: capacitor, C4: capacitor, CK1: wiring, CK5: wiring, CK6: wiring, CK7: wiring, CK8: wiring, GL1: wiring, GL2: wiring, GL3: wiring, IN1: input terminal, IN2: input terminal, IN3: input terminal, IN4: input terminal, IN5: input terminal, M1: transistor, M2: transistor, M3: transistor, M4: transistor, M5: transistor, M6: transistor, M7: transistor, M8: transistor, M9: transistor, M10: transistor, M11: transistor, M12: transistor, M13: transistor, M14: transistor, M15: transistor, M16: transistor, ND1: node, ND2: node, OP1: output terminal, OP2: output terminal, S1: switch, S2: switch, S3: switch, S4: switch, SL1: wiring, SL2: wiring, VDD1: wiring, VDD2: wiring, 10: semiconductor device, 11: band gap reference circuit, 11a: output terminal, 11b: output terminal, 11c: output terminal, 11d: band gap reference circuit, 11e: reference voltage current generation circuit, 12: voltage reference circuit, 12a: input terminal, 12b: output terminal, 12c: input terminal, 12d: input terminal, 13: selection circuit, 13a: input terminal, 13b: input terminal, 13c: output terminal, 13d: input terminal, 14: difference detection circuit, 15: voltage controlled oscillator, 16: negative voltage generation circuit, 16a: input terminal, 16b: output terminal, 16c: level shifter circuit, 16d: charge pump circuit, 16e: input terminal, 16f: input terminal, 17: operation mode control circuit, 18: amplifier, 19: temperature sensor, 20: display device, 21: control portion, 22: display controller, 23: frame memory, 23a: memory device, 23b: memory device, 24: source driver, 24a: buffer circuit, 24b: digital-analog converter circuit, 24c: level shifter circuit, 24d: latch circuit, 24e: switch control circuit, 25: gate driver, 25a: shift register circuit, 25b: shift register circuit, 25c: buffer circuit, 25d: buffer circuit, 25e: inversion control circuit, 26: display device, 26a: pixel, 26b: pixel, 26c: pixel, 27: CPU, 30: amplifier, 31a: transistor, 31b: transistor, 31c: transistor, 31d: transistor, 32a: resistor, 32b: resistor, 32c: resistor, 33: transistor, 34: resistor, 35: transistor, 36a: level shifter, 36b: level shifter, 37a: transistor, 37b: transistor, 37c: capacitor, 38a: transistor, 38b: transistor, 38c: capacitor, 39: transistor, 41: display element, 42: display element, 45: transistor, 48: transistor, 100: semiconductor device, 100a: semiconductor device, 100b: semiconductor device.
This application is based on Japanese Patent Application Serial No. 2017-245920 filed with Japan Patent Office on Dec. 22, 2017 and Japanese Patent Application Serial No. 2018-027234 filed with Japan Patent Office on Feb. 19, 2018, the entire contents of which are hereby incorporated herein by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| JP2017-245920 | Dec 2017 | JP | national |
| JP2018-027234 | Feb 2018 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/IB2018/059811 | 12/10/2018 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2019/123089 | 6/27/2019 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5903248 | Irwin | May 1999 | A |
| 6600436 | Tanaka | Jul 2003 | B2 |
| 7224338 | Yamada | May 2007 | B2 |
| 8054393 | Takahashi | Nov 2011 | B2 |
| 8421784 | Zebedee | Apr 2013 | B2 |
| 8519990 | Yamazaki et al. | Aug 2013 | B2 |
| 8884852 | Yamamoto et al. | Nov 2014 | B2 |
| 8976090 | Yamamoto et al. | Mar 2015 | B2 |
| 9165523 | Funayama et al. | Oct 2015 | B2 |
| 9324263 | Sugimoto | Apr 2016 | B2 |
| 20020186157 | Tanaka | Dec 2002 | A1 |
| 20040174329 | Yamada | Sep 2004 | A1 |
| 20050024317 | Sano | Feb 2005 | A1 |
| 20070164946 | Akutsu | Jul 2007 | A1 |
| 20100238146 | Zebedee | Sep 2010 | A1 |
| 20100289830 | Yamamoto | Nov 2010 | A1 |
| 20120062537 | Jeong et al. | Mar 2012 | A1 |
| 20120162287 | Funayama et al. | Jun 2012 | A1 |
| 20120223978 | Yamamoto et al. | Sep 2012 | A1 |
| 20120236222 | Kim et al. | Sep 2012 | A1 |
| 20120249509 | Kim et al. | Oct 2012 | A1 |
| 20130069717 | Kim | Mar 2013 | A1 |
| 20160225859 | Takata | Aug 2016 | A1 |
| 20200193928 | Kawashima et al. | Jun 2020 | A1 |
| Number | Date | Country |
|---|---|---|
| 001573452 | Feb 2005 | CN |
| 101490962 | Jul 2009 | CN |
| 101887689 | Nov 2010 | CN |
| 102568419 | Jul 2012 | CN |
| 102654979 | Sep 2012 | CN |
| 09-275345 | Oct 1997 | JP |
| 2001-520762 | Oct 2001 | JP |
| 2002-359559 | Dec 2002 | JP |
| 2004-274335 | Sep 2004 | JP |
| 2005-010697 | Jan 2005 | JP |
| 2007-028662 | Feb 2007 | JP |
| 2009-109600 | May 2009 | JP |
| 2009-541781 | Nov 2009 | JP |
| 2010-266494 | Nov 2010 | JP |
| 2011-227479 | Nov 2011 | JP |
| 2012-141393 | Jul 2012 | JP |
| 4970472 | Jul 2012 | JP |
| 2012-185328 | Sep 2012 | JP |
| 2004-0080338 | Sep 2004 | KR |
| 10-0608967 | Aug 2006 | KR |
| 2010-0122443 | Nov 2010 | KR |
| WO 1998047131 | Oct 1998 | WO |
| WO 2008018622 | Feb 2008 | WO |
| Entry |
|---|
| International Search Report (Application No. PCT/IB2018/059811) dated Apr. 2, 2019. |
| Written Opinion (Application No. PCT/IB2018/059811) dated Apr. 2, 2019. |
| Yamazaki, S. et al., “Research, Development, and Application of Crystalline Oxide Semiconductor,” SID Digest '12: SID International Symposium Digest of Technical Papers, Jun. 5, 2012, vol. 43, No. 1, pp. 183-186. |
| Yamazaki, S. et al., “Properties of Crystalline In—Ga—Zn-oxide Semiconductor and its Transistor Characteristics,” Japanese Journal of Applied Physics, Mar. 31, 2014, vol. 53, No. 4S, pp. 04ED18-1-04ED18-10. |
| Ito, S. et al., “Analysis of Nanoscale Crystalline Structure of In—Ga—Zn—O Thin Film with Nano Beam Electron Diffraction,” AM-FPD '13 Digest of Technical Papers, Jul. 2, 2013, pp. 151-154. |
| Yamazaki, S. et al., “In—Ga-—Zn-Oxide Semiconductor and Its Transistor Characteristics,” ECS Journal of Solid State Science and Technology, Jul. 1, 2014, vol. 3, No. 9, pp. Q3012-Q3022. |
| Yamazaki, S., “Crystalline Oxide Semiconductor Using CAAC-IGZO and its Application,” ECS Transactions, Oct. 1, 2014, vol. 64, No. 10, pp. 155-164, The Electrochemical Society. |
| Kato, K. et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Japanese Journal of Applied Physics, 2012, vol. 51, pp. 021201-1-021201-7. |
| Matsuda, S. et al., “30-nm-Channel-Length C-Axis Aligned Crystalline In—Ga—Zn—O Transistors with Low Off-State Leakage Current and Steep Subthreshold Characteristics,” 2015 Symposium On VLSI Technology : Digest of Technical Papers, 2015, pp. T216-T217. |
| Amano, S. et al., “Low Power LC Display Using In—Ga—Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Digest '10: SID International Symposium Digest of Technical Papers, May 23, 2010, vol. 41, No. 1, pp. 626-629. |
| Ryu, S. et al., “A 13-bit Universal Column Driver for Various Displays of OLED and LCD,” Journal of the Society for Information Display, May 4, 2016, vol. 24, No. 5, pp. 277-285. |
| Number | Date | Country | |
|---|---|---|---|
| 20210090513 A1 | Mar 2021 | US |
