Patent Application
20130215370
The present invention generally relates to substrates for display devices (hereinafter referred to as “display device substrates”), and more particularly to display device substrates including semiconductor layers made of oxide semiconductors, methods for fabricating such substrates, and display devices.
In a thin film transistor substrate (active matrix substrate), a thin film transistor (hereinafter referred to as a “TFT”) is provided as a switching device in each of the pixels, which are minimum units of an image.
In the thin film transistor substrate, a thin film transistor using semiconductor layers of amorphous silicon is generally used as a switching device of each of the pixels, which are minimum units of an image.
A typical bottom gate-type TFT includes, e.g., a gate electrode provided on an insulating substrate, a gate insulating layer provided to cover the gate electrode, an island-shaped semiconductor layer provided on the gate insulating layer to overlap the gate electrode, and a source electrode and a drain electrode provided on the semiconductor layer to face each other.
In the bottom gate-type TFT, the upper part of a channel region of the semiconductor layer is covered with an interlayer insulating film made of SiO2 etc., and the surface of an interlayer insulating film is covered with a planarization film made of an acrylic resin etc. A pixel electrode made of indium tin oxide (ITO) is formed on the planarization film, and the drain electrode is connected to the pixel electrode through a contact hole formed in a multilayer film of the interlayer insulating film and the planarization film.
The pixel electrode is formed on the planarization film, thereby fabricating the thin film transistor substrate, and a counter substrate is provided to face the thin film transistor substrate, and a liquid crystal layer is provided between the thin film transistor substrate and the counter substrate, thereby fabricating a liquid crystal display device (for example, see Patent Document 1).
PATENT DOCUMENT 1: Japanese Patent Publication No. 2000-199917
In the above conventional thin film transistor substrate, the drain electrode is constituted by a multilayer film of a first conductive layer made of titanium, and a second conductive layer formed on the first conductive layer and made of aluminum. The second conductive layer serves as an etching stopper layer for improving selectivity during etching of the interlayer insulating film.
However, it is difficult to connect the aluminum constituting the second conductive layer to the pixel electrode made of ITO, and therefore, a poor connection may occur between the second conductive layer and the pixel electrode, resulting in deterioration of display quality.
The first conductive layer of the drain electrode may be connected to the pixel electrode through the semiconductor layer. However, if the semiconductor layer is made of amorphous silicon, the resistance of the amorphous silicon is high, and therefore, it has been difficult to connect the pixel electrode and the first conductive layer of the drain electrode together through the amorphous silicon layer.
Accordingly, in the above conventional thin film transistor substrate, in order to avoid a poor connection between the second conductive layer and the pixel electrode, and connect the pixel electrode and the drain electrode together through the contact hole, it is necessary to etch (wet-etch) the second conductive layer to cause etching shift of the second conductive layer so that the second conductive layer is located under the interlayer insulating film, and the first conductive layer is exposed, thereby connecting the first conductive layer and the pixel electrode together. This disadvantageously causes an increase in the number of fabrication process steps.
In view of the foregoing, the present invention has been developed. It is an objective of the present invention to provide a display device substrate capable of preventing a poor connection between a pixel electrode and a drain electrode to prevent deterioration of display quality without causing an increase in the number of fabrication process steps, and a method of fabricating the display device substrate, and a display device.
In order to achieve the above object, a display device substrate in the present invention includes: an insulating substrate; a gate insulating layer provided on the insulating substrate; a connection layer provided on the gate insulating layer, and made of indium gallium zinc oxide; a drain electrode provided on the connection layer, and made of titanium or a metal whose standard electrode potential is lower than that of titanium; a contact hole formed in the connection layer and the drain electrode; and a pixel electrode provided on a surface of the contact hole, and contacting the connection layer, wherein the drain electrode and the pixel electrode are electrically connected together through the connection layer.
In this configuration, indium of the indium gallium zinc oxide which constitutes the connection layer is reduced by titanium which constitutes the drain electrode or a metal which constitutes the drain electrode and whose standard electrode potential is lower than that of titanium, and the resistance of the connection layer is decreased, thereby making it possible to connect the pixel electrode and the drain electrode together through the connection layer whose resistance is decreased. Therefore, unlike the above-described conventional techniques, it is unnecessary to perform an etching process for connecting the pixel electrode and the drain electrode together. As a result, it becomes possible to prevent a poor connection between the pixel electrode and the drain electrode to prevent deterioration of display quality without causing an increase in the number of fabrication process steps.
In the display device substrate of the present invention, the drain electrode may include a first conductive layer provided on a surface of the connection layer, and a second conductive layer provided on a surface of the first conductive layer, and the first conductive layer may be made of the titanium.
In this configuration, the drain electrode has a multilayer structure of the first conductive layer and the second conductive layer, and even if a poor connection occurs between the pixel electrode and the second conductive layer, the pixel electrode and the second conductive layer of the drain electrode can be connected together through the connection layer whose resistance is decreased.
A display device substrate in the present invention includes: an insulating substrate; a line provided on the insulating substrate, and formed by a gate line layer; a gate insulating layer covering the line formed by the gate line layer; a connection layer provided on the gate insulating layer, and made of indium gallium zinc oxide; a line provided on the connection layer, and formed by a source line layer made of titanium or a metal whose standard electrode potential is lower than that of titanium; a contact hole formed in the gate insulating layer, the connection layer, and the line formed by the source line layer; and a conductive film provided on a surface of the contact hole, and contacting the line formed by the gate line layer and the connection layer, wherein the line formed by the gate line layer and the line formed by the source line layer are electrically connected together through the connection layer and the conductive film.
In this configuration, indium of the indium gallium zinc oxide which constitutes the connection layer is reduced by titanium which constitutes the line formed by the source line layer or a metal which constitutes the line formed by the source line layer and whose standard electrode potential is lower than that of titanium, and the resistance of the connection layer is decreased, thereby making it possible to connect the line formed by the gate line layer and the line formed by the source line layer together through the connection layer whose resistance is decreased. Therefore, unlike the above-described conventional techniques, it is unnecessary to perform an etching process for connecting the line formed by the gate line layer and the line formed by the source line layer together. As a result, it becomes possible to prevent a poor connection between the line formed by the gate line layer and the line formed by the source line layer to prevent deterioration of display quality without causing an increase in the number of fabrication process steps.
In the display device substrate of the present invention, the line formed by the source line layer may include a first conductive layer provided on a surface of the connection layer, and a second conductive layer provided on a surface of the first conductive layer, and the first conductive layer may be made of the titanium.
In this configuration, the line formed by the source line layer has a multilayer structure of the first conductive layer and the second conductive layer, and even if a poor connection occurs between the conductive film and the second conductive layer, the line formed by the gate line layer and the second conductive layer of the line formed by the source line layer can be connected together through the connection layer whose resistance is decreased.
The display device substrate in the present invention has an outstanding advantage of preventing a poor connection between the pixel electrode and the drain electrode or a poor connection between the gate line and the source line to prevent deterioration of display quality without causing an increase in the number of fabrication process steps. Therefore, the display device substrate in the present invention can be preferably used to a display device including another display device substrate provided to face the display device substrate; and a display medium layer provided between the display device substrate and the another display device substrate. The display device in the present invention can be preferably used to a display device in which the display medium layer is a liquid crystal layer.
A method for forming a display device substrate in the present invention includes: a gate insulating layer formation step of forming a gate insulating layer on an insulating substrate; a connection layer formation step of forming, on the gate insulating layer, a connection layer made of indium gallium zinc oxide; a drain electrode formation step of forming, on the connection layer, a drain electrode made of titanium or a metal whose standard electrode potential is lower than that of titanium; a contact hole formation step of forming a contact hole in the connection layer and the drain electrode; and a pixel electrode formation step of forming a pixel electrode on a surface of the contact hole to contact the connection layer, thereby electrically connecting the drain electrode and the pixel electrode together through the connection layer.
In this configuration, indium of the indium gallium zinc oxide which constitutes the connection layer is reduced by titanium which constitutes the drain electrode or a metal which constitutes the drain electrode and whose standard electrode potential is lower than that of titanium, and the resistance of the connection layer is decreased, thereby making it possible to connect the pixel electrode and the drain electrode together through the connection layer whose resistance is decreased. Therefore, unlike the above-described conventional techniques, it is unnecessary to perform an etching process for connecting the pixel electrode and the drain electrode together. As a result, it becomes possible to prevent a poor connection between the pixel electrode and the drain electrode to prevent deterioration of display quality without causing an increase in the number of fabrication process steps.
In the method of forming the display device substrate in the present invention, in the drain electrode formation step, a first conductive layer made of titanium may be formed on a surface of the connection layer, and a second conductive layer may be formed on the first conductive layer, thereby forming the drain electrode including a multilayer film of the first conductive layer and the second conductive layer.
In this configuration, the drain electrode has the multilayer structure of the first conductive layer and the second conductive layer, and even if a poor connection occurs between the pixel electrode and the second conductive layer, the pixel electrode and the second conductive layer of the drain electrode can be connected together through the connection layer whose resistance is decreased.
A method for forming a display device substrate in the present invention includes: a line formation step of forming a line formed by a gate line layer on an insulating substrate; a gate insulating layer formation step of forming a gate insulating layer covering the line formed by the gate line layer; a connection layer formation step of forming, on the gate insulating layer, a connection layer made of indium gallium zinc oxide; another line formation step of forming, on the connection layer, a line formed by a source line layer made of titanium or a metal whose standard electrode potential is lower than that of titanium; a contact hole formation step of forming a contact hole in the gate insulating layer, the connection layer, and the line formed by the source line layer; and a conductive film formation step of forming a conductive film on a surface of the contact hole to contact the line formed by the gate line layer and the connection layer, thereby electrically connecting the line formed by the gate line layer and the line formed by the source line layer together through the connection layer and the conductive film.
In this configuration, indium of the indium gallium zinc oxide which constitutes the connection layer is reduced by titanium which constitutes the line formed by the source line layer or a metal which constitutes the line formed by the source line layer and whose standard electrode potential is lower than that of titanium, and the resistance of the connection layer is decreased, thereby making it possible to connect the line formed by the gate line layer and the line formed by the source line layer together through the connection layer whose resistance is decreased. Therefore, unlike the above-described conventional techniques, it is unnecessary to perform an etching process for connecting the line formed by the gate line layer and the line formed by the source line layer together. As a result, it becomes possible to prevent a poor connection between the line formed by the gate line layer and the line formed by the source line layer to prevent deterioration of display quality without causing an increase in the number of fabrication process steps.
In the method of forming the display device substrate in the present invention, in the another formation step, a first conductive layer made of titanium may be formed on a surface of the connection layer, and a second conductive layer may be formed on the first conductive layer, thereby forming the line formed by the source line layer including a multilayer film of the first conductive layer and the second conductive layer.
In this configuration, the source line has the multilayer structure of the first conductive layer and the second conductive layer, and even if a poor connection occurs between the conductive film and the second conductive layer, the gate line and the second conductive layer of the source line can be connected together through the connection layer whose resistance is decreased.
According to the present invention, it is possible to prevent a poor connection between a pixel electrode and a drain electrode, and a poor connection between a line formed by a gate line layer and a line formed by a source line layer to prevent deterioration of display quality without causing an increase in the number of fabrication process steps.
An embodiment of the present invention will be described hereinafter with reference to the drawings. The present invention is not limited to the following embodiment.
As illustrated in
As illustrated in
As illustrated in
The gate lines 11a extend to a gate terminal region Tg of the terminal region T illustrated in
In a source terminal region Ts of the terminal region T illustrated in
As illustrated in
Each of the TFTs 5a has a bottom-gate structure and, as illustrated in
In this configuration, the interlayer insulating film 17 covering the source electrode 16aa and the drain electrode 16b (i.e., the TFTs 5a) is provided on the channel region C of the oxide semiconductor layer 13a.
As illustrated in
The first conductive layers 14a and 14b are made of, e.g., titanium and the second conductive layers 15a and 15b are made of, e.g., aluminum. The drain electrode 16b overlaps the auxiliary capacitor line 11b through the gate insulating layer 12, thereby forming an auxiliary capacitor.
The oxide semiconductor layer 13a is made of an oxide semiconductor of, e.g., indium gallium zinc oxide (IGZO).
In this embodiment, as illustrated in
In order to electrically connect the plurality of auxiliary capacitor lines 11b to each other, each of the auxiliary capacitor lines 11b being provided between the respective gate lines 11a and extending in parallel with each other, it is necessary to connect the auxiliary capacitor lines 11b together through other lines (i.e., the source lines 16a) except the gate lines 11a provided in the same layer as the auxiliary capacitor lines 11b, and therefore, the line change region T1 is a region for ensuring an electric connection between the gate line 11a and the signal lines 16 to connect the plurality of the auxiliary capacitor lines 11b together through the source lines 16a.
The line change region T2 is a region which changes the line between the source lines 16a and the gate lines 11a, and the source terminals 19c and the source lines 16a are made of the same metal as the gate lines 11a, thereby reducing improper mounting caused by problems such as corrosion since there is no barrier metal in the upper layer like a case where the source lines 16a are made of a multilayer film of, such as aluminum/titanium, copper/titanium. Moreover, the formation of the line change region T2 can improve reworkability to correct defects which occur when forming the source terminals 19c and the source lines 16a since the source terminals 19c and the source lines 16a are simultaneously formed in the formation of the gate lines 11a.
As illustrated in
As well as the source electrode 16aa described above, the source line 16a is made of a multilayer film of the first conductive layer 14a and the second conductive layer 15a.
As illustrated
The liquid crystal layer 40 is made of, for example, a nematic liquid crystal material having electrooptic properties.
In each of the pixels in the liquid crystal display device 50 having the above-described configuration, when a gate signal is transmitted from a gate driver (not shown) to the gate electrode 11aa through the gate line 11a to turn on the TFT 5a, a source signal is sent from a source driver (not shown) to the source electrode 16aa through the signal line 16a, thereby writing a predetermined amount of charge in the pixel electrode 19a through the oxide semiconductor layer 13a and the drain electrode 16b.
In this process, a potential difference occurs between the pixel electrode 19a of the active matrix substrate 20 and the common electrode 23 of the counter substrate 30, resulting in that a predetermined voltage is applied to the liquid crystal layer 40, i.e., a liquid crystal capacitor of each pixel and an auxiliary capacitor connected to the liquid crystal capacitor in parallel.
In each of the pixels in the liquid crystal display device 50, the alignment state of the liquid crystal layer 40 is changed depending on the level of the voltage applied to the liquid crystal layer 40. In this manner, an image is displayed with adjustment of the light transmittance of the liquid crystal layer 40.
As illustrated in
As illustrated in
The pixel electrode 19a and the drain electrode 16b are electrically connected together through the connection layer 25 made of the oxide semiconductor by a connection path 31 illustrated by an arrow in
As well as the oxide semiconductor layer 13a described above, as the oxide semiconductor which constitutes the connection layer 25, an oxide semiconductor made of, e.g., indium gallium zinc oxide (IGZO) can be used.
Next, the principle of connection between the pixel electrode 19a and the drain electrode 16b through the connection layer 25 made of the oxide semiconductor will be described.
The results shown in
As can be seen from
Similarly, as can be seen from
In other words, in this embodiment, the oxide semiconductor (IGZO) which constitutes the connection layer 25 is reduced by the titanium which constitutes the first conductive layer 14b of the drain electrode 16b contacting the connection layer 25, and therefore, it becomes possible to cause a decrease in resistance of the connection layer 25 made of the oxide semiconductor.
As described above, since in this embodiment, the pixel electrode 19a and the drain electrode 16b can be connected together through the connection layer 25 whose resistance is decreased, unlike the above-described conventional techniques, it is unnecessary to perform an etching process for connecting the pixel electrode 19a and the drain electrode 16b together. Therefore, it becomes possible to prevent a poor connection between the pixel electrode 19a and the drain electrode 16b to prevent deterioration of display quality without causing an increase in the number of fabrication process steps.
If the second conductive layer 15b is made of copper, when the interlayer insulating film 17 is formed on the second conductive layer 15b, an oxide film (copper oxide) is formed on the surface of the second conductive layer 15b. However, in this embodiment, the pixel electrode 19a and the drain electrode 16b can be connected together through the connection layer 25 whose resistance is decreased, and therefore, the step of removing the oxide film is not needed.
In this embodiment, as illustrated in
As illustrated in
The auxiliary capacitor line 11b and the line constituted by the first conductive layer 14a and the second conductive layer 15a are electrically connected together through the connection layer 38 made of the oxide semiconductor and the transparent conductive film 41 by a connection path 42 illustrated by an arrow in
As well as the oxide semiconductor layer 13a and the connection layer 25 described above, as the oxide semiconductor which constitutes the connection layer 38, an oxide semiconductor made of, e.g., indium gallium zinc oxide (IGZO) can be used.
As well as the connection region 29 provided with the connection layer 25 described above, in the connection region 32, the oxide semiconductor (IGZO) which constitutes the connection layer 38 is reduced by the titanium which constitutes the first conductive layer 14a of the source line 16a contacting the connection layer 38, and therefore, it becomes possible to cause a decrease in resistance of the connection layer 38 made of the oxide semiconductor.
Therefore, since in this embodiment, the auxiliary capacitor line 11b and the line constituted by the first conductive layer 14a and the second conductive layer 15a can be connected together through the connection layer 38 whose resistance is decreased, and as well as the connection region 29, it is unnecessary to perform an etching process for connecting the auxiliary capacitor line 11b and the line constituted by the first conductive layer 14a and the second conductive layer 15a together. Therefore, it becomes possible to prevent a poor connection between the auxiliary capacitor line 11b and the line constituted by the first conductive layer 14a and the second conductive layer 15a to prevent deterioration of display quality without causing an increase in the number of fabrication process steps.
In this embodiment, the drain electrode 16b is made of a multilayer film of the first conductive layer 14b and the second conductive layer 15b, and the first conductive layer 14b of the drain electrode 16b contacting the connection layer 25 is made of titanium. Therefore, even if the drain electrode 16b is made of the multilayer film of the first conductive layer 14b and the second conductive layer 15b, and a poor connection occurs between the pixel electrode 19a and the second conductive layer 15b, the pixel electrode 19a and the second conductive layer 15b of the drain electrode 16b can be connected together through the connection layer 25 whose resistance is decreased.
Similarly, the line formed by the source line layer is made of a multilayer film of the first conductive layer 14a and the second conductive layer 15a, and the first conductive layer 14a contacting the connection layer 38 is made of titanium. Therefore, even if the line formed by the source line layer is made of the multilayer film of the first conductive layer 14a and the second conductive layer 15a, and a poor connection occurs between the transparent conductive film 41 and the second conductive layer 15a, the auxiliary capacitor line 11b and the second conductive layer 15a can be connected together through the connection layer 38 whose resistance is decreased.
Next, an example method for fabricating the liquid crystal display device 50 according to this embodiment will be described with reference to
Process steps of forming the thin film transistor substrate will now be described.
<Gate Electrode and Gate Line Formation Step>
First, for example, a molybdenum film (with a thickness of about 150 nm) is deposited by sputtering over the entire surface of an insulating substrate 10a such as a glass substrate, a silicon substrate, a heat-resistant plastic substrate, etc. Thereafter, patterning of a resist by photolithography with a first photomask, wet etching of the molybdenum film, removal of the resist, and cleaning are performed, thereby forming the gate lines 11a, the gate electrodes 11aa, the auxiliary capacitor lines 11b, and the relay lines 11c on the insulating substrate 10a, as illustrated in
In this embodiment, the molybdenum film having a single-layer structure is illustrated as a metal film which constitutes the gate electrodes 11aa. Alternatively, the gate electrodes 11aa may be made of a metal film, such as an aluminum film, a tungsten film, a tantalum film, a chromium film, a titanium film, a copper film, etc., or an alloy or metal nitride film thereof which have a thickness of 50 nm-300 nm.
The plastic substrate may be made of, for example, polyethylene terephthalate resin, polyethylene naphthalate resin, polyethersulfone resin, acrylic resin, or polyimide resin.
<Gate Insulating Layer Formation Step>
Next, for example, a silicon nitride film (with a thickness of about 200 nm-500 nm) is deposited by CVD over the entire substrate on which the gate lines 11a, the gate electrodes 11aa, and the auxiliary capacitor lines 11b are formed, thereby forming the gate insulating layer 12 covering the gate lines 11a, the gate electrodes 11aa, and the auxiliary capacitor lines 11b, as illustrated in
The gate insulating layer 12 may be made of a multilayer film of two layers. In this case, in addition to the silicon nitride film (SiNx), a silicon oxide film (SiOx), a silicon oxynitride film (SiOxNy, x>y), or a silicon nitride oxide film (SiNxOy, x>y), for example, may be used.
To prevent diffusion of, for example, an impurity from the insulating substrate 10a, a silicon nitride film or a silicon nitride oxide film is preferably used as a lower gate insulating layer, whereas a silicon oxide film or a silicon oxynitride film is preferably used as an upper gate insulating layer. For example, a silicon nitride film with a thickness of 100 nm-200 nm may be formed as a lower gate insulating layer using SiH4 and NH3 as a reactant gas, and a silicon oxide film with a thickness of 50 nm-100 nm may be formed using N2O and SiH4 as a reactant gas.
To deposit a dense gate insulating layer 12 with a small gate leakage current at a low temperature, a rare gas such as an argon gas is preferably contained in the reactant gas to be mixed in the insulating layer.
<Semiconductor Layer and Connection Layer Formation Step>
Thereafter, for example, an oxide semiconductor film (with a thickness of about 30 nm-100 nm) of indium gallium zinc oxide (IGZO) is deposited by sputtering. Then, patterning of a resist by photolithography with a second photomask, wet etching of the oxide semiconductor film, removal of the resist, and cleaning are performed thereby forming the oxide semiconductor layers 13a, and the connection layers 25 and 38 on the gate insulating layer 12, as illustrated in
<Source Line and Drain Electrode Formation Step>
Next, as illustrated in
Thereafter, patterning of a resist by photolithography with a third photomask, wet etching of the aluminum film are performed, and dry etching (plasma etching) of the titanium film, removal of the resist, and cleaning are performed. As illustrated in
In other words, in this step, the drain electrode 16b is formed by dry etching on the connection layer 25 which has been formed in the connection layer formation step, whereby the connection layer 25 and the first conductive layer 14b of the drain electrode 16b are in contact with each other.
Similarly, the lines formed by the source line layers are formed by dry etching on the connection layers 38 which have been formed in the connection layer formation step, whereby the connection layer 38 and the first conductive layer 14a that is the line formed by the source line layer are in contact with each other.
In the etching process, either the dry etching described above or the wet etching described above may be used, and if a substrate having a large area is processed, the dry etching is preferably used. A fluorine-based gas, such as CF4, NF3, SF6, CHF3, etc., a chlorine-based gas, such as Cl2, BCl3, SiCl4, CCl4, etc., an oxygen-based gas, etc., can be used as an etching gas, and an inert gas, such as helium and argon, etc., may be added.
<Interlayer Insulating Film Formation Step>
Thereafter, for example, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film, etc., is deposited by plasma CVD over the entire substrate on which the source and drain electrodes 16aa and 16b (i.e., the TFTs 5a), and the lines formed by the source line layers are formed, thereby forming an interlayer insulating film 17 having a thickness of about 400 nm, and covering the TFTs 5a (i.e., the oxide semiconductor layers 13a, the source electrodes 16aa, the drain electrodes 16b, and the connection layers 25), the lines formed by the source line layers, and the connection layers 38, as illustrated in
<Planarization Film Formation Step>
Next, the entire substrate including the interlayer insulating film 17 is coated with a photosensitive organic insulating film 28 made of, for example, a photosensitive acrylic resin, and having a thickness of about 1.0 μm-3.0 μm by spin coating or slit coating, as illustrated in
Next, patterning of a resist by photolithography with a fourth photomask, exposure and development of the organic insulating film 28, removal of the resist, and cleaning are performed, thereby forming the planarization film 18 on the surface of the interlayer insulating film 17, as illustrated in
<Contact Hole Formation Step>
Next, dry etching is performed by using a predetermined etching gas (for example, a CF4 gas and an O2 gas) with the planarization film 18, the source electrodes 16aa and the drain electrodes 16b as masks to remove part of the interlayer insulating film 17 and part of the connection layers 25, thereby forming the contact holes Ca in the connection layers 25 and the drain electrodes 16b to form the connection layers 29 each in which the contact hole Ca is formed, as illustrated in
Dry etching is performed by using a predetermined etching gas (for example, a CF4 gas and an O2 gas) with the planarization film 18, the lines formed by the source line layers, and the connection layers 38 as masks to remove part of the interlayer insulating film 17 and part of the gate insulating layer 12, thereby forming the contact holes Cc in the gate insulating layer 12, the connection layers 38, and the lines formed by the source line layers to form the connection layers 32 each in which the contact hole Cc is formed, as illustrated in
The contact holes Cb described above are formed at the same time of forming the contact holes Ca and Cc by etching of the gate insulating layer 12.
When the contact holes Ca and Cc are formed, the etching selectivity of the connection layer 25 at the side of the contact hole Ca, and the etching selectivity of the gate insulating layer 12 at the side of the contact hole Cc are adjust, thereby stopping the etching at the connection layer 25 at the side of the contact hole Ca to make it possible to prevent etching of the gate insulating layer 12.
<Pixel Electrode and Transparent Conductive Film Formation Step>
Finally, for example, an ITO film (with a thickness of about 50 nm-200 nm) of indium tin oxide is deposited by sputtering over the entire substrate on which the interlayer insulating film 17 and the planarization film 18 are formed. Then, patterning of a resist by photolithography with a fifth photomask, wet etching of the ITO film, removal of the resist, and cleaning are performed, thereby forming the pixel electrodes 19a on the surfaces of the contact holes Ca, as illustrated in
At this time, as illustrated in
As described above, in this embodiment, the pixel electrode 19a and the drain electrode 16b can be connected together through the connection layer 25 without an etching process for connecting the pixel electrode 19a and the drain electrode 16b together. Therefore, it becomes possible to prevent a poor connection between the pixel electrode 19a and the drain electrode 16b to prevent deterioration of display quality without causing an increase in the number of fabrication process steps.
As illustrated in
Therefore, the auxiliary capacitor line 11b and the line constituted by the first conductive layer 14a and the second conductive layer 15a can be connected together through the connection layer 38 without an etching process for connecting the auxiliary capacitor line 11b and the line constituted by the first conductive layer 14a and the second conductive layer 15a together. Therefore, it becomes possible to prevent a poor connection between the auxiliary capacitor line 11b and the line constituted by the first conductive layer 14a and the second conductive layer 15a to prevent deterioration of display quality without causing an increase in the number of fabrication process steps.
In the case of forming a transmissive liquid crystal display device 50, the pixel electrodes 19a may include indium oxide or indium zinc oxide containing tungsten oxide, or include indium oxide or indium tin oxide containing titanium oxide, for example. Instead of indium tin oxide (ITO) described above, indium zinc oxide (IZO) or indium tin oxide (ITSO) containing silicon oxide, for example, may be used.
In the case of forming a reflective liquid crystal display device 50, a conductive film of titanium, tungsten, nickel, gold, platinum, silver, aluminum, magnesium, calcium, lithium, or an alloy containing at least one of these elements may be used as a reflective metal thin film, and this metal thin film may be used for the pixel electrodes 19a.
In the foregoing manner, the thin film transistor substrate 20 illustrated in
<Counter Substrate Formation Step>
First, the entire surface of the insulating substrate 10b such as a glass substrate is coated with, for example, a black-colored photosensitive resin by spin coating or slit coating, and then is exposed to light and developed, thereby forming the black matrix 21 with a thickness of about 1.0 nm, as illustrated in
Next, the entire substrate including the black matrix 21 is coated with a red-, green-, or blue-colored photosensitive resin by spin coating or slit coating, and then is exposed to light and developed, thereby forming a colored film 22 of a selected color (e.g., a red film) with a thickness of about 2.0 μm, as illustrated in
Then, a transparent conductive film such as an ITO film, for example, is deposited by sputtering over the substrate including the colored films 22, thereby forming a common electrode 23 with a thickness of about 50 nm-200 nm, as illustrated in
Lastly, the entire substrate including the common electrode 23 is coated with a photosensitive resin by spin coating or slit coating, and then is exposed to light and developed, thereby forming photospacers 24 each with a thickness of about 4 μm, as illustrated in
In the foregoing manner, the counter substrate 30 can be formed.
<Liquid Crystal Injection Step>
First, a resin film of polyimide is applied by printing onto the surfaces of the thin film transistor substrate 20 formed by the above-descried thin film transistor substrate formation step and the counter substrate 30 formed by the above-descried counter substrate formation step, and then, is subjected to calcination and rubbing, thereby forming an alignment film.
Next, a sealing material of, for example, an ultraviolet (UV)/thermosetting resin is printed in a frame shape on the surface of the counter substrate 30 on which the alignment film is formed, and then a liquid crystal material is dropped inside the frame of the sealing material.
Thereafter, the counter substrate 30 on which the liquid crystal material has been dropped and the thin film transistor substrate 20 on which the alignment film is formed are bonded together under a reduced pressure to form a bonded assembly. This bonded assembly is then exposed to the air under an atmospheric pressure, thereby pressurizing the front and back surfaces of the bonded assembly.
Subsequently, the sealing material enclosed in the bonded assembly is irradiated with UV light, and then the bonded assembly is heated, thereby curing the sealing material.
Lastly, the bonded assembly enclosing the cured sealing material is diced, for example, and unwanted portions thereof are removed.
In the foregoing manner, the liquid crystal display device 50 of the embodiment is fabricated.
The above embodiment may be modified in the following manner.
In the above embodiment, the connection layer 25 is provided in the contact hole Ca, and the drain electrode 16b and the pixel electrode 19a are electrically connected together through the connection layer 25, and the connection layer 38 is provided in the contact hole Cc, and the auxiliary capacitor line 11b and the line constituted by the first conductive layer 14a and the second conductive layer 15a are electrically connected together through the connection layer 38. However, the present invention is not limited to such configurations, and for example, the contact hole Cb described above can be applied.
For example, as well as the contact hole Cc described above, in the contact hole Cb, a connection layer made of indium gallium zinc oxide (IGZO) may be provided between the gate insulating layer 12 and the source line 16a, and a transparent conductive film contacting the relay line 11c and the connection layer may be provided on the surface of the contact hole Cb, and the relay line 11c and the source line 16a may be electrically connected together through the transparent conductive film and the connection layer.
In the above embodiment, indium gallium zinc oxide (IGZO) is used as an oxide semiconductor constituting the connection layers 25 and 38, and the first conductive layer 14b of the drain electrode 16b contacting the connection layers 25, and the first conductive layer 14a of the line formed by the first conductive layer 14a and the second conductive layer 15a contacting the connection layers 38 are made of titanium. Alternatively, another material except titanium can be used as a metal constituting the first conductive layer 14b of the drain electrode 16b and a metal constituting the first conductive layer 14a of the line formed by the first conductive layer 14a and the second conductive layer 15a as long as an oxide semiconductor constituting the connection layers 25 and 38 are reduced by the metal constituting the first conductive layer 14b of the drain electrode 16b and the metal constituting the first conductive layer 14a of the line formed by the first conductive layer 14a and the second conductive layer 15a to decrease the resistances of the connection layers 25 and 38 made of the oxide semiconductors.
More specifically, for example, if the material is a metal whose standard electrode potential is lower than that of titanium, when the material is in contact with indium gallium zinc oxide, the indium gallium zinc oxide can be reduced as well as the above-described titanium.
Specifically, the standard electrode potential of titanium is −1.63 V, and metals having a standard electrode potential lower than titanium includes, for example, aluminum (−1.676V), barium (−2.92V), beryllium (−1.847V), calcium (−2.84V), cesium (-2.923V), potassium (−2.925V), lithium (−3.045V), magnesium (−2.37V), sodium (Na: −2.714V), rubidium (−2.925), strontium (−2.89V), etc.
In this case, the drain electrode 16b (i.e., the first conductive layer 14b) made of a metal whose standard electrode potential is lower than that of titanium is formed on the connection layer 25, and the source line 16a (i.e., the first conductive layer 14a) made of a metal whose standard electrode potential is lower than that of titanium is formed on the connection layer 38.
In the above embodiment, the thin film transistor substrate 20 is fabricated by using the five photomasks, and alternatively, the thin film transistor substrate may be fabricated by performing the semiconductor layer and connection layer formation step and the source line and drain electrode formation step with one photomask, and using four photomasks in total.
In this case, initially, in the thin film transistor substrate formation step, as well as
Subsequently, as illustrated in
Next, a photoresist is formed over the entire substrate on which the titanium film 26 and the aluminum film 27 are formed, and the photoresist is patterned by half exposure with a second photomask to have a predetermined shape, thereby forming a photoresist 52, as illustrated in
In this case, as illustrated in
Next, as illustrated in
In the foregoing manner, the semiconductor layer and connection layer formation step, and the source line and drain electrode formation step are performed with one photomask.
Thereafter, remove of the photoresist 52 and cleaning are performed, and then, as well as
The present invention is applicable to a display device substrate using a semiconductor layer of an oxide semiconductor, a method for fabricating the substrate, and a display device, for example.
5
a Thin film transistor
10
a Insulating substrate
11
a Gate line
11
aa Gate electrode
11
b Auxiliary Capacitor Line (Line Formed by Gate Line Layer)
12 Gate insulating layer
13
a Oxide semiconductor layer
14
a First conductive layer
14
b First conductive layer
15
a Second conductive layer
15
b Second conductive layer
16
a Source line
16
aa Source electrode
16
b Drain electrode
17 Interlayer insulating film
18 Planarization film
19
a Pixel electrode
20 Thin film transistor substrate (display device substrate)
25 Connection layer
30 Counter substrate (another display device substrate)
38 Connection layer
40 Liquid crystal layer (display medium layer)
41 Transparent conductive film (conductive film)
50 Liquid crystal display device
C Channel region
Ca Contact hole
Cc Contact hole
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-183225 | Aug 2010 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2011/002634 | 5/11/2011 | WO | 00 | 3/1/2013 |
