Patent Grant
10878768
This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2018-0015742, filed on Feb. 8, 2018 in the Korean Intellectual Property Office (KIPO), the content of which is incorporated herein by reference in its entirety.
This disclosure relates generally to display devices, and more particularly to display devices supporting normal and variable frame rate modes and methods of operating the same.
A content frame rate is a frame rate at which a host processor such as a graphic processing unit (GPU) or a graphic card supplies image data to a display device. A display refresh rate (or just “refresh rate”) is a rate at which a display device screen is updated with image voltages. Recently developed display devices such as a liquid crystal displays (LCDs) or organic light emitting diode (OLED) devices operate in both a “normal mode” and a “variable frame mode”. In a normal mode, both the content frame rate and the refresh rate are constant from frame to frame and are synchronized. Here, the refresh rate may be the same as, or a multiple of, the content frame rate.
In rendering systems, however, the content frame rate, also called the rendering frame rate, may be variable from frame to frame. In particular, when the host processor provides the display device with frame data for a game image that requires complicated rendering, the host processor may use longer frame lengths (lower frame rates) for complex video segments that require more rendering time. If the rendering frame rate is variable and the display refresh rate is not, a mismatch may occur between the rendering frame rate and the display refresh rate. In systems that aren't configured to correct it, the mismatch may cause a tearing phenomenon where a boundary line appears in the display image.
To prevent the tearing phenomenon, a variable refresh rate mode (e.g., Free-Sync™, G-Sync™, etc.), i.e., the above-noted “variable frame mode”, has been developed. In this mode, the host processor provides frame data to the display device with a variable frame rate by changing blank period length from frame to frame. A display device supporting the variable frame mode may have a refresh rate equaling (or an integer multiple of) the content frame rate. Thus, a variable refresh rate is synchronized with the variable content frame rate, thereby preventing the tearing phenomenon.
In a display device supporting a normal mode of a constant frame rate and a variable frame mode of a variable frame rate, embodiments described herein may optimize power consumption according to the normal mode or the variable frame mode. Power consumption in output buffer amplifiers may be reduced in the normal mode by reducing bias current, thereby reducing a slew rate of data signals output to pixels, relative to the slew rate used in the variable frame mode.
According to example embodiments, a method of operating a display device involves detecting whether a frame mode of the display device is a normal mode in which image data are received with a constant frame rate or a variable frame mode in which the image data are received with a variable frame rate. An output buffer drivability of a data driver included in the display device may be set according to the detected frame mode, and an image is displayed by outputting data voltages corresponding to the image data with respective slew rates corresponding to the set output buffer drivability. Power consumption may be selectively reduced by setting lower output buffer drivability and lower slew rates in the normal mode.
In various example embodiments:
To set the output buffer drivability, an output buffer drivability register included in the data driver may be set to a first output buffer drivability level when the detected frame mode is the variable frame mode, and the output buffer drivability register included in the data driver may be set to a second output buffer drivability level lower than the first output buffer drivability level when the detected frame mode is the normal mode.
To display the image, the data voltage may be output with a first slew rate corresponding to the first output buffer drivability level when the detected frame mode is the variable frame mode, and the data voltages may be output with a second slew rate corresponding to the second output buffer drivability level when the detected frame mode is the normal mode. The second slew rate may be less than the first slew rate.
An active period of each frame in the normal mode may be longer than an active period of each frame in the variable frame mode.
One horizontal time in the normal mode may be longer than one horizontal time in the variable frame mode.
A polarity inversion type may be set according to the detected frame mode.
When the detected frame mode is the variable frame mode, the data voltages may be output alternatingly in a first polarity inversion type, and, when the detected frame mode is the normal mode, the data voltages may be output alternatingly in a second polarity inversion type different from the first polarity inversion type.
The first polarity inversion type may be one of a one-dot inversion type, a two-dot inversion type, a column inversion type, a row inversion type and a frame inversion type, and the second polarity inversion type may be another one of the one-dot inversion type, the two-dot inversion type, the column inversion type, the row inversion type and the frame inversion type.
A decision on whether to perform charge sharing may be set according to the detected frame mode.
When the detected frame mode is the variable frame mode, the charge sharing may not be performed, and, when the detected frame mode is the normal mode, the charge sharing may be performed.
According to example embodiments, there is provided a display device including a display panel including a plurality of pixels, a gate driver configured to provide a gate signal to the plurality of pixels, a data driver configured to provide data voltages to the plurality of pixels, and a timing controller configured to receive image data, and to control the gate driver and the data driver. The timing controller detects whether a frame mode of the display device is a normal mode in which image data are received with a constant frame rate or a variable frame mode in which the image data are received with a variable frame rate, and sets an output buffer drivability of the data driver according to the detected frame mode. The data driver outputs the data voltages corresponding to the image data with respective slew rates corresponding to the set output buffer drivability.
In example embodiments:
The timing controller may include a mode detector configured to detect whether the frame mode is the normal mode or the variable frame mode by measuring one horizontal time and a time of a blank period in at least one frame.
The data driver may include an output buffer drivability register. The timing controller may set the output buffer drivability register to a first output buffer drivability level when the detected frame mode is the variable frame mode, and may set the output buffer drivability register to a second output buffer drivability level lower than the first output buffer drivability level when the detected frame mode is the normal mode.
The data driver may further include a bias generator and output buffers. When the detected frame mode is the variable frame mode, the bias generator may provide the output buffers with a first bias current corresponding to the first output buffer drivability level, and the output buffers may output the data voltage with a first slew rate corresponding to the first bias current. When the detected frame mode is the normal mode, the bias generator may provide the output buffers with a second bias current corresponding to the second output buffer drivability level, and the output buffers may output the data voltage with a second slew rate corresponding to the second bias current. The second slew rate may be less than the first slew rate.
One horizontal time in the normal mode may be longer than one horizontal time in the variable frame mode.
The timing controller may set a polarity inversion type according to the detected frame mode.
The data driver may include a polarity inversion type register. When the detected frame mode is the variable frame mode, the timing controller may set the polarity inversion type register to a value indicating a first polarity inversion type, and the data driver may output the data voltage in the first polarity inversion type based on the value of the polarity inversion type register. When the detected frame mode is the normal mode, the timing controller may set the polarity inversion type register to a value indicating a second polarity inversion type different from the first polarity inversion type, and the data driver may output the data voltage in the second polarity inversion type based on the value of the polarity inversion type register.
The first polarity inversion type may be one of a one-dot inversion type, a two-dot inversion type, a column inversion type, a row inversion type and a frame inversion type, and the second polarity inversion type may be another one of the one-dot inversion type, the two-dot inversion type, the column inversion type, the row inversion type and the frame inversion type.
The timing controller may set whether to perform charge sharing according to the detected frame mode.
The data driver may include a charge sharing register. When the detected frame mode is the variable frame mode, the timing controller may set the charge sharing register to a value indicating that the charge sharing is not performed, and the data driver may not perform the charge sharing based on the value of the charge sharing register. When the detected frame mode is the normal mode, the timing controller may set the charge sharing register to a value indicating that the charge sharing is performed, and the data driver may perform the charge sharing based on the value of the charge sharing register.
As summarized above, the method of operating the display device and the display device according to example embodiments may set an output buffer drivability according to whether a frame mode of the display device is a normal mode in which image data are received with a constant frame rate or a variable frame mode in which the image data are received with a variable frame rate, thereby reducing power consumption in at least one selected one of different frame modes.
Further, the method of operating the display device and the display device according to example embodiments may set a polarity inversion type and/or charge sharing according to the frame mode of the display device, thereby further reducing power consumption in at least one selected one of different frame modes.
In another example embodiment, a display device includes: a display panel including a plurality of pixels; a gate driver configured to provide a gate signal to the plurality of pixels; a data driver; and a timing controller. The timing controller is configured to receive image data, control the gate driver and the data driver, and detect at least one of a frame rate mode or a frame rate of the image data. The data driver includes a plurality of output buffer amplifiers that provide data voltages to the plurality of pixels. The output buffer amplifiers are supplied with a varying bias signal to control power consumption thereof based on at least one of the frame rate mode or the frame rate.
The timing controller may detect the frame rate mode by detecting whether the image data is being supplied according to a constant frame rate or a variable frame rate. A level of the bias signal may be set to a first level when the variable frame rate is detected, and to a second level when the constant frame rate is detected, where the second level is lower than the first level. The bias signal may be a bias current.
Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which like reference characters denote like elements or functions, wherein:
Hereinafter, embodiments of the present inventive concept will be explained in detail with reference to the accompanying drawings.
The display panel 110 may include a plurality of gate lines GL1 to GLm, a plurality of data lines DL1, DL2 . . . DLn, and the plurality of pixels PX coupled to the plurality of gate lines GL1 to GLm and the plurality of data lines DL1 to DLn. As illustrated in
The gate driver 120 may generate the gate signal based on a gate control signal CTRL1 from the timing controller 170, and may sequentially apply the gate signal to the plurality of gate lines GL1 to GLm. Gate control signal CTRL1 may include, but is not limited to, a gate clock signal and a scan start pulse. The gate driver 120 may be mounted directly on the display panel 110, coupled to the display panel 110 in a form of a tape carrier package (TCP), or may be integrated in a peripheral portion of the display panel 110.
The data driver 130 may generate the data voltages VD based on image data ODAT and a data control signal CTRL2 output from the timing controller 170, and may apply the data voltages VD to the plurality of data lines DL1 to DLn. The data control signal CTRL2 may include a horizontal start signal and a load signal. Data driver 130 may be mounted directly on the display panel 110, coupled to the display panel 110 in a form of a TCP, or may be integrated in the peripheral portion of the display panel 110.
The timing controller 170 may receive image data IDAT and a control signal CTRL from an external host processor (e.g., a graphic processing unit (GPU)). The image data IDAT may be RGB data including red image data, green image data and blue image data. Control signal CTRL may include a data enable signal DE and a pixel clock signal CLK. The timing controller 170 may generate the gate control signal CTRL1, the data control signal CTRL2 and the image data ODAT based on the control signal CTRL and the image data IDAT. The timing controller 170 may control an operation of the gate driver 120 by providing the gate control signal CTRL1 to the gate driver 120, and may control an operation of the data driver 130 by providing the data control signal CTRL2 and the image data ODAT to the data driver 130.
The host processor (e.g., the GPU) may provide the image data IDAT with a constant frame rate from frame to frame to the display device 100 in a normal mode, and may provide the image data IDAT with a variable frame rate to the display device 100 in a variable frame mode. For example, the host processor may change the frame rate from frame to frame by allowing a length of a blank period to change in each frame in the variable frame mode. The timing controller 170 may detect whether a frame mode of the display device 100 should be set to the normal mode or the variable frame mode. To this end, the timing controller 170 may include a mode detector 180 which detects whether the frame mode of the host processor is the normal mode or the variable frame mode.
A time between successive falling edges or between successive rising edges of the DE signal may be referred to as a “one horizontal” or “1H” time, which corresponds to a time during which one horizontal row of pixels is refreshed with data voltages VD. In an example, mode detector 180 may detect whether the frame mode is the normal mode or the variable frame mode by measuring the 1H time and a time of a blank period in at least one frame based on the pixel clock signal CLK provided from the host processor and/or an oscillator clock signal generated by an internal oscillator of the timing controller 170. For example, the mode detector 180 may decide that the frame mode is the normal mode when the 1H time is relatively long and the time of the blank period is constant from frame to frame, and may decide that the frame mode is the variable frame mode when the 1H time is relatively short and the time of the blank period is variable. In another example, the image data IDAT may be provided to timing controller 170 with a field indicating whether the frame mode is normal or variable, where the field may also indicate the content frame rate. Mode detector 180 may detect the mode from the information in this field.
The data driver 130 may include output buffers 160, e.g., a bank of output buffer amplifiers BA1 to Ban connected to data lines DL1 to DLn, respectively. To drive a pixel PX with an updated data voltage of a new frame, or to refresh a pixel PX with a previous data voltage of a current frame, each output buffer amplifier BA1 to BAn may output a data voltage signal VD in a pulsed waveform. A leading edge of the pulsed waveform may be characterized in terms of a slew rate, that is, a change in its voltage vs. time. For example, referring momentarily to
As shown in
Herein, the term “output buffer drivability” refers to a characteristic of an output buffer amplifier to drive a pixel PX with a pulsed data voltage in a manner positively correlated with slew rate. Thus, an output buffer amplifier BAi or the output buffers 160 (i.e., the bank of buffer amplifiers BA to Ban, collectively) may be said to have a relatively high or low output buffer drivability if the data voltage(s) output thereby has a relatively fast or slow slew rate, respectively. A given configuration for output buffers 160 may exhibit a high or low output buffer drivability when driven with a high or low bias current IB, respectively, causing power consumption in the output buffers to be respectively high or low.
The timing controller 170 may set an output buffer drivability of the data driver 130 according to the detected frame mode, and the data driver may output the data voltage VD corresponding to the image data ODAT with a slew rate corresponding to the set output buffer drivability. As just explained, slew rate may be defined as an absolute value of the slope of the data voltage VD waveform's leading edge. It should be noted, however, that the peak value of the data voltage VD (the flat area of the VD waveforms in
Data driver 130 may further include an output buffer drivability register 140 that stores a current output buffer drivability level. Timing controller 170 may set the output buffer drivability register 140 to a first output buffer drivability level when the frame mode detected by the mode detector 180 is the variable frame mode, and may set the output buffer drivability register 140 to a second output buffer drivability level lower than the first output buffer drivability level when the frame mode detected by the mode detector 180 is the normal mode. For example, the output buffer drivability register 140 may store 3-bit data, and the timing controller 170 may write data of “HHH” indicating the first output buffer drivability level to the output buffer drivability register 140 when the detected frame mode is the variable frame mode, and may write data of “HLL” indicating the second output buffer drivability level to the output buffer drivability register 140 when the detected frame mode is the normal mode. In other examples, n-bit data is used, where n is less than or higher than three.
To output the data voltages VD with a slew rate corresponding to the output buffer drivability level set to the output buffer drivability register 140, the data driver may further include the bias generator 150 which generates the bias current B. The bias current IB may correspond to the output buffer drivability level set to the output buffer drivability register 140. The output buffers 160 output the data voltages VD based on the bias current B. For example, when the detected frame mode is the variable frame mode, the bias generator 150 may provide the output buffers 160 with a first bias current corresponding to the first output buffer drivability level, and the output buffers 160 may output the data voltages VD with a first slew rate corresponding to the first bias current. Further, when the detected frame mode is the normal mode, the bias generator 150 may provide the output buffers 160 with a second bias current corresponding to the second output buffer drivability level, and the output buffers 160 may output the data voltages VD with a second slew rate corresponding to the second bias current. In this case, the second slew rate may be less than the first slew rate. Accordingly, power consumption in the normal mode may be reduced relative to the case in which the data voltages VD would have otherwise been output with the first slew rate in the normal mode.
In a conventional display device, although the 1H time in the normal mode is longer than the 1H time in the variable frame mode, a data driver of the conventional display device may output data voltages with a fixed slew rate suitable for the 1H time corresponding to the highest frame rate supported by the conventional display device, or for the shorted 1H a time independent of the frame mode. For example, the 1H time interval in the normal mode having a constant frame rate of about 60 Hz is about 14.8 μs. In this case, the data driver of the conventional display device may output the data voltages with a fast slew rate that is capable of charging pixels within a much shorter 1H time interval. In particular, a conventional display device may use a 1H time interval of about 6.2 μs for the variable frame mode having a variable frame rate ranging from about 25 Hz to about 144 Hz, and sets the slew rate of the normal mode the same as that in the variable frame mode.
However, the display device 100 according to example embodiments may detect whether the frame mode is the normal mode or the variable frame mode, and may set the output buffer drivability of the data driver 130 according to the detected frame mode. Thus, the data driver 130 may output the data voltages VD with relatively high output buffer drivability, coinciding to a higher slew rate in the variable frame mode, and may output the data voltages VD with relatively low output buffer drivability coinciding with a lower slew rate in the normal mode. Accordingly, the display device 100 according to example embodiments may operate with an output buffer drivability suitable for each of different frame modes, thereby minimizing the power consumption in the different frame modes and, in particular, reducing the power consumption in the normal mode.
Referring collectively to
For example, as indicated by signal sequence 310 in
However, as indicated by signal sequence 330 in
A length of the active period AP1, AP2 and AP3 in the variable frame mode may be set suitable for the maximum frame rate within the range of the variable frame rate, for example a frame rate of about 144 Hz. Accordingly, the active period AP in the normal mode which is set suitable for the constant frame rate, for example the frame rate of about 60 Hz, may be longer than the active period AP1, AP2 and AP3 in the variable frame mode. Thus, the 1H time of the normal mode may be longer than the 1H time of the variable frame mode. (Note that each vertical “rectangle” in the AP sections of the signal diagrams illustrates a time during which a single horizontal row of pixels receives data. Thus,
The timing controller 170 may set an output buffer drivability of a data driver 130 according to the frame mode detected by the mode detector 180 (S220). Timing controller 170 may set an output buffer drivability register 140 to a first output buffer drivability level when the detected frame mode is the variable frame mode, and may set the output buffer drivability register 140 to a second output buffer drivability level lower than the first output buffer drivability level when the detected frame mode is the normal mode.
To display an image, the data driver 130 may output data voltages VD corresponding to the image data ODAT with a slew rate corresponding to the output buffer drivability set to the output buffer drivability register 140 (S230). Data driver 130 may output the data voltages VD with a first slew rate corresponding to the first output buffer drivability level when the detected frame mode is the variable frame mode, and may output the data voltages VD with a second slew rate corresponding to the second output buffer drivability level when the detected frame mode is the normal mode. The second slew rate may be less than the first slew rate.
For example, as indicated by signal sequence 370 in
Compared with a method 200 illustrated in
If the detected frame mode is the variable frame mode (S410 result: VARIABLE FRAME MODE), the timing controller may set an output buffer drivability register 140 of data driver 130 to a first output buffer drivability level (S420), and may set a polarity inversion type register of the data driver to a value indicating a first polarity inversion type (S430). The data driver may output data voltages with a first slew rate corresponding to the first output buffer drivability level and alternating in the first polarity inversion type to display an image (S450). The first polarity inversion type may be one of a one-dot inversion type, a two-dot inversion type, a column inversion type, a row inversion type and a frame inversion type. For example, as illustrated in
If the detected frame mode is the normal mode (S410: NORMAL MODE), the timing controller may set the output buffer drivability register to a second output buffer drivability lower than the first output buffer drivability level (S460), and may set the polarity inversion type register to a value indicating a second polarity inversion type different from the first polarity inversion type (S470). The data driver may output the data voltages with a second slew rate less than the first slew rate and corresponding to the second output buffer drivability level and in the second polarity inversion type different from the first polarity inversion type to display an image (S490). In some example embodiments, the second polarity inversion type is another one of the one-dot inversion type, the two-dot inversion type, the column inversion type, the row inversion type and the frame inversion type. For example, as illustrated in
In method 800, a mode detector of a timing controller may detect whether a frame mode of the display device is a normal mode in which image data are received with a constant frame rate or a variable frame mode in which the image data are received with a variable frame rate (S410).
If the detected frame mode is the variable frame mode (S410: VARIABLE FRAME MODE), the timing controller may set an output buffer drivability register of a data driver to a first output buffer drivability level (S420), and may set a charge sharing register of the data driver to a first value indicating that the charge sharing is not performed (S440). The data driver may not perform the charge sharing, and may output a data voltage with a first slew rate corresponding to the first output buffer drivability level to display an image (S450a).
If the detected frame mode is the normal mode (S410: NORMAL MODE), the timing controller may set the output buffer drivability register to a second output buffer drivability lower than the first output buffer drivability level (S460), and may set the charge sharing register to a second value indicating that the charge sharing is performed (S480). The data driver may perform the charge sharing, and may output the data voltage with a second slew rate less than the first slew rate and corresponding to the second output buffer drivability level to display an image (S490a). For example, to perform the charge sharing, the data driver may precharge data lines by connecting the data lines to each other before the data voltage is output. Accordingly, current supplying loads of output buffers of the data driver may be reduced, and the power consumption in the normal mode may be further reduced.
The timing controller 170 may detect whether a frame mode of the display device 100a is a normal frame mode or a variable frame mode, and may set a polarity inversion type according to the detected frame mode. Timing controller 170 may set the polarity inversion type register 142 to a first value indicating a first polarity inversion type when the detected frame mode is the variable frame mode, and may set the polarity inversion type register 142 to a second value indicating a second polarity inversion type different from the first polarity inversion type when the detected frame mode is the normal mode. The data driver 130a may output data voltages VD in the first polarity inversion type based on the first value set to the polarity inversion type register 142 when the detected frame mode is the variable frame mode, and may output the data voltages VD in the second polarity inversion type based on the second value set to the polarity inversion type register 142 when the detected frame mode is the normal mode. The first polarity inversion type may be one of a one-dot inversion type, a two-dot inversion type, a column inversion type, a row inversion type and a frame inversion type, and the second polarity inversion type may be another one of the one-dot inversion type, the two-dot inversion type, the column inversion type, the row inversion type and the frame inversion type.
The timing controller 170 may set whether to perform charge sharing according to the detected frame mode. Timing controller 170 may set the charge sharing register 144 to a first value indicating that the charge sharing is not performed when the detected frame mode is the variable frame mode, and may set the charge sharing register 144 to a second value indicating that the charge sharing is performed when the detected frame mode is the normal mode. The data driver 130a may not perform the charge sharing based on the first value set to the charge sharing register 144 when the detected frame mode is the variable frame mode, and may perform the charge sharing based on the second value set to the charge sharing register 144 when the detected frame mode is the normal mode.
In method 1000, mode detector 180 may detect whether a frame mode of the display device is a normal mode in which image data are received with a constant frame rate or a variable frame mode in which the image data are received with a variable frame rate (S410).
If the detected frame mode is the variable frame mode (S410 result: VARIABLE FRAME MODE), the timing controller may set an output buffer drivability register of a data driver to a first output buffer drivability level (S420), may set a polarity inversion type register of the data driver to a value indicating a first polarity inversion type (S430), and may set a charge sharing register of the data driver to a first value indicating that the charge sharing is not performed (S440). The data driver may not perform the charge sharing, and may output a data voltage with a first slew rate corresponding to the first output buffer drivability level and in the first polarity inversion type to display an image (S450b).
If the detected frame mode is the normal mode (S410: NORMAL MODE), the timing controller may set the output buffer drivability register to a second output buffer drivability lower than the first output buffer drivability level (S460), may set the polarity inversion type register to a value indicating a second polarity inversion type different from the first polarity inversion type (S470), and may set the charge sharing register to a second value indicating that the charge sharing is performed (S480). The data driver may perform the charge sharing, and may output the data voltage with a second slew rate less than the first slew rate and corresponding to the second output buffer drivability level and in the second polarity inversion type different from the first polarity inversion type to display an image (S490b).
The inventive concepts may be applied to any display device supporting the normal mode and the variable frame mode, and any electronic device including the display device. For example, the inventive concepts may be applied to a television (TV), a digital TV, a 3D TV, a smart phone, a wearable electronic device, a tablet computer, a mobile phone, a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.
In the above-described example embodiments, the normal mode is selected as a mode in which bias current of output buffer amplifiers is reduced to thereby lower power consumption while slew rates are reduced. In other embodiments, other criteria may be used to select when to lower bias current. For instance, the inventive concept may be applied to reduce power consumption while operating within a variable frame rate mode during times in which frame rates are below a threshold. Accordingly, alternative embodiments may use a “look ahead” approach in which the host processor determines, during a variable frame rate mode, whether a predetermined number of frames to be rendered will be supplied at a frame rate below a threshold. If so, the host processor provides an indication of such to the timing controller 170, and the display device 100 responds by initiating a “bias reduction mode” for the output buffer amplifiers, in which bias current IB is reduced. Concurrently in this bias reduction mode, the timing controller may cause the AP times and 1H times to be temporarily lengthened just for those frames to be displayed below the threshold frame rate. Then, the slew rate reduction technique as described above for the normal mode, which stems from the reduction in bias current IB, may be similarly used in the variable mode to reduce power consumption as these frames are displayed below the threshold frame rate.
Any one of the above-described elements for manipulating, generating and/or processing data and signals, such as any of the above-described timing controller, mode detector, data driver, gate driver, output buffer drivability register, polarity inversion type register, charge sharing register and bias generator may include electronic circuitry such as a special purpose hardware circuit or processor or a general purpose processor that executes instructions read from a memory to run a routine to carry out the element's function. Various ones of the above described elements may be embodied as part of the same processor, which executes instructions at different stages to carry out the functions of the components sequentially, or using parallel processing. With the use of parallel processing, various ones of the components may be embodied as respective processing elements of a parallel processor. Alternatively, the various elements may be embodied as part of a plurality of different processors. For example, with such a composition based on hardware circuitry, the above-discussed timing controller, mode detector, data driver, gate driver, output buffer drivability register, polarity inversion type register, charge sharing register and bias generator may alternatively be called, respectively, a timing controller circuit, mode detector circuit, data driver circuit, gate driver circuit, output buffer drivability register circuit, polarity inversion type register circuit, charge sharing register circuit and bias generator circuit, circuitry, hardware, or the like.
The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the appended claims.
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| 10-2018-0015742 | Feb 2018 | KR | national |
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| 20190244579 A1 | Aug 2019 | US |
