Patent Application
20140362073
This application claims the priority to Chinese Patent Application No. 201310223124.1, filed on Jun. 6, 2013, in the State Intellectual Property Office of P.R. China, which is hereby incorporated herein in its entirety by reference.
The present invention relates generally to display technology, and more particularly to a display device, a timing controller, and an image displaying method.
Currently, video data may be processed in a progressive video format or an interlaced video format. Conventionally, a display screen mostly uses the progressive scanning manner. In some cases, an interlaced-to-progressive format converter needs to be disposed at a front end of display processing such that the display screen is compatible to the interlaced format signal. The format converter may be disposed in a timing control circuit of the display screen, or may be disposed in a motherboard circuit of a display device. However, the conventional interlaced and progressive format converter generally requires a data storage unit for buffering the received data signal. The data storage unit is generally formed by a storage and hardware parts of a periphery auxiliary circuit, which cannot be removed from the display device to save space and cost. In other words, the required storage and hardware parts of the periphery auxiliary circuit occupy certain space in the display device and increase the cost of the display device.
Therefore, a heretofore unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies.
In view of the defects in the prior art, the present invention provides a novel interlaced scanning drive technology, which can implement interlaced scanning display when an interlaced-format signal is received, thereby saving a storage and a periphery auxiliary circuit equipped in a format converter in the prior art.
In one aspect, the present invention provides a display device, which includes: a liquid crystal panel; a gate drive circuit, for providing the liquid crystal panel with a gate drive signal, and a data drive circuit, for providing the liquid crystal panel with a data drive signal; and a timing controller, for receiving an input signal comprising an odd-field signal and an even-field signal, providing the data drive circuit with a data control signal and a data signal, and providing the gate drive circuit with a gate control signal including an output enable (OE) signal and a gate scanning clock (GCK) signal, where in a data signal period in one line, the GCK signal includes two clock pulses, and the OE signal includes one pulse signal. In scanning the odd field, at a time period corresponding to a first clock pulse in the two clock pulses, the gate drive circuit outputs a high potential gate drive signal to drive an odd-line gate bus, and at a time period corresponding to a second clock pulse in the two clock pulses, the gate drive circuit outputs a low potential gate drive signal to drive an even-line gate bus; and in scanning the even field, at a time period corresponding to a first clock pulse in the two clock pulses, the gate drive circuit outputs a low potential gate drive signal to drive an odd-line gate bus, and at a time period corresponding to a second clock pulse in the two clock pulses, the gate drive circuit outputs a high potential gate drive signal to drive an even-line gate bus.
In this technical solution, in receiving an odd-field image, in a data period in each line, the GCK signal generated by the timing controller includes two clock pulses. When the gate drive circuit scans the odd-line gate bus, at a time period corresponding to a first clock pulse in the two clock pulses, a high potential gate drive signal is output and an odd-line gate bus is turned on; when the gate drive circuit scans the even-line gate bus, at a time period corresponding to a second clock pulse, a low potential gate drive signal is output and an even-line gate bus is turned off. In this way, the data drive circuit can write a line of data in an odd line, so as to refresh the odd-line image on the display screen by receiving the odd-field image. In receiving an even-field image, when the gate drive circuit scans the odd-line gate bus, at the time period corresponding to the first clock pulse in the two clock pulses, a low potential gate drive signal is output and an odd-line gate bus is turned off; when the gate drive circuit scans the even-line gate bus, at the time period corresponding to the second clock pulse, a high potential gate drive signal is output, and an even-line gate bus is turned on. In this way, the data drive circuit can write a line of data in an even line, so as to refresh the even-line image on the display screen by receiving the even-field image. In receiving an interlaced image signal, an interlaced image is scanned and displayed on the display screen, which can save a storage and a periphery auxiliary circuit equipped in a converter.
In another aspect, the present invention provides a display device, which includes: a liquid crystal panel; a gate drive circuit, for providing the liquid crystal panel with a gate drive signal, and a data drive circuit, for providing the liquid crystal panel with a data drive signal; and an interlaced and progressive format determination unit, for outputting a first control signal when judging that an input signal is an interlaced image signal including an odd-field signal and an even-field signal, and outputting a second control signal when judging that the input signal is a progressive image signal; and a timing controller, for receiving the input signal, providing the data drive circuit with a data control signal and a data signal, and providing the gate drive circuit with a gate control signal including an OE signal and a GCK signal; where when receiving the first control signal, in a data signal period in one line, the timing controller generates the GCK signal including two clock pulses and generates the OE signal including one pulse signal; in scanning the odd field, at a time period corresponding to a first clock pulse in the two clock pulses, the gate drive circuit outputs a high potential gate drive signal to drive an odd-line gate bus, and at a time period corresponding to a second clock pulse in the two clock pulses, outputs a low potential gate drive signal to drive an even-line gate bus; in scanning the even field, at a time period corresponding to the first clock pulse in the two clock pulses, the gate drive circuit outputs a low potential gate drive signal to drive an odd-line gate bus, and at a time period corresponding to the second clock pulse in the two clock pulses, outputs a high potential gate drive signal to drive an even-line gate bus; and when receiving the second control signal, in the data signal period in one line, the timing processing unit outputs the GCK signal including one clock pulse and a first-potential OE signal.
In this technical solution, in one aspect, in receiving an interlaced image signal, when an odd-field image is scanned, and in a data period in each line, the GCK signal generated by the timing controller includes two clock pulses. When the gate drive circuit scans the odd-line gate bus, at a time period corresponding to a first clock pulse in the two clock pulses, a high potential gate drive signal is output and an odd-line gate bus is turned on; when the gate drive circuit scans the even-line gate bus, at a time period corresponding to a second clock pulse, a low potential gate drive signal is output and an even-line gate bus is turned off. In this way, the data drive circuit can write a line of data into an odd line, so as to refresh the odd-line image on the display screen by receiving the odd-field image. In receiving an even-field image, when the gate drive circuit scans the odd-line gate bus, at the time period corresponding to the first clock pulse in the two clock pulses, a low potential gate drive signal is output and an odd-line gate bus is turned off; when the gate drive circuit scans the even-line gate bus, at the time period corresponding to the second clock pulse, a high potential gate drive signal is output, and an even-line gate bus is turned on. In this way, the data drive circuit can write a line of data into an even line, so as to refresh the even-line image on the display screen by receiving the even-field image. In another aspect, in receiving a progressive image, the timing controller outputs a GCK signal and a first-potential OE signal in a data period in one line. In this way, the gate drive circuit outputs a corresponding a gate drive signal at a time period corresponding to each GCK signal, and outputs a high potential gate drive signal at a time period corresponding to each GCK signal to turn on a gate bus in each line. In this way, the data drive circuit can correspondingly write data into each line, so as to refresh the image progressively on the display screen by receiving a progressive image. Therefore, this technical solution can implement a compatible interlaced scanning manner and a progressive scanning manner.
In still another aspect, the present invention provides an image display method, applied to a display device driven by a gate drive signal and a data drive signal, where steps of the method include: S200: a timing controller receiving an input signal comprising an odd-field signal and an even-field signal; S400: generating a gate control signal, a data control signal, and a data signal, where the gate control signal includes an OE signal and a GCK signal, in a data signal period in one line, the GCK signal includes two clock pulses, and the OE signal includes one pulse signal; and S600: a gate drive circuit processing the OE signal and the GCK signal, to generate the gate drive signal; where if in scanning an odd field, in the gate drive signal for scanning an odd-line gate bus, the potential is high at a time period corresponding to a first clock pulse in the two clock pulses, an odd-line gate bus is turned on, and a line of data drive signals are written in; if in the gate drive signal for scanning an even-line gate bus, the potential is low at a time period corresponding to a second clock pulse in the two clock pulses, an even-line gate bus is turned off; and if in scanning an even field, in the gate drive signal for scanning an odd-line gate bus, the potential is low at a time period corresponding to a first clock pulse in the two clock pulses, an odd-line gate bus is turned off; if in the gate drive signal for scanning an even-line gate bus, the potential is low at a time period corresponding to a second clock pulse in the two clock pulses, an even-line gate bus is turned on, and a line of data drive signals are written in.
In this technical solution, in receiving an odd-field image, in a data period in one line, the GCK signal generated by the timing controller includes two clock pulses. When the gate drive circuit scans the odd-line gate bus, at a time period corresponding to a first clock pulse in the two clock pulses, a high potential gate drive signal is output and an odd-line gate bus is turned on; when the gate drive circuit scans the even-line gate bus, at a time period corresponding to a second clock pulse, a low potential gate drive signal is output and an even-line gate bus is turned off; the data drive circuit writes a line of data into the odd line, so as to refresh the odd-line image on the display screen by receiving the odd-field image. In receiving an even-field image, when the gate drive circuit scans the odd-line gate bus, at the time period corresponding to the first clock pulse in the two clock pulses, a low potential gate drive signal is output and an odd-line gate bus is turned off; when the gate drive circuit scans the even-line gate bus, at the time period corresponding to the second clock pulse, a high potential gate drive signal is output, and an even-line gate bus is turned on; the data drive circuit writes a line of data into the even line, so as to refresh the even-line image on the display screen by receiving the even-field image. In receiving an interlaced image signal, an interlaced image is scanned and displayed on the display screen, which can save a storage and a periphery auxiliary circuit equipped in a converter.
These and other aspects of the invention will become apparent from the following description of the preferred embodiment taken in conjunction with the following drawings, although variations and modifications therein may be effected without departing from the spirit and scope of the novel concepts of the invention.
The accompanying drawings illustrate one or more embodiments of the disclosure and together with the written description, serve to explain the principles of the disclosure. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like elements of an embodiment.
The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.
The terms used in this specification generally have their ordinary meanings in the art, within the context of the invention, and in the specific context where each term is used. Certain terms that are configured to describe the invention are discussed below, or elsewhere in the specification, to provide additional guidance to the practitioner regarding the description of the invention. For convenience, certain terms may be highlighted, for example using italics and/or quotation marks. The use of highlighting has no influence on the scope and meaning of a term; the scope and meaning of a term is the same, in the same context, whether or not it is highlighted. It will be appreciated that same thing can be said in more than one way. Consequently, alternative language and synonyms may be used for any one or more of the terms discussed herein, nor is any special significance to be placed upon whether or not a term is elaborated or discussed herein. Synonyms for certain terms are provided. A recital of one or more synonyms does not exclude the use of other synonyms. The use of examples anywhere in this specification including examples of any terms discussed herein is illustrative only, and in no way limits the scope and meaning of the invention or of any exemplified term. Likewise, the invention is not limited to various embodiments given in this specification.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only configured to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including” or “has” and/or “having” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the invention, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, “around”, “about” or “approximately” shall generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around”, “about” or “approximately” can be inferred if not expressly stated.
As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to.
As used herein, the term “unit”, “module” or “submodule” may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC); an electronic circuit; a combinational logic circuit; a field programmable gate array (FPGA); a processor (shared, dedicated, or group) that executes code; other suitable hardware components that provide the described functionality; or a combination of some or all of the above, such as in a system-on-chip. The term unit, module or submodule may include memory (shared, dedicated, or group) that stores code executed by the processor.
The description will be made as to the embodiments of the invention in conjunction with the accompanying drawings in
In certain embodiments, however, as discussed above, to use the interlaced and progressive format converter as shown in
The timing controller 40 receives video data input signals obtained after a motherboard or a system on a chip (SOC) decodes a video signal, where the video data input signal includes an image signal (RGB), a data enable (DE) signal, a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a clock signal. The timing controller 40 generates a data control signal and a data signal (DV) by using one part of the video data input signals, and outputs the data control signal and the data signal to the data drive circuit 20, where the data control signal includes a source start pulse (SSP) signal, a source clock (SCK) signal, a latch signal (LS), and a signal output enable (SOE). Furthermore, the timing controller 40 generates a gate control signal by using the other part of the video data input signals, and outputs the gate control signal to the gate drive circuit 30, where the gate control signal includes a gate start pulse (GSP) signal, an output enable (OE) signal, and a gate scanning clock (GCK) signal.
The display panel 10 has a pixel circuit. The pixel circuit includes multiple (specifically, m lines of) source data buses (i.e., video signal lines) SL1˜SLm and multiple (specifically, n lines of) gate buses (i.e., line scanning signal lines) GL1˜GLn. Multiple (mxn) pixel constitution portions are disposed at intersections of the source data buses SL1˜SLm and the gate buses GL1˜GLn, and the pixel constitution portions are disposed in a matrix shape to form a pixel array. Each pixel constitution portion includes a thin film transistor 101, and the (ixj)th thin film transistor 101 is provided on an intersection of a gate terminal, the i-th bus in the gate buses GL1˜GLn, and the j-th bus in the source data buses SL1˜SLm. The gate terminal of the thin film transistor 101 is connected to the i-th bus in the gate buses GL1˜GLn, and a source data terminal of the thin film transistor 101 is connected to the j-th bus in the source data buses SL1˜SLm. The i-th bus in the gate buses GL1˜GLn provides a turn-on signal to the thin film transistor 101, and the j-th bus in the source data buses SL1˜SLm provides a data signal to the thin film transistor 101. A pixel electrode is connected to a drain terminal of the thin film transistor 101.
The data drive circuit 20 receives the data signal (DV), the SSP signal, the SCK signal, the latch signal (LS), and the SOE signal output by the timing controller 40, and outputs these signals to the source data buses SL1˜SLm to apply a data drive signal D(1)˜D(m), so as to display an image on the liquid crystal panel 10 by driving an image signal.
The gate drive circuit 30 receives the GSP signal, the OE signal, and the GCK signal output by the timing controller 40, and outputs these signals to sequentially drive, in a vertical direction, gate drive signals GOUT(1)˜GOUT(n) of the gate buses GL1˜GLn, so as to sequentially turn on each gate bus on the liquid crystal panel 10.
The interlaced and progressive format determination unit is configured to determine an input signal as a progressive image signal or an interlaced image signal including an odd-field signal and an even-field signal, to output a first control signal when the input signal is determined as the interlaced image signal, and to output a second control signal when the input signal is determined as the progressive image signal.
Specifically, the odd-field signal is an image signal including odd-line image data, the even-field signal is an image signal including even-line image data, and a frame of image in an interlaced image signal is formed by the odd-field signal and the even-field signal.
In certain embodiments, the interlaced and progressive format determination unit may be integrated in a timing control chip, or may be provided on a circuit board of a timing controller. In certain embodiments, the interlaced and progressive format determination unit may be further integrated in a master chip or on a motherboard. In certain embodiments, the interlaced and progressive format determination unit outputs a first control signal or a second control signal to the timing controller 40.
When the timing controller 40 receives the first control signal, the timing controller 40 enters an interlaced processing mode. In the interlaced processing mode, the timing controller 40 outputs, in a period of the data signal in one line, the GCK signal including two clock pulses, which includes a first clock pulse and a second clock pulse, and the OE signal including one pulse signal. In scanning the odd field, the pulse signal counteracts the second clock pulse of the two clock pulses of the GCK signal. In scanning the even field, the pulse signal counteracts the first clock pulse of the two clock pulses of the GCK signal.
When the timing controller 40 receives the second control signal, the timing controller 40 enters a progressive processing mode. In the progressive processing mode, the timing controller 40 outputs, in a period of the data signal in one line, the GCK signal including a single clock pulse, and the OE signal having a first potential.
The receiving unit 41 may receive a video data LVDS input signal including the image signal (RGB), the DE signal, the horizontal synchronization signal (Hsync), the vertical synchronization signal, and the clock signal, where the motherboard may also output a signal in another data format. One of ordinary skill in the art may learn that, according to the coordination requirement of the motherboard and the timing controller, the signals may be in any data format proper for the timing controller, and the data format applied is not intended to limit the present invention.
The image data processing unit 42 is configured to perform data processing to the received signal, which includes at least the image signal (RGB), and to provide to a data drive circuit the data signal (DV) in a data format proper for displaying of the pixels of the display panel 10. In a data signal period in one line, the image data processing unit 42 correspondingly outputs a line of image data signals. For example, when a pixel matrix of the display panel 10 is 1920*1080, 1920 units of pixel data are generated for each line, and each unit of the pixel data includes three pixel constitution units R, G, and B. The data output 44 is configured to output the generated data signal to the data drive circuit 20.
The timing processing unit 43 is configured to receive the horizontal synchronization signal (Hsync), the vertical synchronization signal (Vsync), and the clock signal, to perform timing processing to generate control signals, and to output the control signals to the gate drive circuit 30 and the data drive circuit 20. In certain embodiments, the timing processing unit 43 provides to the gate drive circuit 30 a gate control signal, which includes the OE signal, the GCK signal, and the GSP signal, and provides to the data drive circuit 20 a data control signal, which includes the SSP signal, the SCK signal, the latch signal (LS), and the SOE signal. In certain embodiments, the GSP signal is generated according to the horizontal synchronization signal (Hsync) and the vertical synchronization signal (Vsync).
When the timing controller 40 receives the first control signal, the timing controller 40 operates in the interlaced processing mode, and when receiving the second control signal, the timing controller 40 operates in the progressive processing mode.
(1) The Timing Controller Operates in Interlaced Processing Mode:
When the receiving unit 41 receives a video data input signal, which is a frame of a video signal in an interlaced format in this case, the frame of the video signal in the interlaced format includes image data having an odd-field signal and an even-field signal. The timing controller 40 performs timing processing according to the input signal, which includes the horizontal synchronization signal (Hsync), the vertical synchronization signal (Vsync) and the clock signal, and outputs a gate control signal including the OE signal, the GCK signal, and the GSP signal. In a data signal period in one line, the GCK signal includes two clock pulses, and the OE signal includes one pulse signal.
Specifically, the first-field signal of the input signal is video data of 1920*540/240 Hz of the odd-field, and an image signal sending period in each line is 1/240*540=7.6*10−6 s. When the timing processing unit 43 performs timing processing to output the GCK signal, within the image signal sending period of 7.6*10−6 s, two clock pulses are generated. In this way, when the 540 lines of the video data for the odd-field are input, 1080 boost pulses for the GCK signal are generated, and are correspondingly input to the gate drive circuit to generate 1080 shift output pulse signals. Moreover, within the image signal sending period in the same line, one boost pulse of the OE signal is generated and output, where the width of the boost pulse of the OE signal covers the second clock pulse of the two clock pulses of the GCK signal. In this way, 540 pulses of the OE signals are generated. The term “covering” refers to the width of the boost pulse of the OE signals being greater than the second width of the second clock pulse of the two clock pulses of the GCK signal. At a start time period of a period of the input signal of the odd-field, the timing processing unit 43 further generates the GSP signal, which is configured to start scanning for the field signal.
The second-field signal of the input signal is video data of 1920*540/240 Hz of the odd-field, and an image signal sending period in each line is 1/240*540=7.6*10−6 s. When the timing processing unit 43 performs timing processing to output the GCK signal, within the image signal sending period of 7.6*10−6 s, two clock pulses are generated. In this way, when the 540 lines of the video data for the odd-field are input, 1080 boost pulses for the GCK signal are generated, and are correspondingly input to the gate drive circuit to generate 1080 shift output pulse signals. Moreover, within the image signal sending period in the same line, one boost pulse of the OE signal is generated and output, where the width of the boost pulse of the OE signal covers the first clock pulse of the two clock pulses of the GCK signal. In this way, 540 pulses of the OE signals are generated. At a start time period of a period of the input signal of the odd-field, the timing processing unit 43 further generates the GSP signal, which is configured to start scanning for the field signal.
Similar to the first implementation, the first-field signal of the input signal is video data of 1920*540/240 Hz of the odd-field, and an image signal sending period in each line is 1/240*540=7.6*10−6 s. When the timing processing unit 43 performs timing processing to output the GCK signal, within the image signal sending period of 7.6*10−6 s, two clock pulses are generated. In this way, when the 540 lines of the video data for the odd-field are input, 1080 boost pulses for the GCK signal are generated, and are correspondingly input to the gate drive circuit to generate 1080 pulses of shift output signals. Moreover, within the image signal sending period in the same line, one buck pulse of the OE signal is generated and output, where the width of the buck pulse of the OE signal covers the second clock pulse of the two clock pulses of the GCK signal. In this way, 540 buck pulses of the OE signals are generated. At a start time period of a period of the input signal of the odd-field, the timing processing unit 43 further generates the GSP signal, which is configured to start scanning for the field signal.
The second-field signal of the input signal is video data of 1920*540/240 Hz of the odd-field, and an image signal sending period in each line is 1/240*540=7.6*10−6 s. When the timing processing unit 43 performs timing processing to output the GCK signal, within the image signal sending period of 7.6*10−6 s, two clock pulses are generated. In this way, when the 540 lines of the video data for the odd-field are input, 1080 boost pulses for the GCK signal are generated, and are correspondingly input to the gate drive circuit to generate 1080 pulses of shift output signals. Moreover, within the image signal sending period in the same line, one buck pulse of the OE signal is generated and output, where the width of the buck pulse of the OE signal covers the first clock pulse of the two clock pulses of the GCK signal. In this way, 540 buck pulses of the OE signals are generated. At a start time period of a period of the input signal of the odd-field, the timing processing unit 43 further generates the GSP signal, which is configured to start scanning for the field signal.
(2) The Timing Controller Operates in Progressive Processing Mode:
When the timing controller 40 receives the second control signal, the timing controller 40 operates in the progressive processing mode. In the progressive processing mode, the timing controller 40 performs timing processing to the received video data in the progressive format, and generates a gate control signal, which includes the OE signal, the GCK signal, and the GSP signal.
The gate drive circuit 30 receives the gate control signal output by the timing controller 40, which includes the OE signal, the GCK signal and the GSP signal. In scanning the odd field, at a first time period corresponding to the first clock pulse of the two clock pulses of the GCK signal, the gate drive circuit 30 outputs the gate drive signal in a high potential to drive one of odd-line gate buses, and at a second time period corresponding to the second clock pulse of the two clock pulses, the gate drive circuit 30 outputs the gate drive signal in a low potential to drive one of even-line gate buses. In scanning the even field, at the first time period, the gate drive circuit 30 outputs the gate drive signal in the low potential to drive one of the odd-line gate buses, and at the second time period, the gate drive circuit 30 outputs the gate drive signal in the high potential to drive one of the even-line gate buses.
Each of the first and second time periods corresponding to the two clock pulses is a clock pulse period, and is formed by a boost pulse and a buck pulse, as shown in
Further, in scanning the odd field, the pulse signal counteracts the second clock pulse of the two clock pulses, such that the gate drive signal to drive the even-line gate buses is in the low potential at the second time point. In scanning the even field, the pulse signal counteracts the first clock pulse of the two clock pulses, such that the gate drive signal to drive the odd-line gate buses is in the low potential at the first time point.
The term “counteracting” refers to an operation that a shift output signal in a high potential, which is generated by the clock pulse, and the boost pulse in a corresponding timing undergo a logic circuit process in the gate drive circuit, thus outputting a gate drive signal in the low potential.
Specifically, in one embodiment, when an interlaced signal including an odd-field signal and an even-field signal is received, the interlaced signal is converted into a progressive signal, and then scanned and displaced in a progressive scanning manner. Referring to
In certain embodiments of the present invention, in scanning the odd field, the pulse signal of the OE signal counteracts the second clock pulse of the two clock pulses of the GCK signal, such that the gate drive signal to drive the even-line gate buses is in the low potential at the second time point. In this way, when the gate drive signal drives the odd-line gate buses at the first time period corresponding to the first clock pulse, a high potential pulse is generated, and a corresponding odd-line gate bus is driven to turn on. When the gate drive signal drives the even-line gate buses at the second time period corresponding to the second clock pulse, a low potential pulse is generated, and a corresponding even-line gate bus is turned off. Therefore, in a process of sequentially scanning each line of the gate buses, at the first time period corresponding to the first clock pulse, the gate drive signal on the corresponding gate bus in the first line generates a high potential pulse, and the high potential pulse drives the gate bus in the first line to turn on, while the gate drive signals on other gate buses are all in the low potential. At the second time period corresponding to the second clock pulse, the gate drive signal on the corresponding gate bus in the second line generates a low potential pulse, and the low potential pulse turns off the gate bus in the second line, while the gate drive signals on other gate buses are all in the low potential. The following procedures of the process may be deduced by analogy. At the (n−1)th time period corresponding to the (n−1)th (which is an odd number) clock pulse, the gate drive signal on the corresponding gate bus in the (n−1)th line generates a high potential pulse, and the high potential pulse drives the gate bus in the (n−1)th line to turn on, while the gate drive signals on other gate buses are all at the low potential. At the n-th time period corresponding to the n-th (which is an even number) clock pulse, the gate drive signal on the corresponding gate bus in the n-th line generates a low potential pulse, and the low potential pulse turns off the gate bus in the n-th line, while the gate drive signals on other gate buses are all in the low potential.
In scanning the even field, the pulse signal counteracts the first clock pulse of the two clock pulses, such that the gate drive signal to drive the odd-line gate buses is in the low potential at the first time point. In this way, when the gate drive signal drives the odd-line gate buses at the first time period corresponding to the first clock pulse, a low potential pulse is generated, and a corresponding odd-line gate bus is turned off. When the gate drive signal drives the even-line gate buses at the second time period corresponding to the second clock pulse, a high potential pulse is generated, and a corresponding even-line gate bus is driven to turn on. Therefore, in a process of sequentially scanning each line of the gate buses, at the first time period corresponding to the first clock pulse, the gate drive signal on the corresponding gate bus in the first line generates a low potential pulse, and the low potential pulse turns off the gate bus in the first line, while the gate drive signals on other gate buses are all in the low potential. At the second time period corresponding to the second clock pulse, the gate drive signal on the corresponding gate bus in the second line generates a high potential pulse, and the high potential pulse drives the gate bus in the second line to turn on, while the gate drive signals on other gate buses are all in the low potential. The following procedures of the process may be deduced by analogy. At the (n−1)th time period corresponding to the (n−1)th (which is an odd number) clock pulse, the gate drive signal on the corresponding gate bus in the (n−1)th line generates a low potential pulse, and the low potential pulse turns off the gate bus in the (n−1)th line, while the gate drive signals on other gate buses are all at the low potential. At the n-th time period corresponding to the n-th (which is an even number) clock pulse, the gate drive signal on the corresponding gate bus in the n-th line generates a high potential pulse, and the high potential pulse drives the gate bus in the n-th line to turn on, while the gate drive signals on other gate buses are all in the low potential.
A first embodiment of the gate drive circuit 30 is provided as follows.
Specifically,
Further referring to
In the first implementation of the Embodiment 1, in scanning the odd field, in an output period for providing image data of each line to the liquid crystal panel, a high potential GOUT signal is output to each of the odd lines, and a low potential GOUT signal is output to each of the even lines. In this way, a high potential GOUT signal is output in scanning the odd lines to turn on the corresponding odd-line gate bus and correspondingly write a line of data signals therein. A low potential GOUT signal is output in scanning the even lines to turn off the corresponding even-line gate bus is turned off, and the data signal in the previous field therein is maintained. Thus, the odd-line image is refreshed and displayed by the odd-field data signal.
Further, as shown in
In the first implementation of the Embodiment 1, in scanning the even field, in an output period for providing image data of each line to the liquid crystal panel, a high potential GOUT signal is output to each of the even lines, and a low potential GOUT signal is output to each of the odd lines. In this way, a high potential GOUT signal is output in scanning the even lines to turn on the corresponding even-line gate bus and correspondingly write a line of data signals therein. A low potential GOUT signal is output in scanning the odd lines to turn off the corresponding odd-line gate bus is turned off, and the data signal in the previous field therein is maintained. Thus, the even-line image is refreshed and displayed by the odd-field data signal.
In the first implementation of the Embodiment 1, by receiving the odd-field signal, the odd-line image can be refreshed and displayed, and by receiving the even-field signal, the even-line image can be refreshed and displayed. By receiving the progressive image signal, the image can be refreshed and displayed progressively. In this way, the display device implemented by the technical solution of the embodiment can achieve compatible progressive and interlaced scanning and displaying, thereby saving the storage and a periphery auxiliary circuit required in a format converter in the conventional device.
A second embodiment of the gate drive circuit 30 is provided as follows:
Specifically,
Further, as shown in
In the second implementation of the Embodiment 1, in scanning the odd field, in an image data period in each line, a high potential GOUT signal is output to each of the odd lines, and a low potential GOUT signal is output to each of the even lines. In this way, a high potential GOUT signal is output in scanning the odd lines to turn on the corresponding odd-line gate bus and correspondingly write a line of data signals therein. A low potential GOUT signal is output in scanning the even lines to turn off the corresponding even-line gate bus is turned off, and the data signal in the previous field therein is maintained. Thus, the odd-line image is refreshed and displayed by the odd-field data signal.
Further, as shown in
In the second implementation of the Embodiment 1, in scanning the even field, in a data period in each line, a high potential GOUT signal is output to each of the even lines, and a low potential GOUT signal is output to each of the odd lines. In this way, a high potential GOUT signal is output in scanning the even lines to turn on the corresponding even-line gate bus and correspondingly write a line of data signals therein. A low potential GOUT signal is output in scanning the odd lines to turn off the corresponding odd-line gate bus is turned off, and the data signal in the previous field therein is maintained. Thus, the even-line image is refreshed and displayed by the odd-field data signal.
In the second implementation of the Embodiment 1 by receiving the odd-field signal, the odd-line image can be refreshed and displayed, and by receiving the even-field signal, the even-line image can be refreshed and displayed. By receiving the progressive image signal, the image can be refreshed and displayed progressively. In this way, the display device implemented by the technical solution of the embodiment can achieve compatible progressive and interlaced scanning and displaying.
In this embodiment, an image displaying method is further provided, which may be applied to a display device driven by a gate drive signal and a data drive signal.
S10: Determine an input signal as an interlaced signal or a progressive signal. When the input signal is an interlaced signal, execute Step S20. When the input signal is a progressive signal, execute Step S30.
S200: A timing controller receives an input signal, which includes an odd-field signal and an even-field signal, where the input signal includes an image signal, a horizontal synchronization signal, a vertical synchronization signal, a DE signal, and a clock signal.
S400: Generate a gate control signal, a data control signal, and a data signal, where the gate control signal includes an OE signal and a GCK signal, and in one horizontal synchronization signal period, the GCK signal includes two clock pulses, and the OE signal includes one pulse in a first potential.
S600: A gate drive circuit processes the OE signal and the GCK signal to generate the gate drive signal.
In scanning the odd field, at a first time period corresponding to the first clock pulse, the gate drive circuit outputs the gate drive signal in a high potential to turn on and write a line of the data drive signal in one of odd-line gate buses, and at a second time period corresponding to the second clock pulse, the gate drive circuit outputs the gate drive signal in a low potential to turn off one of even-line gate buses.
In scanning the even field, at the first time period, the gate drive circuit outputs the gate drive signal in the low potential to turn off one of the odd-line gate buses, and at the second time period, the gate drive circuit outputs the gate drive signal in the high potential to turn on and write a line of the data drive signal in one of the even-line gate buses.
S100: Receive an input signal in a progressive format, where the input signal includes an image signal, a horizontal synchronization signal, a vertical synchronization signal, a DE signal, and a clock signal.
S300: Generate a gate control signal, a data control signal, and a data signal, where the gate control signal includes an OE signal and a GCK signal, and in one horizontal synchronization signal period, the GCK signal includes a single clock pulse, and the OE signal includes one pulse in a first potential.
S500: Process the OE signal and the GCK signal to generate the gate drive signal.
The difference between Embodiment 2 and Embodiment 1 lies in the operational method for receiving an interlaced signal by a timing controller.
A video data input signal received by the receiving unit 41 is interlaced-format video data, where the interlaced-format video data includes odd-field data and even-field data. The timing processing unit 43 performs timing processing according to the input signal, which includes the horizontal synchronization signal (Hsync), the vertical synchronization signal (Vsync), and the clock signal, and then outputs a gate control signal including an OE signal, a GCK signal, and a GSP signal.
In scanning the odd field, in the gate drive signal, a first potential pulse of the OE signal counteracts the second clock pulse in the two clock pulses included in the GCK signal, where the first width of the first clock pulse of the two clock pulses of the GCK signal is greater than the second width of the second clock pulse.
In scanning the even field, the first potential pulse of the OE signal counteracts the first clock pulse in the two clock pulses of the GCK signal, where the first width of the first clock pulse of the two clock pulses of the GCK signal is smaller than the second width of the second clock pulse.
In a preferred Embodiment 2 of the present invention, when interlaced scanning and displaying is performed on the interlaced signal, in a data signal period in one line, two gate scanning clock signals are generated, and two lines of gate buses need to be scanned. For example, for 1920*540/240 Hz interlaced image data, the timing processing unit 43 generates two GCK signals at the same time, which results in a double frame frequency when the display device progressively scans the data. One of ordinary skill in the art knows that the display screen having a higher scanning frequency has a longer liquid crystal molecules response time. However, the liquid crystal molecules response time is determined by the characteristics of the liquid crystal screen. In a case where the scanning frequency is improved, in order to reduce the effect brought by the liquid crystal molecules response time, in the Embodiment 2, in scanning the odd-line image, within a data scanning period in one line, the odd-line gate bus is turned on, and the first width of a corresponding clock pulse is greater than the second width of the clock pulse corresponding to the even-line gate bus; in scanning the even-line image, within a data scanning period in one line, the even-line gate bus is turned on, and the second width of the corresponding clock pulse is greater than the first width of the clock pulse corresponding to the odd-line gate bus. In this way, in comparison with the Embodiment 1, in an interlaced scanning mode, in the image scanning line, the time consumed in turning on the gate bus is prolonged, and there is plenty of time for the liquid crystal molecules in the image scanning line to be activated to a stable state, thereby reducing the trailing effect brought by the liquid crystal molecules response time.
Specifically, with reference to
With reference to
In the first implementation of the Embodiment 2, by receiving the odd-field signal, the odd-line image can be refreshed and displayed, and the even line maintains the previous even-field image. By receiving the even-field signal, the even-line image can be refreshed and displayed, and the odd line maintains the previous even-field image.
Specifically, with reference to
With reference to
In the second implementation of the Embodiment 2, by receiving the odd-field signal, the odd-line image can be refreshed and displayed, and the even line maintains the previous even-field image. By receiving the even-field signal, the even-line image can be refreshed and displayed, and the odd line maintains the previous even-field image.
The foregoing description of the exemplary embodiments of the invention has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.
The embodiments were chosen and described in order to explain the principles of the invention and their practical application so as to activate others skilled in the art to utilize the invention and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the invention pertains without departing from its spirit and scope. Accordingly, the scope of the invention is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201310223124.1 | Jun 2013 | CN | national |
