Display device with high resolution and slim border structure

Abstract

A display device has a pixel array, a plurality of data buses and a drive circuit. The pixel array has a plurality of data lines and a plurality of pixels. The pixels are electrically coupled to the data lines, and these data lines are electrically coupled to these data buses. The drive circuit receives a plurality of image data sequentially and transforms the image data into pixel voltages, which are outputted from corresponding output terminals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (Related Art) is a schematic illustration showing a conventional liquid crystal display device.

FIG. 2 (Related Art) is a schematic illustration showing a liquid crystal display device with an enlarged circuit area on a lateral side.

FIG. 3 is a schematic illustration showing a drive circuit according to the invention.

FIG. 4A is a schematic illustration showing a liquid crystal display device according to a first embodiment of the invention.

FIG. 4B is a timing chart showing control signals according to the first embodiment of the invention.

FIG. 5A is a schematic illustration showing a liquid crystal display device according to a second embodiment of the invention.

FIG. 5B is a timing chart showing control signals according to the second embodiment of the invention.

Claims

1. A thin film transistor display device, comprising: a pixel array having: a plurality of data lines sequentially disposed, in parallel, from a first side of the pixel array to a second side opposite to the first side of the pixel array, wherein two ends of each of the data lines extend to a third side of the pixel array and a fourth side of the pixel array opposite to the third side of the pixel array, respectively; anda plurality of pixels electrically coupled to the data lines, respectively;a plurality of data buses, wherein first ends of one portion of the data buses are electrically coupled to one corresponding portion of the data lines at the third side of the pixel array, and first ends of the other portion of the data buses are electrically coupled to the other corresponding portion of the data lines at the fourth side of the pixel array; anda drive circuit for sequentially receiving a plurality of image data and thus driving the pixels, the drive circuit having: a plurality of output terminals electrically coupled to second ends of the data buses, wherein the drive circuit transforms the image data into a plurality of pixel voltages and then outputs the image data from the corresponding output terminals according to an arrangement relationship between the output terminals and the data lines.

2. The device according to claim 1, wherein the drive circuit further has: a plurality of first latch units, wherein the drive circuit respectively stores the image data into the corresponding first latch units according to the arrangement relationship between the output terminals and the data lines;a plurality of second latch units, electrically coupled to the plurality of first latch units respectively, for receiving the image data stored in the first latch units; anda plurality of digital-to-analog converting units, electrically coupled to the plurality of second latch units and the output terminals respectively, for receiving the image data stored in the second latch units and transforming the image data into the pixel voltages and then outputting the pixel voltages from the corresponding output terminals.

3. The device according to claim 2, wherein the data lines have M data lines DL(1) to DL(M), the output terminals have N output terminals X(1) to X(N), where M and N are positive integers, one portion of the data lines DL(1) to DL(M/2) is electrically coupled to the corresponding output terminals X(1) to X(N/2) at the third side of the pixel array, and the other portion of the data lines DL(M/2+1) to DL(M) is electrically coupled to the corresponding output terminals X(N) to X(N/2+1) at the fourth side of the pixel array.

4. The device according to claim 3, wherein the first latch units have N first latch units L1(1) to L1(N) for respectively receiving control signals C(1) to C(N), the corresponding first latch units L1 store the received image data when the control signals C(1) to C(N) are enabled respectively, and the control signals C(1) to C(N) are enabled in an order from C(1) to C(2) . . . C(N/2), C(N), C(N−1) . . . C(N/2+1) according to the arrangement relationship between the output terminals X(1) to X(N) and the data lines DL(1) to DL(M).

5. The device according to claim 2, wherein the data lines have M data lines DL(1) to DL(M), the output terminals have N output terminals X(1) to X(N), where M and N are positive integers, the odd numbered data lines DL(1), DL(3), DL(5) . . . are electrically coupled to the corresponding output terminals X(1) to X(N/2) at the third side of the pixel array, the even numbered data lines DL(2), DL(4), DL(6) . . . are electrically coupled to the corresponding output terminals X(N) to X(N/2+1) at the fourth side of the pixel array.

6. The device according to claim 5, wherein the first latch units have N first latch units L1(1) to L1(N) for respectively receiving control signals C(1) to C(N), the corresponding first latch units L1 store the received image data when the control signals C(1) to C(N) are enabled respectively, and the control signals C(1) to C(N) are enabled in an order from C(1) to C(N), C(2), C(N−1), C(3), C(N−2) . . . according to the arrangement relationship between the output terminals X(1) to X(N) and the data lines DL(1) to DL(M).