Patent Application
20240046900
This application claims the benefit of priority to Japanese Patent Application Number 2022-126400 filed on Aug. 8, 2022. The entire contents of the above-identified application are hereby incorporated by reference.
The disclosure relates to a display device.
A known technique relating to liquid crystal panels repairs the disconnection of a signal line using a spare wiring line. For example, in the method described in WO 2020/012654, a signal voltage is output to a portion of a disconnected signal line beyond a disconnection location, the signal voltage being obtained by correcting a signal voltage to be output to this portion on the basis of the position of the disconnection location, the wiring line resistance of the signal line, and the wiring line resistance of the spare wiring line.
In another example described in JP 2015-082063, a delay correction value is calculated on the basis of a position of a scanning line corresponding to a pixel whose gray scale specified by a gray-scale voltage, and a timing for outputting the gray-scale voltage to a data signal line is corrected (is correction) on the basis of the delay correction value.
In the methods described in WO 2020/012654 and JP 2015-082063, τs correction cannot be appropriately performed when repairing a disconnection using a spare wiring line.
An object of an aspect of the disclosure is to provide a technique for appropriately performing is correction even when disconnection is corrected using a spare wiring line.
A display device according to an aspect of the disclosure includes: a plurality of pixels; a plurality of scanning signal lines; a plurality of data signal lines; a source driver configured to supply a data signal to the plurality of pixels via a corresponding data signal line of the plurality of data signal lines; and a spare wiring line configured to connect to a disconnected data signal line, wherein for each data signal output to a data signal line with disconnection corrected by the spare wiring line, the source driver sets an output delay amount according to a disconnection position and a line position of a pixel to be supplied with the data signal.
Accordingly, even when disconnection is corrected using a spare wiring line, τs correction can be appropriately performed.
The disclosure will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
The liquid crystal panel 1 includes a plurality of scanning signal lines G, a plurality of data signal lines S that intersect the plurality of scanning signal lines G, and a plurality of pixels P provided in a one-to-one correspondence at each intersection between the plurality of scanning signal lines G and the plurality of data signal lines S. The pixels P each include a transistor TR and a liquid crystal capacitance LC. The liquid crystal capacitance LC includes a pixel electrode, a common electrode Ec, and a liquid crystal layer disposed between the pixel electrode and the common electrode Ec. The gate terminal of the transistor TR is connected to the scanning signal line G, the source terminal of the transistor TR is connected to the data signal line S, and a data signal DS is written to the liquid crystal capacitance LC from the data signal line S via the transistor TR.
The control unit 5 (e.g., a timing controller) is provided on the control board 6. The control unit 5 outputs a display signal J (e.g., a differential signal) to the source driver 2. The control board 6 and the source substrate 3 are connected to one another via a Flexible Flat Cable (FFC), and the source substrate 3 and the liquid crystal panel 1 are connected to one another via a plurality of Flexible Printed Circuits (FPCs) 7. The plurality of FPCs 7 are each provided with the source driver 2, and each source driver 2 includes a spare wiring line buffer BF. A plurality of the source substrates 3 may be provided. The source driver 2 outputs the data signal DS to the data signal line S of the liquid crystal panel 1. The gate driver 4 outputs a scanning signal GS to a scanning signal line G of the liquid crystal panel 1. In the example described hereinafter, the source driver 2 is provided below the liquid crystal panel 1, and the plurality of pixel rows (hereinafter, referred to as lines L) of the liquid crystal panel 1 are scanned from up to down.
As illustrated in
The data signal line (hereinafter also referred to as the corrected data signal line) Sy for which disconnection has been corrected using the spare wiring lines 11 and 12 includes a first portion A1 that is located on the same side of a disconnection position Y as the source driver 2 and that is connected to the source driver 2 without passing through the spare wiring lines 11 and 12, and a second portion A2 that is located on the opposite side of the disconnection position Y from the source driver 2 and that is connected to the source driver 2 via the spare wiring lines 11 and 12.
The source driver 2 of Example 1 sets, for each data signal DS output to the data signal line Sy with disconnection corrected by the spare wiring lines 11 and 12, an output delay amount UD according to the disconnection position Y and the line position L of the pixel P to be supplied with the data signal DS.
The source driver 2 is connected to the first portion A1 of the corrected data signal line Sy and is connected to the second portion A2 of the corrected data signal line Sy via the spare wiring line 11, the spare wiring line buffer BF, and the spare wiring line 12. The spare wiring line 11 is connected at one end to an input terminal of the spare wiring line buffer BF and, at a peripheral region on a side close to the source driver 2, is connected to the first portion A1 of the corrected data signal line Sy by a disconnection correction process using a laser or the like. The spare wiring line 12 is connected at one end to an output terminal of the spare wiring line buffer BF and, at a peripheral region on a side far from the source driver 2, is connected to the second portion A2 of the corrected data signal line Sy by a disconnection correction process using a laser or the like. The data signal DS output from the source driver 2 is transmitted to the first portion A1 without passing through the spare wiring lines 11 and 12, and is also transmitted to the second portion A2 via the spare wiring line 11, the spare wiring line buffer BF, and the spare wiring line 12. In the disclosure, the data signal DS output to the first portion A1 means the data signal DS supplied to the pixel P connected to the first portion A1, and the data signal DS output to the second portion A2 means the data signal DS supplied to the pixel P connected to the second portion A2.
The source driver 2 sets the output delay amount UD for each data signal DS output to the second portion A2. In other words, the source driver 2 delays the output timing of each data signal DS output to the second portion A2 by a period of time corresponding to the output delay amount UD set for each data signal DS. The source driver 2 sets the largest output delay amount UD for, of each data signal DS output to the second portion A2 of one corrected data signal line Sy, the data signal DS supplied to the pixel P of a line position Li farthest from the source driver 2, and sets the smallest output delay amount UD for the data signal DS supplied to the pixel P of a line position Ln closest to the disconnection position Y.
In the present example, the source driver 2 sets, for each data signal DS output to the second portion A2, the output delay amount UD that is smaller the closer the line position L of the pixel P to be supplied with the data signal DS is to the disconnection position Y. Note that the same output delay amount UD may be set for the data signals DS supplied to the pixels P at two or more adjacent line positions L.
The source driver 2 also sets the output delay amount UD for each data signal DS output to the first portion A1. In other words, the source driver 2 delays the output timing of each data signal DS output to the first portion A1 by a period of time corresponding to the output delay amount UD set for each data signal DS. The source driver 2 sets the largest output delay amount UD for, of each data signal DS output to the first portion A1 of one corrected data signal line Sy, the data signal DS supplied to the pixel P of a line position Lm closest to the source driver 2, and sets the smallest output delay amount UD for the data signal DS supplied to the pixel P of a line position Ln+1 closest to the disconnection position Y.
In the present example, the source driver 2 sets, for each data signal DS output to the first portion A1, the output delay amount UD that is smaller the closer the line position L of the pixel P to be supplied with the data signal DS is to the disconnection position Y. Note that the same output delay amount UD may be set for the data signals DS supplied to the pixels P at two or more adjacent line positions L.
The source driver 2 also sets the output delay amount UD for the data signal DS output to a normal data signal line Sx without disconnection correction. In other words, the source driver 2 delays the output timing of each data signal DS output to the normal data signal line Sx by a period of time corresponding to the output delay amount UD set for each data signal DS. The source driver 2 sets the largest output delay amount UD for, of each data signal DS output to one normal data signal line Sx, the data signal DS supplied to the pixel P of a line position Lm closest to the source driver 2, and sets the smallest output delay amount UD for the data signal DS supplied to the pixel P of the line position Li farthest from the source driver 2.
In the present example, the source driver 2 sets, for each data signal DS output to the normal data signal line Sx, the output delay amount UD that is smaller the farther the line position L of the pixel P to be supplied with the data signal DS is from the source driver 2. Note that the same output delay amount UD may be set for the data signals DS supplied to the pixels P at two or more adjacent line positions L.
A transmission delay amount TD of the first portion A1 is larger when the line position L of the pixel P is closer to the disconnection position Y. Thus, the source driver 2 sets, for each data signal DS output to the first portion A1, the output delay amount UD that is smaller the closer the line position L of the pixel P to be supplied with the data signal DS is to the disconnection position Y. For example, the output delay amount UD of the data signal DS supplied to the pixel P of the line position L4 (transmission delay amount TD=2) is set to ‘6’, and the output delay amount UD of the data signal DS supplied to the pixel P of the line position L5 (transmission delay amount TD=0) is set to ‘8’.
As described above, by making the sum of the output delay amount UD and the transmission delay amount TD between the first portion A1 and the second portion A2 in the corrected data signal line Sy the same and making the sum of the output delay amount UD and the transmission delay amount TD between the corrected data signal line Sy and the normal data signal line Sx the same, mistiming of the transmission of the data signal DS between the data signal lines Sx and Sy can be corrected. Thus, even when the disconnection is corrected using the spare wiring lines 11 and 12, τs correction can be appropriately performed.
The data interface 21 uses the display signal J to generate signals such as a decoded image signal DA, a clock signal CK, a latch signal LS, and a polarity signal PS. The shift register 23 sequentially receives the image signals DA (digital signals) from the data interface 21 and repeats a shift operation until the number of the image signals DA equals a predetermined number. The latch circuit 24 latches the image signals DA output from the shift register 23 on the basis of the latch signal LS and outputs the latched image signals DA to the delay circuit 25. The delay circuit 25 has a function of delaying and holding the image signals DA for a discretionary period of time.
The line counter 30 is a counter that counts the line position of the pixel P to be supplied with the data signal DS. The line counter 30 increases the count value by one each time one horizontal period ends according to the latch signal LS output from the data interface 21. Also, the line counter 30 resets the count value to zero every time one frame is completed. The count value of the line counter 30 is output to the first delay amount counter 31 and the second delay amount counter 32.
The first delay amount counter 31 is a counter that increases the count value as line scanning progresses in one vertical scanning period. In the present example, the count value of the first delay amount counter 31 is used when setting the output delay amount UD for each data signal DS output to the normal data signal line Sx and the first portion A1 of the corrected data signal line Sy. The count value of the first delay amount counter 31 is set to a first initial value when the count value of the line counter 30 is zero. Also, the count value of the first delay amount counter 31 increases by one each time the count value of the line counter 30 becomes a multiple of the line number for changing a delay amount. The first initial value is an initial value (or a value corresponding thereto) of the output delay amount UD associated with the normal data signal line Sx, and specifically is the output delay amount UD (or a value corresponding thereto) set for the data signal DS which is the first output to the normal data signal line Sx in one frame. In the present example, the first initial value is the output delay amount UD set for the data signal DS supplied to the pixel P of the line position L1 connected to the normal data signal line Sx and is ‘0’, for example. In addition, the line number for changing a delay amount is a discretionary number. For example, when the line number for changing the delay amount is ‘8’, the count value of the first delay amount counter 31 is increased by one each time the count value of the line counter 30 becomes a multiple of ‘8’. In this case, the same output delay amount UD is set for the data signals DS supplied to the pixels P of eight adjacent line positions L.
The second delay amount counter 32 is a counter that decreases the count value as line scanning progresses in one vertical scanning period. In the present example, the count value of the second delay amount counter 32 is used when setting the output delay amount UD for each data signal DS output to the second portion A2 of the corrected data signal line Sy. The count value of the second delay amount counter 32 is set to a second initial value when the count value of the line counter 30 is zero. Also, the count value of the second delay amount counter 32 decreases by one each time the count value of the line counter 30 becomes a multiple of the line number for changing a delay amount. The second initial value is an initial value (or a value corresponding thereto) of the output delay amount UD associated with the second portion A2 of the corrected data signal line Sy, and specifically is the output delay amount UD (or a value corresponding thereto) set for the data signal DS which is the first output to the second portion A2 in one frame. In the present example, the second initial value is the output delay amount UD set for the data signal DS supplied to the pixel P of the line position L1 connected to the second portion A2 and is ‘8’, for example. The line number for changing a delay amount is a discretionary number. The line number for changing a delay amount may be the same for both the first delay amount counter 31 and the second delay amount counter 32, or may be different. For example, when the line number for changing the delay amount is ‘8’, the count value of the second delay amount counter 32 is decreased by one each time the count value of the line counter 30 becomes a multiple of ‘8’. In this case, the same output delay amount UD is set for the data signals DS supplied to the pixels P of eight adjacent line positions L.
The delay circuit 25 sets the output delay amount UD for each data signal DS output to the plurality of data signal lines S on the basis of the count value of the first delay amount counter 31 and the count value of the second delay amount counter 32. In the present example, the delay circuit 25 sets the output delay amount UD based on the count value of the first delay amount counter 31 for each data signal DS output to the normal data signal line Sx and the first portion A1 of the corrected data signal line Sy. Also, the delay circuit 25 sets the output delay amount UD based on the count value of the second delay amount counter 32 for each data signal DS output to the second portion A2 of the corrected data signal line Sy.
Specifically, the delay circuit 25 holds each image signal DA corresponding to the data signal DS output to the normal data signal line Sx for a period of time corresponding to a clock number that corresponds to the count value of the first delay amount counter 31 and delays the output timing to the DAC 26. Here, the period of time corresponding to the clock number that corresponds to the count value of the first delay amount counter 31 corresponds to the period of time corresponding to the output delay amount UD associated with the data signal DS (data signal DS output in the current horizontal period) to be output among the data signals DS output to the normal data signal line Sx. In this manner, the output timing of the data signal DS output to the normal data signal line Sx is delayed by a period of time corresponding to the output delay amount UD associated with the data signal DS.
In addition, the delay circuit 25, for each image signal DA corresponding to the data signal DS output to the corrected data signal line Sy, switches between the delay amount counters (the first delay amount counter 31 and the second delay amount counter 32) to be referenced, according to the count value of the line counter 30, and sets the output delay amount UD. In other words, while the count value of the line counter 30 is in a range from 0 to a value corresponding to the disconnection position Y (that is, in the period of time the data signal DS is supplied to the pixel P connected to the second portion A2), the delay circuit 25 holds each image signal DA corresponding to the data signal DS output to the corrected data signal line Sy (the second portion A2 in this example) for a period of time corresponding to the clock number that corresponds to the count value of the second delay amount counter 32, and delays the output timing to the DAC 26. Here, the period of time corresponding to the clock number that corresponds to the count value of the second delay amount counter 32 corresponds to the period of time corresponding to the output delay amount UD associated with the data signal DS to be output among the data signals DS output to the second portion A2. In this manner, the output timing of the data signal DS output to the second portion A2 of the corrected data signal line Sy is delayed by a period of time corresponding to the output delay amount UD associated with the data signal DS.
On the other hand, when the count value of the line counter 30 is greater than the value corresponding to the disconnection position Y (that is, in the period of time the data signal DS is supplied to the pixel P connected to the first portion A1), the delay circuit 25 holds each image signal DA corresponding to the data signal DS output to the corrected data signal line Sy (the first portion A1 in this example) for a period of time corresponding to the clock number that corresponds to the count value of the first delay amount counter 31, and delays the output timing to the DAC 26. Here, the period of time corresponding to the clock number that corresponds to the count value of the first delay amount counter 31 corresponds to the period of time corresponding to the output delay amount UD associated with the data signal DS to be output of the normal data signal line Sx described above as well as to the period of time corresponding to the output delay amount UD associated with the data signal DS to be output among the data signals DS output to the first portion A1. In this manner, the output timing of the data signal DS output to the first portion A1 of the corrected data signal line Sy is delayed by a period of time corresponding to the output delay amount UD associated with the data signal DS.
The gray-scale voltage generation circuit 22 generates a gray-scale voltage VT on the basis of the polarity signal PS, gamma data for gamma correction, and a reference voltage VK, and outputs the gray-scale voltage VT to the DAC 26.
The DAC 26 uses the gray-scale voltage VT output from the gray-scale voltage generation circuit 22 to convert the image signals DA (digital signals) output from the delay circuit 25 into the data signals DS (analog signals) and outputs the data signals DS to the output buffer 27.
The output buffer 27 outputs the data signals DS output from the DAC 26 to the data signal lines S (Sx and Sy).
The spare wiring line buffer BF is connected at one of two input terminals to the spare wiring line 11 and is connected at the output terminal to the spare wiring line 12. Output is fed back to the other of the two input terminals.
The register group 39 are registers for holding a setting value used in the source driver 2, and the data interface 21 sets a value for the register group 39 on the basis of the display signal J. The register group 39 includes the following registers, for example.
(1) a Register Set with a Value Indicating Whether the Corrected Data Signal Line Sy is Present in the Liquid Crystal Panel 1 (Register A)
When the value of the register A indicates that the corrected data signal line Sy is not present, the delay circuit 25 determines all of the data signal lines S to be normal and sets the output delay amount UD for each data signal DS on the basis of the count value of the first delay amount counter 31.
On the other hand, when the value of the register A indicates that the corrected data signal line Sy is present, for the corrected data signal line Sy indicated by the value of a register B described below, the delay circuit 25 sets the output delay amount UD for each data signal DS output to the first portion A1 on the basis of the count value of the first delay amount counter 31 and sets the output delay amount UD for each data signal DS output to the second portion A2 on the basis of the count value of the second delay amount counter 32. Also, for the normal data signal line Sx, not the corrected data signal line Sy indicated by the value of the register B, the delay circuit 25 sets the output delay amount UD for each data signal DS on the basis of the count value of the first delay amount counter 31.
(2) Register Set with Value Indicating Corrected Data Signal Line Sy (Register B)
The register B is set with a number or the like allocated to the corrected data signal line Sy, for example. When there are multiple corrected data signal lines Sy, the register B is set with a value indicating each of the corrected data signal lines Sy.
(3) Register Set with Value Indicating Disconnection Position Y in Corrected Data Signal Line Sy (Register C)
The register C is set with an address or the like in the vertical direction of the disconnection position Y as a value indicating the disconnection position Y. When there are multiple corrected data signal lines Sy, the register C is set with a value indicating the disconnection position Y for each of the corrected data signal lines Sy. The delay circuit 25 references the value of the register C and determines whether the count value of the line counter 30 is greater than the value corresponding to the disconnection position Y.
(4) Register Set with First Initial Value (Register D)
The value set for the register D is set for the first delay amount counter 31 as the initial value.
(5) Register Set with Second Initial Value (Register E)
The value set for the register E is set for the second delay amount counter 32 as the initial value.
(6) Register Set with Line Number for Changing a Delay Amount (Register F)
The first delay amount counter 31 and the second delay amount counter 32 reference the value set for the register F and update the count value.
When is correction is not performed, at the first portion A1 side of the corrected data signal line Sy and the normal data signal line Sx, a ghost image is displayed at the lower side of the image because the data signal DS supply timing is later than the timing at which the scanning signal becomes active, and at the second portion A2 side, a ghost image is displayed at the upper side of the image because the data signal DS supply timing is earlier than the timing at which the scanning signal becomes active. When is correction is performed without using the present example, at the first portion A1 side of the corrected data signal line Sy and the normal data signal line Sx, the ghost image disappears because the timing at which the scanning signal becomes active matches the data signal DS supply timing. However, at the second portion A2 side, the ghost image is more distinct than when is correction is not performed because the data signal DS supply timing is further earlier than the timing at which the scanning signal becomes active. On the other hand, in Example 1, at the first portion A1 side and the second portion A2 side of the corrected data signal line Sy and the normal data signal line Sx, the timing at which the scanning signal becomes active matches the data signal DS supply timing. Thus, in any case, the ghost image disappears, and image quality is improved.
Note that in the disclosure, the data signal DS supply timing refers to the timing at which the data signal DS is supplied to the supply target pixel P regardless of whether the transistor TR of the supply target pixel P is on, or in other words the timing at which the data signal DS reaches the supply target pixel P. In addition, the timing at which the scanning signal becomes active and the data signal DS supply timing are time periods of a discretionary length of time. The timing at which the scanning signal becomes active matching the data signal DS supply timing does not necessarily mean that both time periods have matching start and/or end times, and refers to both time periods having an appropriate relationship (this includes partially overlapping or one being included within the other) such that a desired voltage based on the data signal DS is appropriately applied to the supply target pixel P.
In the present example described herein, the source driver 2 is provided below the liquid crystal panel 1 and the data signals DS are supplied in order from the pixel P of the line position L1 farthest from the source driver 2. However, the source driver 2 may be provided above the liquid crystal panel 1, or the data signals DS may be supplied in order from the pixel P of the line position closest to the source driver 2, and, in these examples, a similar effect to the present example is obtained.
In an example in which the source driver 2 is provided below the liquid crystal panel 1 and the data signals DS are supplied in order from the pixel P of the line position Lm closest to the source driver 2, the delay amount counter to be referenced is the opposite of that in Example 1 described above, the count value of the second delay amount counter 32 is used when setting the output delay amount UD for each data signal DS output to the normal data signal line Sx and the first portion A1 of the corrected data signal line Sy, and the count value of the first delay amount counter 31 is used when setting the output delay amount UD for each data signal DS output to the second portion A2 of the corrected data signal line Sy. This example achieves a similar effect to that of Example 1.
The first portion A1 of the corrected data signal line Sy, as with the normal data signal line Sx, is directly connected to the source driver 2 without passing through the spare wiring lines 11 and 12. Thus, the first portion A1 of the corrected data signal line Sy and the normal data signal line Sx are essentially the same in terms of the transmission delay amount TD of the data signal DS supplied to the pixel P of the same line position L. In this manner, by the gate driver 4 delaying the scanning signal GS, the timing at which the scanning signal GS becomes active and the data signal DS supply timing match at not only the normal data signal line Sx but also at the first portion A1 of the corrected data signal line Sy. On the other hand, at the second portion A2 of the corrected data signal line Sy, by the gate driver 4 delaying the scanning signal GS, the timing at which the scanning signal GS becomes active and the data signal DS supply timing may become more offset from one another.
The source driver 2 of Example 2 sets, for each data signal DS output to the second portion A2 of the data signal line Sy with disconnection corrected by the spare wiring lines 11 and 12, the output delay amount UD according to the disconnection position Y and the line position L of the pixel P to be supplied with the data signal DS.
On the other hand, the source driver 2 does not set the output delay amount UD for each data signal DS output to the first portion A1 (L3 to L5) of the corrected data signal line Sy (output delay amount UD is ‘0’). That is, in Example 2, the output timing of each data signal DS output to the first portion A1 of the corrected data signal line Sy is not delayed. This is because, as described above, by the gate driver 4 delaying the scanning signal GS, the timing at which the scanning signal GS becomes active and the data signal DS supply timing match at the first portion A1 of the corrected data signal line Sy.
By setting the output delay amount UD for each data signal DS output to the second portion A2 (L1 and L2) as illustrated in
In this manner, at the normal data signal line Sx and the first portion A1 of the corrected data signal line Sy, the delay amount GD of the scanning signal GS is set so that the transmission delay amount TD of the data signal DS and the delay amount GD of the scanning signal GS match at each line. In addition, at the second portion A2 of the corrected data signal line Sy, the output delay amount UD of the data signal DS is set so that the sum of the output delay amount UD of the data signal DS and the transmission delay amount TD matches the delay amount GD of the scanning signal GS at each line. Accordingly, at the first portion A1 and the second portion A2 of the corrected data signal line Sy and the normal data signal line Sx, the timing at which the scanning signal GS becomes active and the data signal DS supply timing can be made to match. This makes ghost images disappear at all locations of the display region and improves image quality.
The delay amount counter 33 is a counter that decreases the count value as line scanning progresses in one vertical scanning period. The count value of the delay amount counter 33 is set to an initial value when the count value of the line counter 30 is zero. Also, the count value of the delay amount counter 33 decreases by one each time the count value of the line counter 30 becomes a multiple of the line number for changing a delay amount.
The delay circuit 35 sets the output delay amount UD for each data signal DS output to the second portion A2 of the corrected data signal line Sy on the basis of the count value of the delay amount counter 33. The delay circuit 35 is disposed on a path running from an output end 2f of the source driver 2 to the second portion A2 via the spare wiring lines 11 and 12. For example, the spare wiring line 11 is connected to the first portion A1 of the corrected data signal line Sy connected to the output end 2f, and is also connected to the delay circuit 35. Also, the delay circuit 35 is connected to an input terminal of the spare wiring line buffer BF, and an output terminal of the spare wiring line buffer BF is connected to the spare wiring line 12. Thus, the data signal DS output from the source driver 2 to the corrected data signal line Sy is input to the delay circuit 35 of Example 2.
While the count value of the line counter 30 is in a range from 0 to a value corresponding to the disconnection position Y (that is, in the period of time the data signal DS is supplied to the pixel P connected to the second portion A2), the delay circuit 35 holds the input data signal DS (the data signal DS output to the second portion A2 in this example) for a period of time corresponding to the clock number that corresponds to the count value of the delay amount counter 33, and delays the output timing to the spare wiring line buffer BF. Here, the period of time corresponding to the clock number that corresponds to the count value of the delay amount counter 33 corresponds to the period of time corresponding to the output delay amount UD associated with the data signal DS to be output among the data signals DS output to the second portion A2. In this manner, the output timing of the data signal DS output to the second portion A2 of the corrected data signal line Sy is delayed by a period of time corresponding to the output delay amount UD associated with the data signal DS.
On the other hand, when the count value of the line counter 30 is greater than a value corresponding to the disconnection position Y (that is, in the period of time the data signal DS is supplied to the pixel P connected to the first portion A1), the delay circuit 35 does not delay the output timing of the input data signal DS (the data signal DS output to the first portion A1 in this example) to the spare wiring line buffer BF. Note that the first portion A1 of the corrected data signal line Sy is directly connected to the source driver 2 without passing through the spare wiring lines 11 and 12. Thus, the data signal DS output to the first portion A1 is supplied to the supply target pixel P without passing through the delay circuit 35 (output delay amount UD of ‘0’).
Note that, in the present example described herein, the source driver 2 is provided below the liquid crystal panel 1 and the data signals DS are provided in order from the pixel P of the line position L1 farthest from the source driver 2. However, the source driver 2 may be provided above the liquid crystal panel 1, or the data signals DS may be supplied in order from the pixel P of the line position closest to the source driver 2, and, in these examples, a similar effect to the present example is obtained.
For example, when the source driver 2 is provided below the liquid crystal panel 1 and the data signals DS are supplied in order from the pixel P of the line position Lm closest to the source driver 2, a similar effect to Example 2 is obtained by using a counter that increases the count value with the progress of the line scanning in a vertical scanning period as the delay amount counter 33 (by increasing the count value of the delay amount counter 33 by one each time the count value of the line counter 30 becomes a multiple of the line number for changing a delay amount, and setting the count value of the delay amount counter 33 to an initial value when the count value of the line counter 30 is 0 or a value corresponding to the disconnection position Y).
The embodiments and examples described above are for the purpose of illustration and description and are not intended to be limiting. It will be apparent to those skilled in the art that many variations will be possible in accordance with these examples and descriptions.
While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-126400 | Aug 2022 | JP | national |
