The present application claims priority from Japanese application JP2004-237166 filed on Aug. 17, 2004, the content of which is hereby incorporated by reference into this application.
1. Field of the Invention
The present invention relates to a display device having an electron emission element (electron emission source) for each pixel typified by a field-emission-type image display device, and relates to a substrate (display substrate) for use in the device.
2. Description of the Related Art
Japanese patent literature JP-A-2004-111053 (and its counterpart US 2004/017160) describes a panel (display substrate, sometimes mentioned as FED substrate) for use in a field-emission-type image display device (Field Emission Display).
To achieve increase in size of a screen, a voltage drop in the scan lines needs to be suppressed to reduce unevenness in luminance along the scan lines. For example, in the FED substrate in JP-A-2004-111053, a method for suppressing the voltage drop by broadening the scan lines to reduce a resistance value is considered.
However, when the scan line is broadened, separation or a crack tends to occur easily at a sealing portion using the glass frit due to internal stress in the scan lines, resulting in deterioration in airtightness of the inside of the substrate.
The invention was made in the light of the above circumstance, and an object of the invention is to provide a technique for sealing an internal circuit more securely with the voltage drop in the internal circuit being suppressed in a panel having a connection wiring line to an external circuit.
To solve the above problem, in a display substrate of the invention, a wiring line of the internal circuit and a lead line at the sealing portion are formed in accordance with different specifications respectively. For example, the wiring line of the internal circuit is specified as low resistance, and the lead line at the sealing portion is specified to have a small thickness to the extent of preventing leakage through that sealing portion.
Specifically, the display substrate of the field-emission-type image display device of the invention has scan lines formed within the display substrate, a sealing portion for sealing the inside of the display substrate, and lead lines for connecting the scan lines to an external circuit through the sealing portion; wherein the scan lines are formed to have low resistance to the extent that the voltage drop in the scan lines falls within the allowable range, and thickness of the lead lines at the sealing portion is formed small to the extent that the inside of the display substrate can be sealed.
Moreover, the display substrate of the field-emission-image display device of the invention has the sealing portion for sealing the inside of the display substrate, and the lead lines for connecting the scan lines within the display substrate to the external circuit; wherein at least part of the scan lines are formed from a material having lower resistivity than that of the lead lines at the sealing portion.
Moreover, at least part of the scan lines can be formed using wiring lines having a thickness larger than that of the lead lines at the sealing portion.
Moreover, the display substrate of the field-emission-type image display device of the invention can be one that has the sealing portion for sealing the inside of the display substrate, first wiring lines which form the scan lines within the display substrate and is connected to the external circuit through the sealing portion, and second wiring lines that overlap at least part of the portion of the first wiring lines forming the scan lines and form the scan lines.
Moreover, the display substrate of the field-emission-type image display device of the invention can be one that has the sealing portion for sealing the inside of the display substrate, first wiring lines forming the scan lines within the display substrate, and second wiring lines which overlap at least part of the first wiring lines, form part of the scan lines, and are connected to the external circuit through the sealing portion.
The display substrate described above is incorporated into a display device in a form of a substrate having a main surface of which the inner area (area that may be called display area) has multiple electron emission elements disposed thereon, and wiring lines to be connected to the electron emission elements are formed on the inner area of the main surface of the substrate. The inner area of the main surface of the substrate, particularly an image display area in the display device (display panel) is sealed by a sealing member, and left at a pressure lower than the ambient atmosphere of the display device (so-called, vacuum). Wiring lines (not limited to the scan lines) as a feature of the invention are left in a space kept at the low pressure (for example, 1×10−4 Pa or lower), and connected to the external circuit provided outside the space by the lead lines as a feature of the invention.
Preferred embodiments of a display device of the invention will be described with reference to drawings. While a substrate that exhibits structural features of the display device of the invention is described as “FED substrate” in the following description, the substrate can be provided with a plurality of electron emission elements and wiring lines concerned with driving the elements on its main surface. In other words, even if a substrate in which electrodes or their equivalents for forming an electric field by which electrons are emitted can not be provided due to a shape of the electron emission elements is used, the following aspects can be realized.
The cathode substrate 110 is formed by an insulative substrate such as glass. Data lines 170 and scan lines 160 are provided crosswise on the cathode substrate 110. The data lines 170 are formed from Al or Al alloys. Thickness of the data lines 170 is typically within a range of 100 to 500 nm. Ends of the data lines 170 are connected to a data-line drive circuit (not shown) that is an external circuit.
Each of the scan lines 160 is typically formed from Ag, Au, Cu, and Pd or alloys of them, however, it is preferably formed from Ag in terms of low resistance (small resistivity) and particularly ease in manufacturing. Thickness of the scan lines 160 is typically within a range of 1 to 30 μm, and preferably 5 to 20 μm. Line width of them is typically within a range of 50 to 600 μm. However, the thickness or line width of the scan lines is preferably determined to have a predetermined resistance value such that a voltage drop in the scan lines falls within its allowable range. Each of the scan lines 160 is connected to a scan-line lead line 130 on the cathode substrate 110 at a bonding portion 320.
The scan-line lead lines 130 are wiring lines for connecting the scan lines to the scan-line drive circuit (not shown) that is an external circuit through a sealing portion 310. The scan-line lead lines 130 are typically formed from Al, Cu, Cr or alloys of them; however, they are preferably formed from Al in terms of ease in manufacturing. Thickness of the scan-line lead lines 130 is typically within a range of 100 to 500 nm in terms of perfect sealing at the sealing portion 310.
A cold cathode electron source (not shown) is provided at a position where the data line 170 intersects with the scan line 160. The cold cathode electron source is roughly classified into a field-emission-type electron source such as Spindt-type electron source, surface-conduction-type electron source, and carbon-nanotube-type electron source, and a hot-electron-type electron source such as MIM (Metal-Insulator-Metal) type electron source having a stacked metal/insulator/metal layers and MIS (Metal-Insulator-Semiconductor) type electron source having a stacked metal/insulator/semiconductor layers, and either of the electron sources can be provided. For example, the MIM type electron source, which is disclosed in Japanese patent literatures JP-A-10-153979 and JP-A-2004-111053, may be disposed.
The anode substrate 120 is formed by a transparent glass plate. A black matrix, a phosphor layer and an anode electrode are formed on one surface of the anode substrate 120 and arranged such that the formation surface is opposed to a wiring formation surface of the cathode substrate 110. The black matrix is formed from chromium oxide. The phosphor may comprise, for example, Y2O2S:Eu (P22-R) for red, ZnS:Cu, Al (P22-G) for green, and ZnS:Ag (P22-B) for blue.
A space between the frame glass 150 and the cathode substrate 110 or the anode substrate 120 is sealed using an adhesive 151, 152 such as glass frit such that pressure of the inside 115 of the substrate can be kept at about 10−5 Pa.
Next, a method for manufacturing the FED substrate of the first embodiment is described.
First, the data lines 170 are formed on the cathode substrate (glass substrate) 110 with the electron sources such as MIM electron sources. The data lines can be formed from Al or Al alloys using sputter, photolithography, or etching. The data lines are typically formed to have the thickness within the range of 100 to 500 nm.
Next, as shown in
Next, the scan lines 160 are formed on the cathode substrate 110. A formation method is not particularly limited as long as it can form the scan lines 160. Hereinafter, a method for forming the scan lines using Ag is described.
Here, screen printing is used as shown in
As the Ag paste, paste that can be baked at a temperature lower than an allowable temperature limit of the electron sources provided on the cathode substrate 110 is preferably used. For example, when the MIM electron sources are provided on the cathode substrate 110, since the allowable temperature limit of the MIM electron source is about 430° C., Ag paste that can be baked at 430° C. or lower is preferably used. Specifically, frit-contained XFP5369-50L (manufactured by NAMICS CORPORATION, heating condition: temporal drying; 150° C. for 15 min, and baking; 430° C. for 30 min) can be used.
The Ag wiring lines are typically formed to have a thickness within a range of 1 to 30 μm. In addition, the wiring lines are typically formed to have a line width within a range of 100 to 300 μm.
The screen printing may be performed several times to increase thickness. For example, the Ag paste is printed in first printing and then dried, and then overprinted in second printing and dried, and then baked. According to this, when an Ag wiring line about 7 μm in thickness is obtained in the first printing, an Ag wiring line about 12 μm in thickness can be obtained in the second printing.
Next, as shown in
As the glass frit 151, 152 used for the adhesive, one that can be fused at a temperature lower than the allowable temperature limit of the electron sources is preferably used. For example, when the MIM electron sources are provided on the cathode substrate 110, glass frit that can be fused at 430° C. or lower is preferably used.
Next, the inside 115 of the substrate is evacuated to about 10−5 Pa of pressure of the inside 115 through an exhaust port (not shown) using a vacuum pump, and then sealed.
Hereinbefore, the FED substrate according to the first embodiment has been described.
According to the embodiment, since the scan lines and the lead lines are separately formed, each can be specified differently. That is, since the scan lines can be formed from Ag having low resistance, the voltage drop in the scan lines can be suppressed. On the other hand, since the lead lines have short distance, they can be sufficiently secured to have small thickness. Therefore, even if heating is performed at high temperature to fuse the glass frit, the separation or the crack due to the internal stress can be prevented, there by airtightness at the sealing portion can be improved.
The scan lines can be easily formed by Ag wiring lines using the screen printing having high mass-productivity. The screen printing is advantageous in patterning in a direction perpendicular to the squeeze, but disadvantageous in patterning in a direction diagonal or parallel to the squeeze because inferior application (bleed or run-out) easily occur. In the embodiment, as shown in
In the FED substrate of the first embodiment, the scan-line lead lines 130 were formed by wiring lines of Al in small thickness to secure the airtightness at the sealing portion 310. Moreover, the scan lines 160 were formed by wiring lines of Ag having low resistance to reduce resistance of the scan lines 160. On the contrary, in this embodiment, as shown in figures, the scan-line lead lines 130 extend to an area of scan lines, and forms part of scan lines 1302. To reduce resistance of the scan lines, wiring lines 1602 of Ag having low resistance is overlapped the scan line portion 1302. That is, the scan lines are formed by a combination of the wiring 1302 and the wiring 1602.
The scan-line lead lines 130 partially combined with the scan lines are typically formed from Al, Cu, Cr or alloys of them similarly as the scan-line lead lines of the FED substrate of the first embodiment; however, they are preferably formed from Al in terms of ease in manufacturing. Thickness of the scan-line lead lines 130 is typically within a range of 100 to 500 nm in terms of perfect sealing at the sealing portion 310, and preferably within a range of 200 to 400 nm.
The wiring lines 1602 overlapped the wiring lines 1302 are typically formed from Ag, Au, Cu, Pd or alloys of them, similarly as the scan lines of the FED substrate of the first embodiment. Among them, they are preferably formed from Ag in terms of low resistance and ease in manufacturing. Line width of the wiring lines 1602 is typically within a range of 50 to 600 μm, and thickness of the wiring lines is typically within a range of 1 to 30 μm, and preferably 5 to 20 μm. However, the thickness or line width of the wiring lines 1602 is preferably determined to have a predetermined resistance value such that the voltage drop in the scan lines falls within its allowable range.
Next, a method for manufacturing the FED substrate of the second embodiment is described.
First, the data lines 170 are formed on the cathode substrate (glass substrate) 110 with the electron sources (not shown) such as MIM electron sources, similarly as the case of manufacturing the FED substrate of the first embodiment.
Next, as shown in
Next, to reduce resistance of the scan line portion, the wiring lines of Ag having low resistance are overlapped the scan lines 1302. Here, the screen printing is used as shown in
The Ag wiring is typically formed to have a thickness within a range of 1 to 30 μm. The screen printing may be performed several times to increase thickness similarly as the first embodiment.
Next, as shown in
Next, the inside 115 of the substrate is evacuated to about 10−5 Pa of pressure of the inside 115 through the exhaust port (not shown) using the vacuum pump, and then sealed. In this way, the FED substrate as shown in
Hereinabove, the FED substrate of the second embodiment has been described. According to the embodiment, the scan-line portion and the lead-line portion can be configured in different specifications respectively. That is, the scan lines are formed by wiring lines of Al and wiring lines of Ag that have low resistance and are overlapped on the Al lines. Therefore, the voltage drop on the scan lines can be suppressed. On the other hand, since the lead lines need not be low resistive, the wiring lines of Al can be remained with sufficiently small thickness being secured. Therefore, even if heating is performed at high temperature to fuse the glass frit, the separation or the crack due to the internal stress can be prevented, thereby airtightness at the sealing portion can be improved.
In the FED substrate of the second embodiment, the scan-line lead lines 130 were extended to an area of scan lines, forming part of scan lines 1302. In addition, to reduce resistance of the scan lines, wiring lines 1602 of Ag having low resistance were overlapped on the scan line portion 1302. On the contrary, as shown in
The scan lines 1603 are typically formed from Ag, Au, Cu, Pd or alloys of them, similarly as the scan lines of the FED substrate of the first embodiment. Among them, they are preferably formed from Ag in terms of low resistance and ease in manufacturing. Line width of the wiring lines 1603 is typically within a range of 50 to 600 μm. Thickness of the scan lines 1603 is typically within a range of 1 to 30 μm in the light of decrease in resistance of the scan lines, and preferably 5 to 20 μm. However, the thickness or line width of the scan lines is preferably determined to have a predetermined resistance value such that the voltage drop in the scan lines falls within its allowable range.
The scan-line lead lines 130 partially combined with the scan lines 1303 are typically formed from Al, Cu, Cr or alloys of them similarly as the scan-line lead lines of the FED substrate of the first embodiment; however, they are preferably formed from Al in terms of ease in manufacturing. Thickness of the scan-line lead lines 130 is typically within a range of 100 to 500 nm at the sealing portion 310.
Next, a method for manufacturing the FED substrate of the third embodiment is described.
First, as shown in
Next, the scan lines 1603 are formed by the wiring lines of Ag having low resistance. Here, the screen printing is used as shown in
The Ag wiring is typically formed to have a thickness within a range of 1 to 30 μm. The screen printing may be performed several times to increase thickness similarly as the first embodiment.
Next, as shown in
Next, as shown in
Next, the inside 115 of the substrate is evacuated to about 10−5 Pa of pressure of the inside 115 through the exhaust port (not shown) using the vacuum pump, and then sealed. In this way, the FED substrate as shown in
Hereinabove, the FED substrate of the third embodiment has been described. According to the embodiment, the scan line portion and the lead line portion can be configured in different specifications respectively. That is, part of the scan lines are formed by the wiring lines of Ag having low resistance. Therefore, the voltage drop on the scan lines can be suppressed. On the other hand, since the lead lines need not be low resistive, the wiring lines of Al can be remained with sufficiently small thickness being secured. Therefore, even if heating is performed at high temperature to fuse the glass frit, the separation or the crack due to the internal stress can be prevented, thereby airtightness at the sealing portion can be improved.
In the third embodiment, the scan-line lead lines 130 forming the part of the scan lines may be formed such that the scan lines 160 formed from Ag are partially overlapped as shown in a plane view of
Hereinabove, while description has been made on several embodiments of the invention, the invention is not limited to the embodiments. Various modifications of the embodiments can be made within a scope of the spirit of the invention.
For example, while the scan line portion (or part of it) and scan-line lead-line portion are formed from different materials respectively, they may be formed from the same material as shown in 1304 of
As described above, the thickness or the line width of the scan lines is determined according to the allowable range of the voltage drop in the scan lines. More specifically, it is determined according to the allowable range of the resistance value determined according to the allowable range of the voltage drop. The allowable range of the voltage drop is typically within 0.5 V. For example, when a display screen size is 20 to 32 inches, length of the scan lines is 400 to 720 mm, and the resistance value of the scan lines is made to be 15 to 40 Ω so that the voltage drop falls within its allowable range. When the display screen size is 33 to 50 inches, length of the scan lines is 700 to 1200 mm, and the resistance value of the scan lines is made to be 6 to 15 Ω so that the voltage drop falls within its allowable range. When the display screen size is 51 to 65 inches, length of the scan lines is 1000 to 1500 mm, and the resistance value of the scan lines is made to be 3 to 6 Ω so that the voltage drop falls within its allowable range. The thickness or the line width of the scan lines is adjusted such that the resistance value falls within such resistance value ranges.
In the embodiments, in the process of forming the scan lines by screen printing, frit-contained metal paste (Ag paste) was used to improve adhesion to a base (in the example of
For example, when frit-free Ag paste is used in the FED substrate of the second embodiment (
Such a configuration can be achieved in the following manner. First, frit-contained Ag paste (for example, XFP5369-50L (manufactured by NAMICS CORPORATION)) is applied on a wiring pattern of the scan lines and then subjected to temporal drying. Next, frit-free Ag paste (for example, XFP5369-50L-0 (manufactured by NAMICS CORPORATION, heating condition: temporal drying; 150° C. for 15 min, and baking; 430° C. for 30 min)) is applied by screen printing such that it overlaps the frit-contained Ag paste pattern. The frit-free Ag paste may be optionally overprinted. After that, the Ag paste is dried and then baked.
When the two layers are baked in an overlapped manner in this way, Ag particles are fusion-bonded to one another, thereby contact resistance between the two layers can be reduced.
The invention is not limited to the FED substrate. The invention can be applied to any substrate as long as it has a structure that an internal circuit is sealed from an external circuit, and has wiring lines for connecting the internal circuit to the external circuit.
While we have shown and described several embodiments in accordance with the present invention, it is understood that the same is not limited thereto but is susceptible of numerous changes and modifications as known to those skilled in the art, and we therefore do not wish to be limited to the details shown and described herein but intend to cover all such changes and modifications as are encompassed by the scope of the appended claims.
Number | Date | Country | Kind |
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2004-237166 | Aug 2004 | JP | national |