TECHNICAL FIELD
The present invention relates to a display device.
BACKGROUND ART
In recent years, as a display device replacing a liquid crystal display device, a self-luminous organic electroluminescence (hereinafter also referred to as “EL”) display device using an organic EL element has attracted attention. In this organic EL display device, a flexible organic EL display device in which an organic EL element or the like is formed on a resin substrate layer having flexibility is proposed.
For example, PTL1 describes a large-scale integration (LSI) chip on flexible circuit board in which a spacing unit for maintaining a minimum interval between an LSI terminal and an LSI chip when the LSI chip is mounted is provided in an opening of an insulating film formed as a region for mounting the LSI chip.
CITATION LIST
Patent Literature
SUMMARY OF INVENTION
Technical Problem
In the LSI chip on flexible wiring board described in PTL1, although deflection of the flexible wiring board can be suppressed by the spacing unit, since the spacing unit is disposed straddling the plurality of terminals arranged side by side, the conductive particles forming the anisotropic conductive film may clump together between the spacing unit and a bump of the LSI chip, with the clump of conductive particles disadvantageously forming a connection. In this case, the adjacent terminals may be short-circuited by the connected conductive particles. This shows that there is still room for improvement.
The present invention has been made in view of the above, and an object of the present invention is to suppress short-circuiting between terminals in a chip mounting portion.
Solution to Problem
To achieve the object described above, a display device according to the present invention includes: a flexible substrate layer; a thin film transistor layer provided on the flexible substrate layer; and a light-emitting element layer provided on the thin film transistor layer and including a plurality of light-emitting elements, the plurality of light-emitting elements arrayed corresponding to a plurality of subpixels constituting a display region, respectively, wherein a frame region is provided around the display region, a terminal portion extending in one direction is provided at an end portion of the frame region, a chip mounting portion is provided between the display region and the terminal portion, the display device is provided with a plurality of chip terminals arranged in a row in the chip mounting portion and a plurality of terminal wiring lines corresponding to the plurality of chip terminals, the plurality of terminal wiring lines extending parallel to one another and being electrically connected to the plurality of chip terminals, respectively, and in the chip mounting portion, for at least one chip terminal of the plurality of chip terminals, a chip support body is provided at each terminal wiring line with the chip support body overlapping the terminal wiring line corresponding to the at least one chip terminal or an extension line of the terminal wiring line.
Advantageous Effects of Invention
According to the present invention, short-circuiting between terminals in a chip mounting portion can be suppressed.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a plan view illustrating a schematic configuration of an organic EL display device according to a first embodiment of the present invention.
FIG. 2 is a plan view of a display region of an organic EL display panel constituting the organic EL display device according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view of the display region of the organic EL display panel constituting the organic EL display device according to the first embodiment of the present invention.
FIG. 4 is an equivalent circuit diagram of a thin film transistor layer constituting the organic EL display panel of the organic EL display device according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating an organic EL layer constituting the organic EL display panel of the organic EL display device according to the first embodiment of the present invention.
FIG. 6 is a plan view of a chip mounting portion in a frame region of the organic EL display panel of the organic EL display device according to the first embodiment of the present invention and of the periphery of the chip mounting portion.
FIG. 7 is an enlarged plan view illustrating the chip mounting portion of the frame region of the organic EL display panel of the organic EL display device according to the first embodiment of the present invention.
FIG. 8 is a cross-sectional view of the organic EL display device taken along line VIII-VIII in FIG. 7.
FIG. 9 corresponds to FIG. 6 and is a plan view of the chip mounting portion of the frame region of an organic EL display panel constituting an organic EL display device according to a second embodiment of the present invention and of the periphery of the chip mounting portion.
FIG. 10 corresponds to FIG. 7 and is an enlarged plan view of the chip mounting portion of the frame region of the organic EL display panel constituting the organic EL display device according to the second embodiment of the present invention.
FIG. 11 is a cross-sectional view of the organic EL display device taken along line XI-XI in FIG. 10.
FIG. 12 corresponds to FIG. 7 and is an enlarged plan view of the chip mounting portion of the frame region of an organic EL display panel constituting an organic EL display device according to a third embodiment of the present invention.
FIG. 13 corresponds to FIG. 12 and is a plan view of a modified example of the organic EL display panel constituting the organic EL display device according to the third embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
Embodiments of a technique according to the present invention will be described below in detail with reference to the drawings. Note that the technique according to the present invention is not limited to the embodiments to be described below.
First Embodiment
FIG. 1 to FIG. 8 illustrate a first embodiment of a display device according to the present invention. Note that, in each of the following embodiments, an organic EL display device including an organic EL element will be exemplified as a display device including a light-emitting element. Here, FIG. 1 is a plan view illustrating a schematic configuration of an organic EL display device 70a according to the present embodiment. Further, FIGS. 2 and 3 are a plan view and a cross-sectional view of a display region D of an organic EL display panel 50a constituting the organic EL display device 70a. Further, FIG. 4 is an equivalent circuit diagram of a thin film transistor layer 30 constituting the organic EL display panel 50a. Further, FIG. 5 is a cross-sectional view illustrating an organic EL layer 33 constituting the organic EL display panel 50a. Further, FIG. 6 is a plan view of a chip mounting portion M in a frame region F of the organic EL display panel 50a and of the periphery of the chip mounting portion M. Further, FIG. 7 is an enlarged plan view of the chip mounting portion M in the frame region F of the organic EL display panel 50a. FIG. 8 is a cross-sectional view of the organic EL display device 70a taken along a line VIII-VIII in FIG. 7.
As illustrated in FIG. 1, the organic EL display device 70a includes an organic EL display panel 50a, an integrated circuit chip 60 mounted on the chip mounting portion M described below of the organic EL display panel 50a, and a flexible printed circuit 55 mounted on a terminal portion T described below of the organic EL display panel 50a.
As illustrated in FIG. 1, the organic EL display panel 50a includes, for example, the display region D that is provided in a rectangular shape and in which an image is displayed, and a frame region F provided in a frame-like shape surrounding the display region D. Note that in the present embodiment, the display region D having the rectangular shape has been exemplified, but examples of the rectangular shape include a substantially rectangular shape such as a shape whose sides are arc-shaped, a shape whose corners are arc-shaped, a shape in which a part of a side has a notch and the like.
As illustrated in FIG. 2, a plurality of subpixels P are arrayed in a matrix shape in the display region D. In addition, in the display region D, for example, a subpixel P including a red light-emitting region Lr for displaying a red color, a subpixel P including a green light-emitting region Lg for displaying a green color, and a subpixel P including a blue light-emitting region Lb for displaying a blue color are provided adjacent to one another, as illustrated in FIG. 2. Note that one pixel is configured by, for example, three adjacent subpixels P including the red light-emitting region Lr, the green light-emitting region Lg, and the blue light-emitting region Lb in the display region D.
The terminal portion T is provided at a lower end portion of the frame region F in FIG. 1 in such a manner as to extend in one direction (lateral direction in the diagram). Further, as illustrated in FIG. 1, the chip mounting portion M is provided between the display region D and the terminal portion T in the frame region F so as to extend in one direction (lateral direction in the diagram). As illustrated in FIG. 1, the chip mounting portion M is provided in a rectangular shape in a plan view so as that the long sides extend in the extending direction of the terminal portion T.
As illustrated in FIG. 3, the organic EL display panel 50a includes a flexible substrate layer 10, a thin film transistor (hereinafter, also referred to as a TFT) layer 30 provided on the flexible substrate layer 10, an organic EL element layer 40 provided on the TFT layer 30 as a light-emitting element layer, and a sealing film 45 provided covering the organic EL element layer 40.
The flexible substrate layer 10 is formed, for example, of a polyimide resin and has flexibility. In the present embodiment described herein, the flexible substrate layer 10 made of a resin such as polyimide resin, but the flexible substrate layer 10 may be made of metal in the form of a metal film, a thin metal plate, or the like.
As illustrated in FIG. 3, the TFT layer 30 includes a base coat film 11 provided on the flexible substrate layer 10, a plurality of first TFTs 9a, a plurality of second TFTs 9b (see FIG. 4), a plurality of third TFTs 9c, and a plurality of capacitors 9d provided on the base coat film 11, and the first flattening film 19a and the second flattening film 21a sequentially provided on each of the first TFTs 9a, each of the second TFTs 9b, each of the third TFTs 9c, and each of the capacitors 9d.
In the TFT layer 30, as illustrated in FIG. 3, on the flexible substrate layer 10, the base coat film 11, a semiconductor pattern layer such as a semiconductor layer 12a described below, a gate insulating film 13, a first wiring line layer such as a gate line 14g described below, a first interlayer insulating film 15, a second wiring line layer such as an upper conductive layer 16c described below, a second interlayer insulating film 17, a third wiring line layer such as a source line 18f described below, a first flattening film 19a, a fourth wiring line layer such as a power source line 20a, and a second flattening film 21a are layered in order. For example, each of the base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 is composed of a single-layer film or a layered film of an inorganic insulating film of silicon nitride, silicon oxide, silicon oxynitride, or the like.
As illustrated in FIGS. 2 and 4, in the TFT layer 30, a plurality of gate lines 14g are provided as the first wiring line layer so as to extend parallel to each other in a lateral direction in the drawings. In addition, in the TFT layer 30, as illustrated in FIGS. 2 and 4, a plurality of light emission control lines 14e are provided as the first wiring line layer so as to extend parallel to each other in the lateral direction in the drawings. Note that, as illustrated in FIG. 2, each of the light emission control lines 14e is provided adjacent to a corresponding one of the gate lines 14g. In the TFT layer 30, as illustrated in FIGS. 2 and 4, a plurality of the source lines 18f are provided as the third wiring line layer in such a manner as to extend parallel to each other in a longitudinal direction in the drawings. As illustrated in FIG. 3, in the TFT layer 30, the power source line 20a is provided in a lattice pattern as the fourth wiring line layer between the first flattening film 19a and the second flattening film 21a. In addition, in the TFT layer 30, as illustrated in FIG. 4, each subpixel P includes the first TFT 9a, the second TFT 9b, the third TFT 9c, and the capacitor 9d.
As illustrated in FIG. 4, the first TFT 9a is electrically connected to the corresponding gate line 14g, the corresponding source line 18f, and the corresponding second TFT 9b in each subpixel P. Additionally, as illustrated in FIG. 3, the first TFT 9a includes a semiconductor layer 12a, a gate insulating film 13, a gate electrode 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, and a source electrode 18a and a drain electrode 18b, which are sequentially provided on the base coat film 11. Here, as illustrated in FIG. 3, the semiconductor layer 12a is provided in an island shape on the base coat film 11, and includes a channel region, a source region, and a drain region, as described below. Additionally, as illustrated in FIG. 3, the gate insulating film 13 is provided so as to cover the semiconductor layer 12a. Additionally, as illustrated in FIG. 3, the gate electrode 14a is provided on the gate insulating film 13 so as to overlap with the channel region of the semiconductor layer 12a. Additionally, as illustrated in FIG. 3, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially provided so as to cover the gate electrode 14a. Additionally, as illustrated in FIG. 3, the source electrode 18a and the drain electrode 18b are separated from each other on the second interlayer insulating film 17. Additionally, as illustrated in FIG. 3, the source electrode 18a and the drain electrode 18b are electrically connected to the source region and the drain region of the semiconductor layer 12a, respectively, via each contact hole formed in a layered film including the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17.
As illustrated in FIG. 4, the second TFT 9b is electrically connected to the corresponding first TFT 9a, the corresponding power source line 20a, and the corresponding third TFT 9c in each subpixel P. Note that the second TFT 9b has substantially the same structure as the first TFT 9a and the third TFT 9c to be described later.
As illustrated in FIG. 4, the third TFT 9c is electrically connected to the corresponding second TFT 9b, a first electrode 31a of a corresponding organic EL element 35 described later, and the corresponding light emission control line 14e in each subpixel P. Additionally, as illustrated in FIG. 3, the third TFT 9c includes a semiconductor layer 12b, the gate insulating film 13, a gate electrode 14b, the first interlayer insulating film 15, the second interlayer insulating film 17, and a source electrode 18c and a drain electrode 18d, which are sequentially provided on the base coat film 11. Here, as illustrated in FIG. 3, the semiconductor layer 12b is provided in an island shape on the base coat film 11, and includes a channel region, a source region, and a drain region, as with the semiconductor layer 12a. Additionally, as illustrated in FIG. 3, the gate insulating film 13 is provided so as to cover the semiconductor layer 12b. Additionally, as illustrated in FIG. 3, the gate electrode 14b is provided on the gate insulating film 13 so as to overlap with the channel region of the semiconductor layer 12b. Additionally, as illustrated in FIG. 3, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially provided so as to cover the gate electrode 14b. Additionally, as illustrated in FIG. 3, the source electrode 18c and the drain electrode 18d are separated from each other on the second interlayer insulating film 17. Additionally, as illustrated in FIG. 3, the source electrode 18c and the drain electrode 18d are electrically connected to the source region and the drain region of the semiconductor layer 12b, respectively, via each contact hole formed in a layered film including the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17.
Note that, in the present embodiment, the first TFT 9a, the second TFT 9b, and the third TFT 9c of a top gate type are exemplified, but the first TFT 9a, the second TFT 9b, and the third TFT 9c may be of a bottom gate type.
As illustrated in FIG. 4, the capacitor 9d is electrically connected to the corresponding first TFT 9a and the corresponding power source line 20a in each subpixel P. Here, the capacitor 9d includes, as illustrated in FIG. 3, a lower conductive layer 14c provided as the first wiring line layer, the first interlayer insulating film 15 provided so as to cover the lower conductive layer 14c, and the upper conductive layer 16c provided, as the second wiring line layer, on the first interlayer insulating film 15 so as to overlap with the lower conductive layer 14c. Note that the upper conductive layer 16c is electrically connected to the power source line 20a via a contact hole (not illustrated) formed in the second interlayer insulating film 17 and the first flattening film 19a.
The first flattening film 19a and the second flattening film 21a have a flat surface in the display region D, and are formed of, for example, an organic resin material such as a polyimide resin or an acrylic resin, or a polysiloxane-based spin on glass (SOG) material. Here, as illustrated in FIG. 3, between the first flattening film 19a and the second flattening film 21a, a relay electrode 20b is provided as the fourth wiring line layer in addition to the power source line 20a described above.
The organic EL element layer 40 includes a plurality of the first electrodes 31a, a common edge cover 32a, a plurality of the organic EL layers 33, and a common second electrode 34 provided in that order corresponding to the plurality of subpixels P. Here, in each of the subpixels P, the first electrode 31a, the organic EL layer 33, and the second electrode 34 constitute the organic EL element 35 (see FIG. 4), and in the organic EL element layer 40, a plurality of the organic EL elements 35 are arranged in a matrix shape.
As illustrated in FIG. 3, the plurality of first electrodes 31a are provided in a matrix shape on the second flattening film 21a so as to correspond to the plurality of subpixels P. As illustrated in FIG. 3, the first electrode 31a is electrically connected to the drain electrode 18d of each third TFT 9c via a contact hole formed in the first flattening film 19a, the relay electrode 20b, and a contact hole formed in the second flattening film 21a. Additionally, the first electrode 31a has a function to inject a hole (positive hole) into each of the organic EL layers 33. Additionally, the first electrode 31a is preferably formed of a material having a high work function to improve hole injection efficiency into the organic EL layer 33. Here, examples of a material constituting the first electrode 31a include a metal material such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), tin (Sn) and the like. Examples of the material of the first electrode 31a also include an alloy such as astatine (At)/astatine oxide (AtO2). Further, the material constituting the first electrode 31a may be, for example, an electrically conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO) and the like. Additionally, the first electrode 31a may be formed by layering a plurality of layers including any of the materials described above. Note that examples of compound materials having a high work function include indium tin oxide (ITO) and indium zinc oxide (IZO).
As illustrated in FIG. 3, the edge cover 32a is provided in a lattice pattern, and covers a peripheral end portion of each of the first electrodes 31a. The edge cover 32a is formed of, for example, an organic resin material such as a polyimide resin or an acrylic resin, or a polysiloxane-based SOG material.
As illustrated in FIG. 3, the plurality of organic EL layers 33 are disposed on each of the first electrodes 31a, and provided in a matrix shape and correspond to the plurality of subpixels P. Here, as illustrated in FIG. 5, each of the organic EL layers 33 includes a hole injection layer 1, a hole transport layer 2, a light-emitting layer 3, an electron transport layer 4, and an electron injection layer 5, which are sequentially provided on the first electrode 31a.
The hole injection layer 1 is also referred to as an anode electrode buffer layer, and has a function to reduce an energy level difference between the first electrode 31a and the organic EL layer 33 and to improve hole injection efficiency from the first electrode 31a into the organic EL layer 33. Here, examples of materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.
The hole transport layer 2 has a function to improve hole transport efficiency from the first electrode 31a to the organic EL layer 33. Here, examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.
The light-emitting layer 3 is a region where, when a voltage is applied by the first electrode 31a and the second electrode 34, a positive bole and an electron are injected from the first electrode 31a and the second electrode 34, respectively, and the positive hole and the electron are recombined. Here, the light-emitting layer 3 is formed of a material having high luminous efficiency. Moreover, examples of materials constituting the light-emitting layer 3 include metal oxinoid compounds (8-hydroxyquinoline metal complexes), naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinyl acetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, styrylamine derivatives, bisstyrylbenzene derivatives, trisstyrylbenzene derivatives, perylene derivatives, perinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, aquidine derivatives, phenoxazone, quinacridone derivatives, rubrene, poly-p-phenylenevinylene, polysilane, and the like.
The electron transport layer 4 has a function of facilitating migration of electrons to the light-emitting layer 3 efficiently. Here, examples of materials constituting the electron transport layer 4 include oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silole derivatives, and metal oxinoid compounds, as organic compounds.
The electron injection layer 5 functions to reduce an energy level difference between the second electrode 34 and the organic EL layer 33 to thereby improve the efficiency of electron injection into the organic EL layer 33 from the second electrode 34, and this function allows the drive voltage of the organic EL element to be reduced. Note that the electron injection layer 5 is also referred to as a cathode electrode buffer layer. Here, examples of materials constituting the electron injection layer 5 include inorganic alkaline compounds, such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), and barium fluoride (BaF2), aluminum oxide (Al2O3), and strontium oxide (SrO).
The second electrode 34 is provided on the plurality of organic EL layers 33 so as to be common to the plurality of subpixels P, that is, the second electrode 34a is provided to cover each of organic EL layers 33 and the edge cover 32a, as illustrated in FIG. 3. Further, the second electrode 34 functions to inject electrons into the organic EL layer 33. Further, the second electrode 34 is preferably formed of a material having a low work function to improve the efficiency of electron injection into the organic EL layer 33. Here, examples of a material constituting the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). Further, the second electrode 34 may be formed of alloy such as magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), astatine (At)/astatine oxide (AtO2), lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), and lithium fluoride (LiF)/calcium (Ca)/aluminum (Al). Further, the second electrode 34 may be formed of an electrically conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). Further, the second electrode 34 may be formed by layering a plurality of layers formed of any of the materials described above. Note that examples of materials having a low work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), and lithium fluoride (LiF)/calcium (Ca)/aluminum (Al).
As illustrated in FIG. 3, the sealing film 40 is provided to cover the second electrode 34, and includes a first inorganic sealing film 41, an organic sealing film 42, and a second inorganic sealing film 43 sequentially layered on the second electrode 34, and has a function to protect the organic EL layer 33 of the organic EL element 35 from moisture and oxygen. Here, the first inorganic sealing film 41 and the second inorganic sealing film 43 include, for example, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, and a silicon oxynitride film. Additionally, the organic sealing film 42 is made of, for example, an organic resin material such as an acrylic resin, an epoxy resin, a silicone resin, a polyurea resin, a parylene resin, a polyimide resin, and a polyamide resin. Note that in the frame region F of the organic EL display panel 50a, a first dam wall for suppressing the spread of ink corresponding to the organic sealing film 42 is provided in a frame-like shape surrounding the display region D, and a second dam wall is provided in a frame-like shape surround the first dam wall.
As illustrated in FIG. 6, the organic EL display panel 50a includes, in the chip mounting portion M of the frame region F, an under-chip circuit portion C provided in a rectangular shape extending in the lateral direction in the diagram, a plurality of output-side terminal wiring lines 18tc and a plurality of output-side terminal wiring lines 18td provided extending parallel to one another on the display region D side (upper side in the diagram) of the under-chip circuit portion C, and a plurality of input-side terminal wiring lines 18te provided extending parallel to one another on the terminal portion T side (lower side in the diagram) of the under-chip circuit portion C. As illustrated in FIGS. 6 and 7, the plurality of output-side terminal wiring lines 18tc and the plurality of output-side terminal wiring lines 18td are alternately provided in the extending direction (lateral direction in the diagram) of the chip mounting portion M. Note that the output-side terminal wiring lines 18te, the output-side terminal wiring lines 18td, and the input-side terminal wiring lines 18te are provided as the third wiring line layer.
As illustrated in FIG. 6, the organic EL display panel 50a includes, in the chip mounting portion M of the frame region F, a plurality of first output terminals 20c provided on the display region D side (upper side in the diagram) arranged in a row as a chip terminal on the display region D side of the under-chip circuit portion C, a plurality of second output terminals 20d provided on the terminal portion T side (lower side in the diagram) arranged in a row as a chip terminal on the display region D side of the under-chip circuit portion C, and a plurality of input terminals 20e arranged in a row as a chip terminal on the terminal portion T side (lower side in the diagram) of the under-chip circuit portion C. As illustrated in FIGS. 6 and 7, the plurality of first output terminals 20c and the plurality of second output terminals 20d are provided in a zig-zag shape in the extending direction (lateral direction in the diagram) of the chip mounting portion M. Note that the first output terminals 20c, the second output terminals 20d, and the input terminals 20e are provided as the fourth wiring line layer. As illustrated in FIG. 8, the plurality of first output terminals 20c are layered on the plurality of output-side terminal wiring lines 18tc and are electrically connected to the plurality of output-side terminal wiring lines 18tc. Also, the plurality of second output terminals 20d are layered on the plurality of output-side terminal wiring lines 18td and are electrically connected to the plurality of output-side terminal wiring lines 18td. The plurality of input terminals 20e are layered on the plurality of input-side terminal wiring lines 18te and are electrically connected to the plurality of input-side terminal wiring lines 18te.
As illustrated in FIG. 6, the organic EL display panel 50a includes, in the chip mounting portion M of the frame region F, for each chip terminal including the plurality of first output terminals 20c, the plurality of second output terminals 20d, and the plurality of input terminals 20e, a chip support body Sa is provided in an island shape at each terminal wiring line overlapping the output-side terminal wiring line 18tc, the output-side terminal wiring line 18td, and the input-side terminal wiring line 18te corresponding to the chip terminal or an extension line E of the terminal wiring line. As illustrated in FIG. 8, the chip support body Sa includes a lower resin layer 19b formed of the same material as the first flattening film 19a in the same layer and an upper resin layer 21b provided on the lower resin layer 19b and formed of the same material as the second flattening film 21a in the same layer. As illustrated in FIGS. 6 and 7, for each first output terminal 20c, the chip support body Sa is provided on the display region D side (upper side in the diagram) of the first output terminal 20c, and for each second output terminal 20d, the chip support body Sa is provided on the terminal portion T side (lower side in the diagram) of the second output terminal 20d. Also, as illustrated in FIG. 6, a pair of the chip support bodies Sa are provided for each input terminal 20e with the pair of chip support bodies Sa sandwiching the input terminal 20e. In the chip support body arrangement example according to the present embodiment described above, the chip support body Sa is provided for each chip terminal. However, the chip support body Sa may be provided for at least one of a plurality of chip terminals.
As illustrated in FIG. 8, a plurality of bumps 61 are provided on the back surface of the integrated circuit chip 60. As illustrated in FIG. 7, the plurality of chip terminals including the plurality of first output terminals 20c, the plurality of second output terminals 20d, and the plurality of input terminals 20e provided in the chip mounting portion M of the frame region F of the organic EL display panel 50a are provided so as to correspond to the plurality of bumps 61. In addition, as illustrated in FIGS. 7 and 8, the plurality of chip terminals (the first output terminals 20c, the second output terminals 20d, and the input terminals 20e) and the plurality of bumps 61 are interposed by an anisotropic conductive film 65 and specifically are electrically connected to one another via the conductive particles 64 in the anisotropic conductive film 65. As illustrated in FIG. 8, the anisotropic conductive film 65 includes, for example, a resin material 63 made of a thermosetting resin and the conductive particles 64 dispersed in the resin material 63.
The flexible printed circuit (FPC) 55 is mounted at the terminal portion T via the anisotropic conductive film 65.
In the organic EL display device 70a described above, in each of the subpixels P, by inputting a gate signal to the first TFT 9a via the gate line 14g, the first TFT 9a is turned on. When a predetermined voltage corresponding to a source signal is written to the gate electrode of the second TFT 9b and the capacitor 9d via the source line 18f, and a light emission control signal is input to the third TFT 9c via the light emission control line 14e, the third TFT 9c is turned on. Then, by supplying a current corresponding to the gate voltage of the second TFT 9b from the power source line 20a to the organic EL layer 33, the light-emitting layer 3 of the organic EL layer 33 emits light to display an image. Note that, in the organic EL display device 70a, even when the first TFT 9a is turned off, the gate voltage of the second TFT 9b is held by the capacitor 9d, and thus, light emission by the light-emitting layer 3 is maintained in each of the subpixels P until a gate signal of the next frame is input.
Next, a method for manufacturing the organic EL display device 70a according to the present embodiment will be described. Note that the method for manufacturing an organic EL display device according to the present embodiment includes a TFT layer forming step, an organic EL display panel preparing step including an organic EL element layer forming step and a sealing film forming step, and a mounting step.
Organic EL Display Panel Preparing Step
TFT Layer Forming Step
First, for example, a non-photosensitive polyimide resin (having a thickness of approximately 10 μm) is applied onto a glass substrate, and then the applied film is prebaked and postbaked to form the flexible substrate layer 10.
Thereafter, a silicon oxide film (having a thickness of approximately 500 nm) and a silicon nitride film (having a thickness of approximately 100 nm) are sequentially formed, for example, by a plasma CVD method, on the substrate surface formed with the flexible substrate layer 10 to form the base coat film 11.
Subsequently, for example, an amorphous silicon film (having a thickness of approximately 50 nm) is formed on the substrate surface formed with the base coat film 11, by plasma CVD, the amorphous silicon film is crystallized by laser annealing or the like to form a semiconductor film of a polysilicon film, and then, the semiconductor film is patterned to form a semiconductor pattern layer such as the semiconductor layer 12a or the like.
Thereafter, an inorganic insulating film (approximately 100 nm) such as a silicon oxide film is formed on the substrate surface formed with the semiconductor pattern layer, for example, by plasma CVD, to form the gate insulating film 13 to cover the semiconductor layer 12a and the like.
Also, a molybdenum film (having a thickness of approximately 250 nm) is formed by, for example, a sputtering method, on the substrate surface formed with the gate insulating film 13. Then, the molybdenum film is patterned to form the first wiring line layer of the gate line 14g and the like.
Subsequently, using the first wiring line layer as a mask, impurity ions are doped to form an intrinsic region and a conductor region in the semiconductor layer 12a and the like.
Thereafter, a silicon nitride film (having thickness of approximately 100 nm) is formed on the substrate surface formed with the semiconductor layers 12a and the like with the intrinsic region and the conductor region, for example, by plasma CVD to form the first interlayer insulating film 15.
Subsequently, a molybdenum film (having a thickness of approximately 250 nm) is formed by, for example, a sputtering method, on the substrate surface formed with the first interlayer insulating film 15, and then, the molybdenum film is patterned to form the second wiring line layer of the upper conductive layer 16c and the like.
Furthermore, a silicon oxide film (having a thickness of approximately 300 nm) and a silicon nitride film (having a thickness of approximately 200 nm) are formed in order, by, for example, a plasma CVD method, on the substrate surface formed with the second wiring line layer to form the second interlayer insulating film 17.
Thereafter, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are patterned to form a contact hole.
Also, a titanium film (having a thickness of approximately 50 nm), an aluminum film (having a thickness of approximately 600 nm), and a titanium film (having a thickness of approximately 50 nm) are sequentially formed by, for example, a sputtering method, on the substrate surface formed with the above-described contact hole, and then, a metal layered film thereof is patterned to form the third wiring line layer of the source line 18f and the like.
Further, a photosensitive polyimide resin (having a thickness of approximately 2.5 μm) is applied, by, for example, a spin coating method or a slit coating method, onto the substrate surface formed with the third wiring line layer, and then the applied film is prebaked, exposed, developed, and postbaked to form the first flattening film 19a, the lower resin layer 19b, and the like.
Thereafter, a titanium film (having a thickness of approximately 50 nm), an aluminum film (having a thickness of approximately 600 nm), a titanium film (having thickness of approximately 50 nm) are sequentially formed on the substrate surface formed with the first flattening film 19a and the like by, for example, a sputtering method, and then, a metal layered film thereof is patterned to form the fourth wiring line layer of the power source line 20a.
Finally, a polyimide-based photosensitive resin film (having a thickness of approximately 2.5 μm) is applied onto the substrate surface formed with the fourth wiring line layer, for example, by spin coating or slit coating, and then, the applied film is prebaked, exposed, developed, and postbaked to form the second flattening film 21a, the upper resin layer 21b, and the like.
As described above, the TFT layer 30 can be formed.
Organic EL Element Layer Forming Step
On the second flattening film 21a of the TFT layer 30 formed in the TFT layer forming step described above, the first electrode 31a, the edge cover 32a, the organic EL layer 33 (the hole injection layer 1, the hole transport layer 2, the light-emitting layer 3, the electron transport layer 4, and the electron injection layer 5), and the second electrode 34 are formed using a known method to form the organic EL element layer 40.
Sealing Film Forming Step
First, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD on a substrate surface formed with the organic EL element layer 40 formed in the organic EL element layer forming step by using a mask to form the first inorganic sealing film 41.
Next, on the substrate surface formed with the first inorganic scaling film 41, a film made of an organic resin material such as acrylic resin is formed by, for example, using an ink-jet method to form the organic sealing film 42.
Next, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD on the substrate surface formed with the organic sealing film 42 by using a mask to form the second inorganic sealing film 43, thereby forming the sealing film 45.
Also, after a protective sheet (not illustrated) on the front surface side is applied to the substrate surface formed with the scaling film 45, the glass substrate is peeled off from the lower surface of the flexible substrate layer 10 by irradiating laser light from the glass substrate side of the flexible substrate layer 10, and then a protective sheet (not illustrated) on the back surface side is applied to the lower surface of the flexible substrate layer 10 from which the glass substrate has been peeled off.
The organic EL display panel 50a can be prepared as described above.
Mounting Step
First, the protective sheet on the front surface side of the organic EL display panel 50a prepared in the organic EL display panel preparing step is partially removed by, for example, irradiating the protective sheet with laser light to expose the chip mounting portion M and the terminal portion T.
Subsequently, the anisotropic conductive film 65 is temporarily fixed to the chip mounting portion M and the terminal portion T.
Further, after the integrated circuit chip 60 and the flexible printed circuit 55 are aligned with the chip mounting portion M and the terminal portion T, respectively, a compression bonding tool is used to press the integrated circuit chip 60 and the flexible printed circuit 55 and mount the integrated circuit chip 60 and the flexible printed circuit 55 on the chip mounting portion M and the terminal portion T, respectively.
Thus, the organic EL display device 70a of the present embodiment can be manufactured as described above.
As described above, according to the organic EL display device 70a of the present embodiment, in the chip mounting portion M of the frame region F, for each chip terminal including the plurality of first output terminals 20c, the plurality of second output terminals 20d, and the plurality of input terminals 20e, the chip support body Sa is provided in an island shape at each terminal wiring line overlapping the output-side terminal wiring line 18tc, the output-side terminal wiring line 18td, and the input-side terminal wiring line 18te corresponding to the chip terminal or the extension line E of the terminal wiring line. This makes it difficult for the conductive particles 64 to clump together between chip support bodies Sa and the adjacently-disposed bumps 61. Thus, short-circuiting between the adjacent terminals due to the conductive particles 64 forming a connection can be suppressed, and short-circuiting between the terminals in the chip mounting portion M can be suppressed.
Also, according to the organic EL display device 70a of the present embodiment, in the chip mounting portion M of the frame region F, the chip support bodies Sa are provided at or near the chip terminals including the plurality of first output terminals 20c, the plurality of second output terminals 20d, and the plurality of input terminals 20e. Thus, deflection of the organic EL display panel 50a at or near the bumps 61 of the integrated circuit chip 60 in the mounting step can be suppressed. In this manner, cracking in the base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 of the organic EL display panel SOa can be suppressed, and disconnection of the output-side terminal wiring lines 18tc, the output-side terminal wiring lines 18td, and the input-side terminal wiring lines 18te provided on the second interlayer insulating film 17 can be suppressed.
Second Embodiment
FIGS. 9 to 11 illustrate a second embodiment of a display device according to the present invention. Here, FIG. 9 corresponds to FIG. 6 and is a plan view of the chip mounting portion M of the frame region F of an organic EL display panel 50b constituting an organic EL display device 70b according to the present embodiment and of the periphery of the chip mounting portion M. Also, FIG. 10 corresponds to FIG. 7 and is an enlarged plan view of the chip mounting portion M of the frame region F of the organic EL display panel 50b constituting the organic EL display device 70b according to the present embodiment. Additionally, FIG. 11 is a cross-sectional view of the organic EL display device 70b taken along line XI-XI in FIG. 10. Note that, in each of the following embodiments, the same portions as those in FIG. 1 to FIG. 8 are denoted by the same reference signs, and the detailed description of these portions are omitted.
In the first embodiment described above, the organic EL display device 70a includes the dual-layer-structured chip support body Sa. However, in the present embodiment described below, the organic EL display device 70b include a triple-layer-structured chip support body Sb.
As with the organic EL display device 70a of the first embodiment, the organic EL display device 70b includes an organic EL display panel 50b, the integrated circuit chip 60 mounted on the chip mounting portion M of the organic EL display panel 50b, and the flexible printed circuit 55 mounted on the terminal portion T of the organic EL display panel 50b.
As with the organic EL display panel 50a of the first embodiment described above, the organic EL display panel 50b includes the display region D provided in a rectangular shape in which an image is displayed and the frame region F provided in a frame-like shape in a periphery of the display region D.
As with the organic EL display panel 50a of the first embodiment described above, the organic EL display panel 50b includes the flexible substrate layer 10, the TFT layer 30 provided on the flexible substrate layer 10, the organic EL element layer 40 provided on the TFT layer 30, and the sealing film 45 provided covering the organic EL element layer 40.
As illustrated in FIG. 9, the organic EL display panel 50b includes, in the chip mounting portion M of the frame region F, the under-chip circuit portion C provided in a rectangular shape extending in the lateral direction in the diagram, the plurality of output-side terminal wiring lines 18tc and the plurality of output-side terminal wiring lines 18td provided extending parallel to one another on the display region D side (upper side in the diagram) of the under-chip circuit portion C, and the plurality of input-side terminal wiring lines 18te provided extending parallel to one another on the terminal portion T side (lower side in the diagram) of the under-chip circuit portion C.
As illustrated in FIG. 9, the organic EL display panel 50b includes, in the chip mounting portion M of the frame region F, a plurality of first output terminals 20f provided on the display region D side (upper side in the diagram) arranged in a row as a chip terminal on the display region D side of the under-chip circuit portion C, a plurality of second output terminals 20g provided on the terminal portion T side (lower side in the diagram) arranged in a row as a chip terminal on the display region D side of the under-chip circuit portion C, and a plurality of input terminals 20h arranged in a row as a chip terminal on the terminal portion T side (lower side in the diagram) of the under-chip circuit portion C. As illustrated in FIGS. 9 and 10, the plurality of first output terminals 20f and the plurality of second output terminals 20g are provided in a zig-zag shape in the extending direction (lateral direction in the diagram) of the chip mounting portion M. Note that the first output terminals 20f, the second output terminals 20g, and the input terminals 20h are provided as the fourth wiring line layer. As illustrated in FIG. 11, the plurality of first output terminals 20f are layered on the plurality of output-side terminal wiring lines 18tc and are electrically connected to the plurality of output-side terminal wiring lines 18tc. Also, the plurality of second output terminals 20g are layered on the plurality of output-side terminal wiring lines 18td and are electrically connected to the plurality of output-side terminal wiring lines 18td. The plurality of input terminals 20h are layered on the plurality of input-side terminal wiring lines 18te and are electrically connected to the plurality of input-side terminal wiring lines 18te.
As illustrated in FIG. 9, the organic EL display panel 50b includes, in the chip mounting portion M of the frame region F, for each chip terminal including the plurality of first output terminals 20f, the plurality of second output terminals 20g, and the plurality of input terminals 20h, the chip support body Sb is provided in an island shape at each terminal wiring line overlapping the output-side terminal wiring line 18tc, the output-side terminal wiring line 18td, and the input-side terminal wiring line 18te corresponding to the chip terminal. As illustrated in FIG. 11, the chip support body Sb includes the lower resin layer 19b formed of the same material as the first flattening film 19a in the same layer, a metal layer 20fe provided on the lower resin layer 19b, and the upper resin layer 21b provided on the metal layer 20fe and formed of the same material as the second flattening film 21a in the same layer. The metal layer 20fe is an extension portion of the first output terminal 20f. As illustrated in FIGS. 9 and 10, for each first output terminal 20f, the chip support body Sb is provided on the display region D side (upper side in the diagram) of the first output terminal 20f, and for each second output terminal 20g, the chip support body Sb is provided on the terminal portion T side (lower side in the diagram) of the second output terminal 20g. As illustrated in FIG. 9, for each input terminal 20, the chip support body Sb is provided as a pair on the display region D side (upper side in the diagram) and the terminal portion T side (lower side in the diagram) of the input terminal 20h. In the chip support body arrangement example according to the present embodiment described above, the chip support body Sb is provided for each chip terminal. However, the chip support body Sb may be provided for at least one of a plurality of chip terminals.
As illustrated in FIG. 11, the plurality of bumps 61 are provided on the back surface of the integrated circuit chip 60. As illustrated in FIG. 10, the plurality of chip terminals including the plurality of first output terminals 20f, the plurality of second output terminals 20g, and the plurality of input terminals 20h provided in the chip mounting portion M of the frame region F of the organic EL display panel 50b are provided so as to correspond to the plurality of bumps 61. In addition, as illustrated in FIGS. 10 and 11, the plurality of chip terminals (the first output terminals 20f, the second output terminals 20g, and the input terminals 20h) and the plurality of bumps 61 are interposed by the anisotropic conductive film 65 and specifically are electrically connected to one another via the conductive particles 64 in the anisotropic conductive film 65.
As with the organic EL display device 70a of the first embodiment described above, the organic EL display device 70b described above has flexibility and is configured to display an image by causing the light-emitting layer 3 of the organic EL layer 33 to emit light as appropriate via the first TFT 9a, the second TFT 9b, and the third TFT 9c in each subpixel P.
The organic EL display device 70b of the present embodiment can be manufactured by modifying the pattern shapes of the fourth wiring line layer in the manufacturing method for the organic EL display device 70a of the first embodiment.
As described above, according to the organic EL display device 70b of the present embodiment, in the chip mounting portion M of the frame region F, for each chip terminal including the plurality of first output terminals 20f, the plurality of second output terminals 20g, and the plurality of input terminals 20h, the chip support body Sb is provided in an island shape at each terminal wiring line overlapping the output-side terminal wiring line 18tc, the output-side terminal wiring line 18td, and the input-side terminal wiring line 18te corresponding to the chip terminal. This makes it difficult for the conductive particles 64 to clump together between chip support bodies Sb and the adjacently-disposed bumps 61. Thus, short-circuiting between the adjacent terminals due to the conductive particles 64 forming a connection can be suppressed, and short-circuiting between the terminals in the chip mounting portion M can be suppressed.
In addition, according to the organic EL display device 70b of the present embodiment, the height of the chip support body Sb is increased by an amount corresponding to the thickness of the first output terminal 20f, the second output terminal 20g, and the input terminal 20h. This allows the dispersion effect of the conductive particles 64 in the anisotropic conductive film 65 to be increased. This makes it more difficult for the conductive particles 64 to clump together between chip support bodies Sb and the adjacently-disposed bumps 61. Thus, short-circuiting between the adjacent terminals due to the conductive particles 64 forming a connection can be further suppressed, and short-circuiting between the terminals in the chip mounting portion M can be further suppressed.
Also, according to the organic EL display device 70b of the present embodiment, in the chip mounting portion M of the frame region F, the chip support bodies Sb are provided at or near the chip terminals including the plurality of first output terminals 20f, the plurality of second output terminals 20g, and the plurality of input terminals 20h. Thus, deflection of the organic EL display panel 50b at or near the bumps 61 of the integrated circuit chip 60 in the mounting step can be suppressed. In this manner, cracking in the base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 of the organic EL display panel 50b can be suppressed, and disconnection of the output-side terminal wiring lines 18tc, the output-side terminal wiring lines 18td, and the input-side terminal wiring lines 18te provided on the second interlayer insulating film 17 can be suppressed.
Also, according to the organic EL display device 70b of the present embodiment, the height of the chip support body Sb is increased by an amount corresponding to the thickness of the first output terminal 20f, the second output terminal 20g, and the input terminal 20h. Thus, deflection of the organic EL display panel 50b at or near the bumps 61 of the integrated circuit chip 60 in the mounting step can be further suppressed. In this manner, cracking in the base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 of the organic EL display panel 50b can be further suppressed, and disconnection of the output-side terminal wiring lines 18tc, the output-side terminal wiring lines 18td, and the input-side terminal wiring lines 18te provided on the second interlayer insulating film 17 can be further suppressed.
Third Embodiment
FIG. 12 and FIG. 13 illustrate a third embodiment of a display device according to the present invention. Also, FIG. 12 corresponds to FIG. 7 and is an enlarged plan view of the chip mounting portion M of the frame region F of an organic EL display panel 50c constituting the organic EL display device according to the present embodiment. FIG. 13 corresponds to FIG. 12 and is a plan view of an organic EL display panel 50d, which is a modified example of the organic EL display panel 50c.
In the first embodiment described above, the organic EL display device 70a includes the organic EL display panel 50a with a double layer structure in a plan view including the first output terminals 20c and the second output terminals 20d. However, in the present embodiment described below, the organic EL display device includes the organic EL display panel 50c with a triple layer structure in a plan view including the first output terminals 20c, the second output terminals 20d, and third output terminals 20i. In the present embodiment described below, an organic EL display device includes the organic EL display panel 50c with a triple layer structure in a plan view including the first output terminals 20c, the second output terminals 20d, and the third output terminals 20i. However, the organic EL display device may include an organic EL display panel with a quadruple or more layer structure in a plan view including output terminals.
As with the organic EL display device 70a of the first embodiment, the organic EL display device of the present embodiment includes the organic EL display panel 50c, the integrated circuit chip 60 mounted on the chip mounting portion M of the organic EL display panel 50c, and the flexible printed circuit 55 mounted on the terminal portion T of the organic EL display panel 50c.
As with the organic EL display panel 50a of the first embodiment described above, the organic EL display panel 50c includes the display region D provided in a rectangular shape in which an image is displayed and the frame region F provided in a frame-like shape in a periphery of the display region D.
As with the organic EL display panel 50a of the first embodiment described above, the organic EL display panel 50c includes the flexible substrate layer 10, the TFT layer 30 provided on the flexible substrate layer 10, the organic EL element layer 40 provided on the TFT layer 30, and the sealing film 45 provided covering the organic EL element layer 40.
The organic EL display panel 50c includes, in the chip mounting portion M of the frame region F, the under-chip circuit portion C, the plurality of output-side terminal wiring lines 18tc, the plurality of output-side terminal wiring lines 18td, and the plurality of output-side terminal wiring lines 18ti provided extending parallel to one another on the display region D side of the under-chip circuit portion C (see FIG. 12), and the plurality of input-side terminal wiring lines 18te provided extending parallel to one another on the terminal portion T side of the under-chip circuit portion C (see FIG. 6). As illustrated in FIG. 12, each output-side terminal wiring line 18ti is provided adjacent to one of the output-side terminal wiring lines 18tc and one of the output-side terminal wiring lines 18td. Note that as with the output-side terminal wiring lines 18tc, the output-side terminal wiring lines 18td, and the like, the output-side terminal wiring lines 18ti are provided as the third wiring line layer.
The organic EL display panel 50c includes, in the chip mounting portion M of the frame region F, the plurality of first output terminals 20c provided on the display region D side arranged in a row along the long side on the display region D side of the under-chip circuit portion C as chip terminals on the display region D side of the under-chip circuit portion C, the plurality of second output terminals 20d provided on the terminal portion T side arranged in a row along the long side on the display region D side of the under-chip circuit portion C as chip terminals on the display region D side of the under-chip circuit portion C, the plurality of third output terminals 20i (see FIG. 12) provided between the plurality of first output terminals 20c and the plurality of second output terminals 20d and arranged in a row along the long side on the display region D side of the under-chip circuit portion C as chip terminals on the display region D side of the under-chip circuit portion C, and the plurality of input terminals 20e provided arranged in a row along the long side on the terminal portion T side of the under-chip circuit portion C as chip terminals on the terminal portion T side of the under-chip circuit portion C. As illustrated in FIG. 12, the plurality of first output terminals 20c, the plurality of third output terminals 20i, and the plurality of second output terminals 20d are repeatedly arranged in the order of first output terminal 20c, third output terminal 20i, and second output terminal 20d. As with the first output terminals 20c, the second output terminals 20d, and the like, the third output terminals 20i is provided as the fourth wiring line layer. Also, the plurality of third output terminals 20i are layered on the plurality of output-side terminal wiring lines 18ti and are electrically connected to the plurality of output-side terminal wiring lines 18ti. Further, as with the plurality of first output terminals 20c and the plurality of second output terminals 20d, the plurality of third output terminals 20i are provided so as to correspond to the plurality of bumps 61 on the back surface of the integrated circuit chip 60 and is electrically connected to the plurality of bumps 61 via the anisotropic conductive film 65.
As illustrated in FIG. 12, the organic EL display panel 50c includes, in the chip mounting portion M of the frame region F, for each chip terminal including the plurality of first output terminals 20c, the plurality of second output terminals 20d, and the plurality of input terminals 20e, a chip support body Sa is provided in an island shape at each terminal wiring line overlapping the output-side terminal wiring line 18tc, the output-side terminal wiring line 18td, and the input-side terminal wiring line 18te corresponding to the chip terminal or an extension line E of the terminal wiring line. As illustrated in FIG. 12, the chip support body Sa may be provided for each chip terminal of the plurality of third output terminals 20i. As illustrated in FIG. 12, for each first output terminal 20c, the chip support body Sa is provided on the display region D side (upper side in the diagram) of the first output terminal 20c, and for each second output terminal 20d, the chip support body Sa is provided on the terminal portion T side (lower side in the diagram) of the second output terminal 20d. Also, a pair of the chip support bodies Sa are provided for each input terminal 20e with the pair of chip support bodies Sa sandwiching the input terminal 20e (see FIG. 6).
Note that in the present embodiment described above in which the gap between the third output terminals 20i and the first output terminals 20c and the second output terminals 20d is relatively narrow, the organic EL display panel 50c does not include a chip support body for the plurality of third output terminals 20i. However, the organic EL display panel 50d illustrated in FIG. 13 may be used. Specifically, as illustrated in FIG. 13, in the organic EL display panel 50d, the gap between the third output terminals 20i and the first output terminals 20c and the second output terminals 20d is designed to be relatively wide (for example, approximately 45 μm), and a plurality of chip support bodies Sc are provided as island shapes between the third output terminals 20i and the first output terminals 20c and the second output terminals 20d. As illustrated in FIG. 13, the chip support bodies Sc arranged on the upper side and the lower side in the diagram of the third output terminals 20i are provided for the third output terminals 20i and are provided on each terminal wiring line overlapping the output-side terminal wiring lines 18ti corresponding to the third output terminals 20i. As illustrated in FIG. 13, the chip support bodies Sc arranged on the lower side in the diagram of the first output terminals 20c are provided for the first output terminals 20c and are provided on each terminal wiring line overlapping the output-side terminal wiring lines 18tc corresponding to the first output terminals 20c. As illustrated in FIG. 13, the chip support bodies Sc arranged on the upper side in the diagram of the second output terminals 20d are provided for the second output terminals 20d and are provided on each terminal wiring line overlapping the output-side terminal wiring lines 18td corresponding to the second output terminals 20d.
As with the chip support body Sa in the first embodiment, the chip support body Sc includes the lower resin layer 19b formed of the same material as the first flattening film 19a in the same layer and the upper resin layer 21b provided on the lower resin layer 19b and formed of the same material as the second flattening film 21a in the same layer.
As with the organic EL display device 70a of the first embodiment, the organic EL display device according to the present embodiment including the organic EL display panel 50c described above has flexibility and is configured to display an image by causing the light-emitting layer 3 of the organic EL layer 33 to emit light as appropriate via the first TFT 9a, the second TFT 9b, and the third TFT 9c in each of the subpixels P.
As with the first embodiment, in the present embodiment described above, the organic EL display panel 50c includes the chip support bodies Sa separated from the first output terminals 20c, the second output terminals 20d, and the input terminals 20e. However, as with the second embodiment, the chip support bodies Sa (Sb) may be integrally formed with the first output terminals 20c (20f), the second output terminals 20d (20g), and the input terminals 20e (20h).
The organic EL display device including the organic EL display panel 50c of the present embodiment can be manufactured by changing the pattern shape of second wiring line layer, the fourth wiring line layer, the lower resin layer 19b, and the upper resin layer 21b in the manufacturing method for the organic EL display device 70a of the first embodiment.
As described above, according to an organic EL display device including the organic EL display panel 50c of the present embodiment, in the chip mounting portion M of the frame region F, for each chip terminal including the plurality of first output terminals 20c, the plurality of second output terminals 20d, and the plurality of input terminals 20e, the chip support body Sa is provided in an island shape at each terminal wiring line overlapping the output-side terminal wiring line 18tc, the output-side terminal wiring line 18td, and the input-side terminal wiring line 18te corresponding to the chip terminal or the extension line E of the terminal wiring line. This makes it difficult for the conductive particles 64 to clump together between chip support bodies Sa and the adjacently-disposed bumps 61. Thus, short-circuiting between the adjacent terminals due to the conductive particles 64 forming a connection can be suppressed, and short-circuiting between the terminals in the chip mounting portion M can be suppressed.
Also, according to the organic EL display device including the organic EL display panel 50c of the present embodiment, in the chip mounting portion M of the frame region F, the chip support bodies Sa are provided at or near the chip terminals including the plurality of first output terminals 20c, the plurality of second output terminals 20d, and the plurality of input terminals 20e. Thus, deflection of the organic EL display panel 50c at or near the bumps 61 of the integrated circuit chip 60 in the mounting step can be suppressed. In this manner, cracking in the base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 of the organic EL display panel 50c can be suppressed, and disconnection of the output-side terminal wiring lines 18tc, the output-side terminal wiring lines 18td, the output-side terminal wiring lines 18ti, and the input-side terminal wiring lines 18te provided on the second interlayer insulating film 17 can be suppressed.
Other Embodiments
In each of the embodiments described above, the organic EL layer having a five-layer structure including the hole injection layer, the hole transport layer, the light-emitting layer, the electron transport layer, and the electron injection layer is exemplified, but the organic EL layer may have a three-layer structure including a hole injection-cum-transport layer, a light-emitting layer, and an electron transport-cum-injection layer, for example.
In each of the embodiments described above, the organic EL display device including the first electrode as an anode and the second electrode as a cathode is exemplified. The present invention is also applicable to an organic EL display device in which the layered structure of the organic EL layer is reversed with the first electrode being a cathode and the second electrode being an anode.
In each of the embodiments described above, the organic EL display device in which the electrode of the TFT connected to the first electrode serves as the drain electrode is exemplified. However, the present invention is also applicable to an organic EL display device in which the electrode of the TFT connected to the first electrode is referred to as the source electrode.
In each of the embodiments described above, the organic EL display device is exemplified as a display device. The present invention can also be applied to a display device including a plurality of light-emitting elements driven by a current, for example, to a display device including quantum dot light-emitting diodes (QLEDs), which are a light-emitting element using a quantum dot-containing layer.
INDUSTRIAL APPLICABILITY
As described above, the present invention is useful for a flexible display device.
REFERENCE SIGNS LIST
- D Display region
- E Extension line
- F Frame region
- M Chip mounting portion
- P Subpixel
- Sa, Sb, Sc Chip support body
- T Terminal portion
10 Flexible substrate layer
18
tc, 18td, 18ti Output-side terminal wiring line
18
te Input-side terminal wiring line
19
a First flattening film
19
b Lower resin layer
20
a Power source line (wiring line layer)
20
b Relay electrode (wiring line layer)
20
c, 20f First output terminal (chip terminal)
20
d, 20g Second output terminal (chip terminal)
20
e, 20h Input terminal (chip terminal)
20
fe Metal layer
20
i Third output terminal (chip terminal)
21
a Second flattening film
21
b Upper resin layer
30 TFT layer (thin film transistor layer)
35 Organic EL element (organic electroluminescence element, light-emitting element)
40 Organic EL element layer (light-emitting element layer)
41 First inorganic sealing film
42 Organic sealing film
43 Second inorganic sealing film
45 Sealing film
50
a, 50b Organic EL display panel
55 Flexible printed circuit
60 Integrated circuit chip
61 Bump
64 Conductive particles
65 Anisotropic conductive film
70
a, 70b Organic EL display device
Patent Application
20240357882
