Patent Application
20240315094
This application claims priority to and the benefits of Korean Patent Application No. 10-2022-0033556 under 35 U.S.C. § 119, filed on Mar. 17, 2022, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference.
Embodiments relate to a display device.
A display device is a device for displaying an image, and includes a liquid crystal display (LCD), an organic light emitting diode (OLED) display, and the like. The display device is used in various electronic devices such as a mobile phone, a navigation device, a digital camera, an electronic book, a portable game machine, and various terminals.
Since the OLED display has a self-luminance characteristic and does not require an additional light source unlike the LCD, thickness and weight of the OLED display may be reduced. The OLED display has high-quality characteristics such as low power consumption, high luminance, and high response speed.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore it may contain information that does not constitute prior art.
Embodiments provide a display device capable of preventing and minimizing breakage of a semiconductor layer and penetration of hydrogen.
However, embodiments of the disclosure are not limited to those set forth herein. The above and other embodiments will become more apparent to one of ordinary skill in the art to which the disclosure pertains by referencing the detailed description of the disclosure given below.
In an embodiment, a display device may include: a substrate; a first conductive layer disposed on the substrate and including a data line, an initialization voltage line, and a driving voltage line; and a semiconductor layer disposed on the first conductive layer, wherein the semiconductor layer may include a first semiconductor, a second semiconductor, and a third semiconductor spaced apart from each other, the first semiconductor may be electrically connected to the driving voltage line, the second semiconductor may be electrically connected to the data line, the third semiconductor may be electrically connected to the initialization voltage line, and the second semiconductor may not overlap the data line in a direction perpendicular to a surface of the substrate.
The display device may further include: a second conductive layer disposed on the semiconductor layer; and a third conductive layer disposed on the second conductive layer and including a connecting member, wherein the connecting member may overlap both the second semiconductor and the data line, and the second semiconductor and the data line may be electrically connected through the connecting member.
The data line may extend along a second direction, and the connecting member may extend along a first direction intersecting the second direction.
The driving voltage line may extend along a second direction, and the third conductive layer may further include an upper storage electrode disposed between the data line and the driving voltage line in a plan view, and the upper storage electrode may include a protrusion protruding in a first direction crossing the second direction.
The protrusion of the upper storage electrode may extend to cross the driving voltage line.
The protrusion of the upper storage electrode may be electrically connected to the third semiconductor.
The third semiconductor may not overlap the driving voltage line.
The third semiconductor may overlap the initialization voltage line and may be electrically connected to the initialization voltage line.
An edge of the third semiconductor may overlap the initialization voltage line and the third conductive layer.
The third conductive layer may further include an initialization voltage connecting portion overlapping the initialization voltage line, and an edge of the third semiconductor may overlap the initialization voltage line and the initialization voltage connecting portion.
An edge of the first semiconductor may overlap the driving voltage line overlap and the third conductive layer.
The third conductive layer may include a driving voltage connecting portion overlapping the driving voltage line, and an edge of the first semiconductor may overlap the driving voltage line and the driving voltage connecting portion.
The first conductive layer may further include a lower storage electrode overlapping the upper storage electrode, and a side of the lower storage electrode may be disposed inside a boundary of the upper storage electrode in a plan view.
An edge of the first semiconductor may overlap the lower storage electrode and the upper storage electrode.
In an embodiment, a display device may include: a substrate; a first conductive layer disposed on the substrate and including a data line, an initialization voltage line, and a driving voltage line; a semiconductor layer disposed on the first conductive layer; and a third conductive layer disposed on the semiconductor layer and including a cover member, wherein the semiconductor layer may include a first semiconductor, a second semiconductor, and a third semiconductor spaced apart from each other, the first semiconductor may be electrically connected to the driving voltage line, the second semiconductor may be electrically connected to the data line, the third semiconductor may be electrically connected to the initialization voltage line, and an edge of the first semiconductor may overlap the driving voltage line and the cover member.
The cover member may not be electrically connected to the first conductive layer.
An edge of the third semiconductor may overlap the initialization voltage line and the cover member.
The third semiconductor may not overlap the driving voltage line.
The first conductive layer may further include an upper storage electrode disposed between the data line and the driving voltage line in a plan view, the upper storage electrode may include a protrusion, and the protrusion of the upper storage electrode may overlap the third semiconductor.
The second semiconductor may not overlap the first conductive layer.
According to the embodiments, a display device that may minimize breakage of a semiconductor layer and penetration of hydrogen may be provided.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the invention. As used herein “embodiments” and “implementations” are interchangeable words that are non-limiting examples of devices or methods disclosed herein. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Various embodiments do not have to be exclusive nor limit the disclosure. For example, specific shapes, configurations, and characteristics of an embodiment may be used or implemented in an embodiment.
Unless otherwise specified, the illustrated embodiments are to be understood as providing features of the invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and/or aspects, etc. (hereinafter individually or collectively referred to as “elements”), of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.
The use of cross-hatching and/or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for materials, material properties, dimensions, proportions, commonalities between illustrated elements, and/or any other characteristic, attribute, property, etc., of the elements, unless specified. Further, in the accompanying drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. When an embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. Also, like reference numerals denote like elements.
When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. Further, the DR1-axis, the DR2-axis, and the DR3-axis are not limited to three axes of a rectangular coordinate system, such as the X, Y, and Z-axes, and may be interpreted in a broader sense. For example, the DR1-axis, the DR2-axis, and the DR3-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. Further, the X-axis, the Y-axis, and the Z-axis are not limited to three axes of a rectangular coordinate system, such as the x, y, and z axes, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. For the purposes of this disclosure, “at least one of A and B” may be construed as understood to mean A only, B only, or any combination of A and B. Also, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Although the terms “first,” “second,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure.
Spatially relative terms, such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” “side” (e.g., as in “sidewall”), and the like, may be used herein for descriptive purposes, and, thereby, to describe one elements relationship to another element(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. Furthermore, the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing embodiments and is not intended to be limiting. As used herein, the singular forms, “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Moreover, the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is also noted that, as used herein, the terms “substantially,” “about,” and other similar terms, are used as terms of approximation and not as terms of degree, and, as such, are utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.
Various embodiments are described herein with reference to sectional and/or exploded illustrations that are schematic illustrations of embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments disclosed herein should not necessarily be construed as limited to the illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. In this manner, regions illustrated in the drawings may be schematic in nature and the shapes of these regions may not reflect actual shapes of regions of a device and, as such, are not necessarily intended to be limiting.
Further, throughout the specification, the phrase “in a plan view” or “on a plane” means viewing a target portion from the top, and the phrase “in a cross-sectional view” or “on a cross-section” means viewing a cross-section formed by vertically cutting a target portion from the side.
The pixels may include a first pixel PXa, a second pixel PXb, and a third pixel PXc. Each of the first pixel PXa, the second pixel PXb, and the third pixel PXc may include transistors T1, T2, and T3, a storage capacitor Cst, and light emitting diodes EDa, EDb, and EDc that are light emitting elements. Each of the pixels PXa. PXb, and PXc may be divided into the light emitting diode EDa, EDb, or EDc and a pixel circuit part. The pixel circuit part may include the transistors T1, T2, and T3 and the storage capacitor Cst in
The transistors T1, T2, and T3 may include one driving transistor T1 (also referred to as a first transistor) and two switching transistors T2 and T3. The two switching transistors T2 and T3 may be classified into an input transistor T2 (also referred to as a second transistor) and an initialization transistor T3 (also referred to as a third transistor). Each of the transistors T1, T2, and T3 may include a gate electrode, a first electrode, and a second electrode, and may include a semiconductor layer ACT including a channel, so that a current may flow in or may not flow in the channel of the semiconductor layer ACT according to a voltage of the gate electrode. According to voltages applied to respective transistors T1, T2, and T3, one of the first electrode and the second electrode may be a source electrode and another thereof may be a drain electrode.
The gate electrode of the driving transistor T1 may be connected to an end portion of the storage capacitor Cst, and may be also connected to the second electrode (output side electrode) of the input transistor T2. The first electrode of the driving transistor T1 may be connected to a driving voltage line 172v that transmits a driving voltage ELVDD, and the second electrode of the driving transistor T1 may be connected to an anode of the light emitting diode EDa, EDb, or EDc, another end portion of the storage capacitor Cst, and the first electrode of the initialization transistor T3. The gate electrode of the driving transistor T1 may receive a data voltage DVa, DVb, or DVc according to a switching operation of the input transistor T2, and a driving current may be supplied to the light emitting diode EDa, EDb, or EDc according to the voltage of the gate electrode thereof. For example, the storage capacitor Cst may store and maintain the voltage of the gate electrode of the driving transistor T1.
The gate electrode of the input transistor T2 may be connected to a first scan signal line 151 that transmits a first scan signal SC. The first electrode of the input transistor T2 may be connected to a data line 171a, 171b, or 171c that transmits the data voltage DVa, DVb, or DVc, and the second electrode of the input transistor T2 may be connected to an end portion of the storage capacitor Cst and the gate electrode of the driving transistor T1. Data lines 171a, 171b, and 171c may transmit different data voltages DVa, DVb, and DVc, respectively. The input transistors T2 of the pixels PXa, PXb, and PXc may be respectively connected to different data lines 171a, 171b, and 171c. The gate electrodes of the input transistors T2 of the pixels PXa, PXb, and PXc may be connected to the same first scan signal line 151 to receive the first scan signal SC at the same timing. In case that the input transistors T2 of the pixels PXa, PXb, and PXc are simultaneously turned on by the first scan signal SC at the same timing, the different data voltages DVa, DVb, and DVc may be applied to the gate electrodes of the driving transistors T1 of the pixel PXa, PXb, and PXc and an end portion of the storage capacitor Cst through the different data lines 171a, 171b, and 171c.
The embodiment of
The gate electrode of the initialization transistor T3 may be connected to a second scan signal line 151-1 that transmits a second scan signal SS. The first electrode of the initialization transistor T3 may be connected to another end portion of the storage capacitor Cst, the second electrode of the driving transistor T1, and the anode of the light emitting diode EDa, EDb, or EDc, and the second electrode of the initialization transistor T3 may be connected to an initialization voltage line 173 that transmits an initialization voltage VINT. The initialization transistor T3 may be turned on according to the second scan signal SS to transmit the initialization voltage VINT to the anode of the light emitting diode EDa, EDb, or EDc and another end portion of the storage capacitor Cst to initialize the voltage of the anode of the light emitting diode EDa, EDb, or EDc.
The initialization voltage line 173 may perform an operation to sense a voltage of the anode of the light emitting diode EDa, EDb, or EDc before applying the initialization voltage VINT, so that it may function as a sensing wire SL. Through the sensing operation, whether the anode voltage is maintained at a target voltage may be checked. The sensing operation and the initialization operation of transmitting the initialization voltage VINT may be performed separately in different times, and for example, the initialization operation may be performed after the sensing operation is performed.
In the embodiment of
An end portion of the storage capacitor Cst may be connected to the gate electrode of the driving transistor T1 and the second electrode of the input transistor T2, and another end portion of the storage capacitor Cst may be connected to the first electrode of the initialization transistor T3, the second electrode of the driving transistor T1, and the anode of the light emitting diode EDa, EDb, or EDc. In
A cathode of the light emitting diode EDa, EDb, or EDc may receive a driving low voltage ELVSS through a driving low voltage line 174v, and the light emitting diode EDa, EDb, or EDc may emit light according to an output current of the driving transistor T1 to display a gray.
In an embodiment, light emitting capacitors may be formed at respective end portions of the light emitting diodes EDa, EDb, and EDc, so that voltages at respective end portions of the light emitting diodes EDa, EDb, and EDc may be maintained constant so that the light emitting diodes EDa, EDb, and EDc may display a constant luminance.
Hereinafter, an operation of a pixel having the circuit as shown in
One frame may start in case that a light emitting period ends. After that, a high level second scan signal SS is supplied to turn on the initialization transistor T3. In case that the initialization transistor T3 is turned on, an initialization operation and/or a sensing operation may be performed.
The initialization operation and the sensing operation are performed will be described.
The sensing operation may be performed before the initialization operation is performed. For example, as the initialization transistor T3 is turned on, the initialization voltage line 173 may function as the sensing wire SL to sense a voltage of the anode of the light emitting diode EDa, EDb, or EDc. Through the sensing operation, whether the anode voltage is maintained at a target voltage may be checked.
For example, the initialization operation may be performed, and the voltages of another end portion of the storage capacitor Cst, the second electrode of the driving transistor T1, and the anode of the light emitting diode EDa, EDb, or EDc may be changed to the initialization voltage VINT transmitted from the initialization voltage line 173, thereby performing the initialization.
As described above, the sensing operation and the initialization operation for transmitting the initialization voltage VINT may be time-divided and performed, so that the pixel may perform various operations with using a minimum number of transistors and reducing an area occupied by the pixel. As a result, a resolution of the display panel may be improved.
The first scan signal SC may be also applied with being changed to a high level together with the initialization operation or at separate timing, so that the input transistor T2 may be turned on, and a writing operation may be performed. For example, the data voltage DVa, DVb, or DVc from the data lines 171a, 171b, or 171c through the turned-on input transistor T2 may be inputted and stored to the gate electrode of the driving transistor T1 and an end portion of the storage capacitor Cst.
The data voltage DVa, DVb, or DVc and the initialization voltage VINT may be applied to respective end portions of the storage capacitor Cst by the initialization operation and the writing operation, respectively. In the state in which the initialization transistor T3 is turned on, in case that an output current is generated from the driving transistor T1, the output current may be outputted to the outside through the initialization transistor T3 and the initialization voltage line 173, so that the output current may not be inputted to the light emitting diode EDa, EDb, or EDc. In some embodiments, during the writing period in which the high level first scan signal SC is supplied, the driving voltage ELVDD may be applied as a low level voltage, or the driving low voltage ELVSS may be applied as a high level voltage, so that a current from flowing through the light emitting diode EDa, EDb, or EDc may be prevented.
After that, in case that the first scan signal SC is changed to a low level, the driving transistor T1 may generate and output an output current by the high level driving voltage ELVDD applied to the driving transistor T1 and the gate voltage of the driving transistor T1 stored in the storage capacitor Cst. The output current of the driving transistor T1 may be inputted to the light emitting diode EDa, EDb, or EDc, so that a light emitting period in which the light emitting diode EDa, EDb, or EDc emits light may proceed.
A detailed structure of the pixel circuit part among the pixels PXa, PXb, and PXc having the circuit structure as shown in
As illustrated in
First, a stacked structure of the display device 1 will be schematically described with reference to
The display device 1 according to an embodiment may include a first substrate 110. The first substrate 110 may include an insulating material such as glass, plastic, or the like, and may have flexibility.
A first conductive layer CL1, a first insulating layer 120, a semiconductor layer ACT, a second insulating layer 140, a second conductive layer CL2, a third insulating layer 160, a third conductive layer CL3, and a fourth insulating layer 180 may be sequentially formed (or stacked) on the first substrate 110. The first insulating layer 120, the second insulating layer 140, and the third insulating layer 160 may be inorganic insulating layers including an inorganic insulating material, and the fourth insulating layer 180 may be an organic insulating layer including an organic insulating material. In some embodiments, each insulating layer may be formed as layers, and in some embodiments, the third insulating layer 160 may be an organic insulating layer. The inorganic insulating material may include a silicon nitride (SiNx), a silicon oxide (SiOx), and a silicon oxynitride (SiOxNy), and the organic insulating material may include polyimide, an acryl-based polymer, a siloxane-based polymer, and the like. The first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3 may include at least one of copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel, (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys thereof. Each of the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3 may be formed as a single layer or a multilayer. For example, each of the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3 may have a multilayer structure including a lower layer including titanium and an upper layer including copper. For example, the semiconductor layer ACT may include a semiconductor material such as amorphous silicon, polysilicon, or an oxide semiconductor. In an embodiment, a semiconductor layer ACT including an oxide semiconductor will be described. The second insulating layer 140 and the second conductive layer CL2 may be formed by the same process, and may have the same planar shape as each other. For example, the second insulating layer 140 may be positioned to overlap the second conductive layer CL2.
Hereinafter, each constituent element included in the pixel circuit part among a group of pixels will be described in detail with reference to
The first scan signal line 151 may extend in an x-axis direction, may be formed one for each pixel circuit part of a group, and may be formed in the third conductive layer CL3 as a single layer. For example, a second scan signal line 151-1 may extend in the x-axis direction, may be formed one for each pixel circuit part of a group, and may be formed in the third conductive layer CL3 as a single layer. For example, in the embodiments, the first scan signal line 151 and the second scan signal line 151-1 may be formed of layers such as a double-layered structure.
The first scan signal line 151 may be connected (e.g., electrically connected) to a gate electrode 156 positioned (or included) in the second conductive layer CL2 through an opening. The first scan signal SC may be transmitted (or applied) along the first scan signal line 151, and simultaneously may control the input transistors T2 included in a group of pixel circuits through the gate electrode 156 connected (e.g., electrically connected) to the first scan signal line 151.
For example, the second scan signal line 151-1 may be connected (e.g., electrically connected) to a gate electrode 157 positioned (or included) in the second conductive layer CL2 through an opening. The second scan signal SS may be transmitted along the second scan signal line 151-1, and simultaneously may control the input transistors T3 included in a group of pixel circuits through the gate electrode 157 connected (e.g., electrically connected) to the second scan signal line 151-1.
The data lines 171a, 171b, and 171c may extend in the y-axis direction, and three data lines 171a, 171b, and 171c may be all positioned at a side (e.g., a right side in
The data lines 171a, 171b, and 171c may be connected (e.g., electrically connected) to second semiconductors 132a, 132b, and 132c through connecting members 177a, 177b, and 177c positioned (or included) in the third conductive layer CL3, respectively. Through the above-described structure, in case that three pixels PXa, PXb, and PXc included in a group of pixels are controlled by one first scan signal line 151, different data voltages DVa, DVb, and DVc may be applied thereto through different data lines 171a, 171b, and 171c. Accordingly, the light emitting diodes EDa, EDb, and EDc respectively included in the pixels PXa, PXb, and PXc may display different luminance.
The connecting members 177a, 177b, and 177c may be positioned (or extend) along the x-axis direction so that the second semiconductors 132a, 132b, and 132c and the data lines 171a, 171b, and 171c may be connected and may not overlap each other. Accordingly, a problem that the semiconductor layer ACT is broken or the inorganic insulating layer (e.g., 120, 140, or 160) on the semiconductor layer ACT is broken due to a step (or step difference) of the first conductive layer CL1 may be solved or prevented in case that the semiconductor layer ACT passes over the first conductive layer CL1. Specific configurations and effects will be separately described below.
The driving voltage line 172v transmitting the driving voltage ELVDD may include a driving voltage line 172v extending in the y-axis direction and an additional driving voltage line 172h extending in the x-axis direction. The additional driving voltage line 172h may be positioned (or included) in the third conductive layer CL3 like an additional driving low voltage line 174h to be described below. For example, according to this embodiment, the driving voltage line 172v positioned (or included) in the first conductive layer CL1 may be connected (e.g., electrically connected) to the additional driving voltage line 172h positioned (or included) in the third conductive layer CL3 through an opening formed in (or passing through) the first insulating layer 120 and the third insulating layer 160. Thus, a voltage of the driving voltage ELVDD may be prevented from dropping at a specific position by transmitting the driving voltage ELVDD in the x-axis direction and the y-axis direction.
According to the embodiment of
Although separately described below, protrusions 1751a, 1751b, and 1751c of the upper storage electrodes 175a, 175b, and 175c may be positioned between the driving voltage connecting portions 172-3v spaced apart from each other. The protrusions 1751a, 1751b, 1751c may allow third semiconductors 133a, 133b, and 133c to not overlap the driving voltage line 172v and to be connected (e.g., electrically connected) to the upper storage electrodes 175a, 175b, and 175c.
The initialization voltage line 173 that transmits the initialization voltage VINT may be positioned at the left side of the pixel circuit part, may be positioned (or included) in the first conductive layer CL1, and may extend in the y-axis direction. The initialization voltage line 173 may include a section having a double-layered structure. For example, an initialization voltage connecting portion 173-3v positioned (or included) in the third conductive layer CL3 may be further formed on the initialization voltage line 173 positioned (or included) in the first conductive layer CL1. The initialization voltage connecting portion 173-3v may be connected (e.g., electrically connected) to the initialization voltage line 173 through the opening formed in (or passing through) the first insulating layer 120 and the third insulating layer 160. Since the initialization voltage VINT is transmitted to the double layer of the initialization voltage line 173 and the initialization voltage connecting portion 173-3v in a partial section, the wire resistance may be reduced. The initialization voltage connecting portion 173-3v may be connected (e.g., electrically connected) to the third semiconductors 133a. 133b, and 133c through the opening formed in (or passing through) the third insulating layer 160 so that the initialization voltage VINT may be transmitted to the third semiconductors 133a, 133b, and 133c.
Referring to the embodiment of
The driving low voltage line 174v that transmits the driving low voltage ELVSS may include a driving low voltage line 174v extending in the y-axis direction and an additional driving low voltage line 174h extending in the x-axis direction. The driving low voltage line 174v positioned (or included) in the first conductive layer CL1 may be connected (e.g., electrically connected) to the additional driving low voltage line 174h positioned (or included) in the third conductive layer CL3 through the opening formed in (or passing through) the first insulating layer 120 and the third insulating layer 160. Thus, a voltage of the driving low voltage ELVSS may be prevented from dropping at a specific position by transmitting the driving low voltage ELVSS in the x-axis direction and the y-axis direction.
The driving low voltage line 174v may include a section having a triple-layered structure. For example, on the driving low voltage line 174v positioned (or included) in the first conductive layer CL1, a portion 174-2v positioned (or included) in the second conductive layer CL2 and a portion 174-3v positioned (or included) in the third conductive layer CL3 may be connected (e.g., electrically connected) through an opening. For example, the driving low voltage line 174v may be connected (e.g., electrically connected) to the portion 174-3v positioned (or included) in the third conductive layer CL3 through the opening formed in (or passing through) the first insulating layer 120 and the third insulating layer 160. For example, the portion 174-3v positioned (or included) in the third conductive layer CL3 may be connected (e.g., electrically connected) to the portion 174-2v positioned (or included) in the second conductive layer CL2 through the opening formed in (or passing through) the third insulating layer 160. In an embodiment, the driving low voltage line 174v positioned (or included) in the first conductive layer CL1 and the portion 174-2v positioned (or included) in the second conductive layer CL2 may not be directly connected, but may be connected through the portion 174-3v positioned (or included) in the third conductive layer CL3. According to such a triple layered structure, since the driving low voltage ELVSS is transmitted to the triple layer, wire resistance may be reduced.
The additional driving low voltage line 174h positioned (or included) in the third conductive layer CL3 may be connected (e.g., electrically connected) to the cathode of the light emitting diode EDa, EDb, or EDc by an opening 186 positioned in the fourth insulating layer 180, so that the driving low voltage ELVSS may be transmitted to the cathode. In some embodiments, the additional driving low voltage line 174h may be positioned on the fourth insulating layer 180, and may further include the cathode connecting portion for connecting the cathode of the light emitting diode EDa, EDb, or EDc.
For example, referring to
The transistors T1, T2, and T3 may have the same stacked structure, and may include the gate electrode positioned (or included) in the second conductive layer CL2, the channel positioned (or included) in the semiconductor layer ACT, and a first area and a second area positioned at respective sides of the channel and doped to have the same or similar characteristics as or to the conductor. The first area and the second area positioned in the semiconductor layer ACT may correspond to the first electrode and the second electrode described in
Each transistor will be described below.
The driving transistor T1 may have a channel, a first area, and a second area in the first semiconductor 131a, 131b, or 131c positioned on the first insulating layer 120, and the first area and the second area may be doped to have the same or similar conductive characteristics as a conductor. The first area of the first semiconductor 131a, 131b, or 131c may be connected (e.g., electrically connected) to the driving voltage line 172v through the opening and the driving voltage connecting portion 172-3v to receive the driving voltage ELVDD. For example, the driving voltage line 172v may be connected to the driving voltage connecting portion 172-3v through the opening formed in (or passing through) the first insulating layer 120 and the third insulating layer 160. For example, the driving voltage connecting portion 172-3v may be connected (e.g., electrically connected) to the first semiconductor 131a, 131b, or 131c through the opening formed in (or passing through) the third insulating layer 160. For example, the second area of the first semiconductor 131a, 131b, or 131c may be connected (e.g., electrically connected) to the upper storage electrode 175a, 175b, or 175c through the opening formed in (or passing through) the third insulating layer 160. For example, the upper storage electrodes 175a, 175b, and 175c may be connected (e.g., electrically connected) to the lower storage electrodes 125a, 125b, and 125c through the openings formed in the first insulating layer 120 and the third insulating layer 160, and the upper storage electrodes 175a, 175b, and 175c may be connected (e.g., electrically connected) to the third semiconductors 133a, 133b, and 133c through the opening formed in (or passing through) the third insulating layer 160. As a result, the first semiconductors 131a, 131b, and 131c may be also connected (e.g., electrically connected) to the lower storage electrodes 125a, 125b, and 125c and the first area of the third semiconductors 133a, 133b, and 133c.
The gate electrodes 155a, 155b, and 155c may be formed on the first semiconductors 131a, 131b, and 131c. For example, the second insulating layer 140 may be positioned between the first semiconductors 131a, 131b, and 131c and the gate electrodes 155a, 155b, and 155c. In a plan view, a channel may be formed in the first semiconductor 131a, 131b, or 131c overlapping the gate electrode 155a, 155b, or 155c, and the channel may not be doped because it is covered by the gate electrode 155a, 155b, or 155c. The gate electrode 155a, 155b, or 155c may have a protrusion, and the protrusion may be connected (e.g., electrically connected) to the second semiconductor 132a, 132b, or 132c through the opening and the connecting member 176a, 176b, or 176c. For example, the gate electrode 155a, 155b, or 155c positioned (or included) in the second conductive layer CL2 may be connected (e.g., electrically connected) to the connecting member 176a, 176b, or 176c positioned (or included) in the third conductive layer CL3 through the opening formed in (or passing through) the third insulating layer 160, and the connecting member 176a, 176b, or 176c may be connected (e.g., electrically connected) to the second semiconductor 132a, 132b, or 132c through the opening formed in (or passing through) the third insulating layer 160. The connecting member 176a, 176b, or 176c and the upper storage electrode 175a. 175b, or 175c may be positioned on the same layer, and may be formed of the same material.
According to the embodiment of
For example, regarding the portions in which the three gate electrodes 155a, 155b, and 155c are connected (e.g., electrically connected) to the second semiconductors 132a, 132b, and 132c, the gate electrode 155a of the driving transistor T1 of the first pixel PXa may be connected (e.g., electrically connected) to the second semiconductor 132a at an upper side thereof, the gate electrode 155b of the driving transistor T1 of the second pixel PXb may be connected (e.g., electrically connected) to the second semiconductor 132b at an upper side thereof, and the gate electrode 155c of the driving transistor T1 of the third pixel PXc may be connected (e.g., electrically connected) to the second semiconductor 132c at a lower side thereof.
The structure of each of the gate electrodes 155a, 155b, and 155c will be described in detail as follows.
The gate electrode 155a of the driving transistor T1 of the first pixel PXa may include a portion overlapping the first semiconductor 131a and a portion that extends therefrom to form another electrode of the storage capacitor Cst with overlapping the lower storage electrode 125a and the upper storage electrode 175a. The gate electrode 155a of the driving transistor T1 of the first pixel PXa may protrude to further include a protrusion connected (e.g., electrically connected) to the connecting member 176a through the opening formed in (or passing through) the third insulating layer 160. The upper storage electrode 175a may include a removed portion to be able to be connected (e.g., electrically connected) to the lower storage electrode 125a through the opening formed in (or passing through) the first insulating layer 120 and the third insulating layer 160.
For example, a boundary line of the gate electrode 155a of the driving transistor T1 of the first pixel PXa may be positioned more to the inside in a plan view than a boundary line of the lower storage electrode 125a and/or a boundary line of the upper storage electrode 175a that overlap the gate electrode 155a except for the protrusion thereof. For example, the gate electrode 155a may have a structure that is protected by the lower storage electrode 125a and/or the upper storage electrode 175a, so that the lower storage electrode 125a and/or the upper storage electrode 175a may form parasitic capacitance with the pixel PXb adjacent thereto. This is because the gate electrode 155a of the driving transistor T1 of the first pixel PXa is covered by the lower storage electrode 125a and/or the upper storage electrode 175a positioned thereabove and therebelow, and this is because most of generated power lines are connected to the lower storage electrode 125a and/or the upper storage electrode 175a before entering (or connecting) the gate electrode 155a.
The gate electrode 155b of the driving transistor T1 of the second pixel PXb may include a portion overlapping the first semiconductor 131b and a portion that extends therefrom to form another electrode of the storage capacitor Cst with overlapping the lower storage electrode 125b and the upper storage electrode 175b. The gate electrode 155b of the driving transistor T1 of the second pixel PXb may protrude to further include a protrusion connected (e.g., electrically connected) to the connecting member 176b through the opening formed in (or passing through) the third insulating layer 160. The upper storage electrode 175b may include a removed portion to be able to be connected (e.g., electrically connected) to the lower storage electrode 125b through the opening formed in (or passing through) the first insulating layer 120 and the third insulating layer 160.
The boundary line of the gate electrode 155b of the driving transistor T1 of the second pixel PXb may be positioned more to the inside than the boundary line of the lower storage electrode 125b and/or the boundary line of the upper storage electrode 175b that overlap the gate electrode 155b except for the protrusion thereof in a plan view. The gate electrode 155b may have a structure that is protected by the lower storage electrode 125b and/or the upper storage electrode 175b, and the lower storage electrode 125b and/or the upper storage electrode 175b form parasitic capacitance with the pixels PXa and PXc adjacent thereto. This is because the gate electrode 155b of the driving transistor T1 of the second pixel PXb is covered by the lower storage electrode 125b and/or the upper storage electrode 175b positioned thereabove and therebelow, and this is because most of generated power lines are connected to the lower storage electrode 125b and/or the upper storage electrode 175b before entering the gate electrode 155b.
The gate electrode 155c of the driving transistor T1 of the third pixel PXc may include a portion overlapping the first semiconductor 131c and a portion that extends therefrom to form another electrode of the storage capacitor Cst with overlapping the lower storage electrode 125c and the upper storage electrode 175c. The gate electrode 155c of the driving transistor T1 of the third pixel PXc may protrude to further include a protrusion connected (e.g., electrically connected) to the connecting member 176c through the opening formed in (or passing through) the third insulating layer 160. The upper storage electrode 175c may include a removed portion to be able to be connected (e.g., electrically connected) to the lower storage electrode 125c through the opening formed in (or passing through) the first insulating layer 120 and the third insulating layer 160.
The boundary line of the gate electrode 155c of the driving transistor T1 of the third pixel PXc may be positioned more to the inside than the boundary line of the lower storage electrode 125c and/or the boundary line of the upper storage electrode 175c that overlap the gate electrode 155c except for the protrusion thereof in a plan view. For example, the gate electrode 155c may have a structure that is protected by the lower storage electrode 125c and/or the upper storage electrode 175c, and the lower storage electrode 125c and/or the upper storage electrode 175c form parasitic capacitance with the pixel PXb adjacent thereto. This is because the gate electrode 155c of the driving transistor T1 of the third pixel PXc is covered by the lower storage electrode 125c and/or the upper storage electrode 175c positioned thereabove and therebelow, and this is because most of generated power lines are connected to the lower storage electrode 125c and/or the upper storage electrode 175c before entering the gate electrode 155c.
Referring to
The input transistor T2 may have a channel, a first area, and a second area in the second semiconductor 132a, 132b, or 132c positioned on the first insulating layer 120, and the first area and the second area may be doped to have the same or similar conductive characteristics as a conductor. The first area of the second semiconductor 132a, 132b, or 132c may be connected (e.g., electrically connected) to the connecting member 177a, 177b, or 177c through the opening formed in (or passing through) the third insulating layer 160, and the connecting member 177a, 177b, or 177c may be connected (e.g., electrically connected) to the data line 171a, 171b, or 171c through the opening formed in (or passing through) the first insulating layer 120 and the third insulating layer 160 to receive the data voltage DVa, DVb, or DVc. The second area of the second semiconductor 132a, 132b, or 132c may be connected (e.g., electrically connected) to the opening formed in (or passing through) the third insulating layer 160 and the connecting member 176a, 176b, or 176c, and the connecting member 176a, 176b, or 176c may be connected (e.g., electrically connected) to the gate electrode 155a, 155b, or 155c through the openings formed in (or passing through) the third insulating layer 160. In some embodiments, the connecting member 176a, 176b, or 176c may extend toward the channel of the second semiconductor 132a, 132b, or 132c to cover the channel of the second semiconductor 132a, 132b, or 132c.
As shown in
The second semiconductor 132a, 132b, or 132c may be connected to the data line 171a, 171b, or 171c through the connecting member 177a, 177b, or 177c positioned (or extending) along the x-axis direction. The connecting member 177a, 177b, or 177c may be positioned (or extending) along the x-axis direction, and the second semiconductor 132a, 132b, or 132c and the data line 171a, 171b, or 171c may be connected to each other through the opening overlapping the connecting member 177a, 177b, or 177c.
For example, the second semiconductor 132a, 132b, or 132c and the data line 171a, 171b, or 171c may be connected by the connecting member 177a, 177b, or 177c and may not overlap each other. Accordingly, a problem that the semiconductor layer ACT is cut or the inorganic insulating layer (e.g., 120, 140, or 160) on the semiconductor layer ACT is broken due to the step (or step difference) of the first conductive layer CL1 may be solved or prevented in case that the semiconductor layer ACT passes over the first conductive layer CL1. A specific effect will be separately described below.
The gate electrode 156 may be formed on the second semiconductor 132a, 132b, or 132c. For example, the second insulating layer 140 may be positioned between the second semiconductor 132a, 132b, or 132c and the gate electrode 156. In a plan view, a channel may be formed in the second semiconductor 132a, 132b, or 132c overlapping the gate electrode 156, and the channel may be covered by the gate electrode 156 such that the cannel may not be doped. The gate electrode 156 may extend to be connected (e.g., electrically connected) to the first scan signal line 151 positioned on the third conductive layer CL3 through the opening formed in (or passing through) the third insulating layer 160.
The initialization transistor T3 may have a channel, a first area, and a second area in the third semiconductor 133a, 133b, or 133c positioned on the first insulating layer 120, and the first area and the second area may be doped to have the same or similar conductive characteristics as a conductor. The first area of the third semiconductor 133a, 133b, or 133c may be connected to the protrusion 1751a, 1751b, or 1751c from which the upper storage electrode 175a, 175b, or 175c extends in the x-axis direction through the opening formed in (or passing through) the third insulating layer 160. For example, the upper storage electrode 175a, 175b, or 175c may be connected (e.g., electrically connected) to the lower storage electrode 125a, 125b, or 125c through the opening formed in (or passing through) the first insulating layer 120 and the third insulating layer 160, and may be connected (e.g., electrically connected) to the first semiconductor 131a, 131b, or 131c through the opening formed in (or passing through) the third insulating layer 160. The second area of the third semiconductor 133a, 133b, or 133c may be connected (e.g., electrically connected) to the initialization voltage connecting portion 173-3v through the opening formed in (or passing through) the third insulating layer 160 to receive the initialization voltage VINT. The gate electrode 157 may be formed on the third semiconductor 133a, 133b, or 133c. For example, the second insulating layer 140 may be positioned between the third semiconductor 133a, 133b, or 133c and the gate electrode 157. In a plan view, a channel may be formed in the third semiconductor 133a, 133b, or 133c overlapping the gate electrode 157, and the channel may be covered by the gate electrode 157 such that the channel may not be doped. The gate electrode 157 may extend to be connected (e.g., electrically connected) to the second scan signal line 151-1 positioned on the third conductive layer CL3 through the opening formed in (or passing through) the third insulating layer 160.
As shown in
For example, the upper storage electrode 175a, 175b, or 175c may include a protrusion 1751a, 1751b, or 1751c extending and protruding in the x-axis direction. Each protrusion 1751a, 1751b, or 1751c may cross the driving voltage line 172v to overlap the third semiconductor 133a, 133b, or 133c. The protrusion 1751a, 1751b, or 1751c may be positioned between the driving voltage connecting portions 172-3v spaced apart from each other. Since the protrusion 1751a, 1751b, or 1751c is connected (e.g., electrically connected) to the third semiconductor 133a, 133b, or 133c through the opening, the third semiconductor 133a, 133b, or 133c may be connected (e.g., electrically connected) to the upper storage electrode 175a. 175b, or 175c without overlapping the driving voltage line 172v.
As the upper storage electrode 175a, 175b, or 175c is connected to the third semiconductor 133a, 133b, or 133c by the protrusion 1751a, 1751b, or 1751c extending and protruding in the x-axis direction as described above, the third semiconductor 133a, 133b, or 133c may not cross the driving voltage line 172v positioned (or included) in the first conductive layer CL1. Accordingly, the problem in which the semiconductor layer ACT is cut or the inorganic insulating layer (e.g., 120, 140, or 160) on the semiconductor layer ACT is cut due to the step (or step difference) of the first conductive layer CL1 may be solved or prevented.
The storage capacitor Cst may include a first storage capacitor Cst1 and a second storage capacitor Cst2.
The first storage capacitor Cst1 may be formed of the gate electrode 155a, 155b, or 155c positioned (or included) in the second conductive layer CL2, the third insulating layer 160 positioned thereon, and the upper storage electrode 175a, 175b, or 175c positioned thereon. The second storage capacitor Cst2 may be formed of the lower storage electrode 125a, 125b, or 125c positioned (or included) in the first conductive layer CL1, the first insulating layer 120 positioned thereon, and the gate electrode 155a, 155b, or 155c positioned thereon. As a result, the storage capacitor Cst may have a triple-layered structure of two storage electrodes (the upper storage electrode 175a, 175b, or 175c and the lower storage electrode 125a, 125b, or 125c) overlapping at upper and lower portions thereof in a plan view with using the gate electrode 155a, 155b, or 155c between the two storage electrodes.
The lower storage electrode 125a, 125b, or 125c and the upper storage electrode 175a. 175b, or 175c may be connected (e.g., electrically connected) to each other through opening formed in (or passing through) the first insulating layer 120 and the third insulating layer 160, and since the gate electrode 155a, 155b, or 155c is commonly included in the first storage capacitor Cst1 and the second storage capacitor Cst2, the first storage capacitor Cst1 and the second storage capacitor Cst2 may be connected in parallel in terms of a circuit structure. Since the circuit structure has a parallel-connected structure, total capacitance of the storage capacitor Cst may be a sum of capacitance of the first storage capacitor Cst1 and capacitance of the second storage capacitor Cst2.
The upper storage electrodes 175a, 175b, and 175c may be integral, and may be connected (e.g., electrically connected) to anodes of the light emitting diodes EDa, EDb, and EDc through openings 185a, 185b, and 185c formed in the fourth insulating layer 180. In some embodiments, an additional member (or anode connecting member) for connecting the upper storage electrodes 175a, 175b, and 175c and the anodes may be further included.
The light emitting diode EDa, EDb, or EDc may include an anode (e.g., 191 in
In some embodiments, the light emitting layer 370 may be formed only within the opening of the definition wall 350, but according to the embodiment of
An encapsulation layer, a color conversion layer, or a color filter may be formed on the light emitting diodes EDa, EDb, and EDc, and this structure will be described with reference to
The structure of the pixels PXa, PXb, and PXc of the display device 1 according to an embodiment has been described in detail.
The main feature of the invention may be to prevent damage to the semiconductor layer ACT and an inorganic layer ILD on the semiconductor layer ACT due to the step (or step difference) of the first conductive layer CL1 by preventing the semiconductor layer ACT from overlapping the first conductive layer CL1.
Referring to
Referring to
Referring to
Referring to
For example, in the portion in which the semiconductor layer ACT overlaps the first conductive layer CL1, as in the first semiconductor 131a, an upper portion of an overlapping boundary area may be covered by the third conductive layer CL3. Therefore, in case that the inorganic insulating layer (e.g., 120, 140, or 160) is broken at the overlapping portion thereafter, since the upper portion of the inorganic insulating layer (e.g., 120, 140, or 160) is covered with the third conductive layer CL3, a hydrogen penetration path may be blocked by the third conductive layer CL3.
For example, in the display device 1 according to an embodiment, as illustrated in
As illustrated in
For example, a portion of the semiconductor layer ACT may be damaged due to a step (or step difference) of the light blocking member BML. In
Referring to
In
Referring to
In the stacked structure of the display device 1, the organic layer VIA may be positioned on the inorganic layer ILD, and the organic layer VIA may include hydrogens. For example, hydrogen included in the organic layer VIA may diffuse into the semiconductor layer ACT through the damaged inorganic layer ILD to affect performance of the transistor. In
However, in the display device 1 according to an embodiment, as discussed above, the second semiconductor 132a and the third semiconductor 133a may not overlap the first conductive layer CL1, and the portion in which the first semiconductor 131a overlaps the first conductive layer may be covered with the third conductive layer SD (or CL3), so that the diffusion of hydrogen may be prevented.
In the above, the embodiment in which the upper portion of the boundary area in which the first semiconductors 131a, 131b, and 131c overlap the first conductive layer CL1 is covered by the third conductive layer SD (or CL3) and in which the portions of the second semiconductors 132a, 132b, and 132c and the third semiconductors 133a, 133b, and 133c may not overlap the first conductive layer CL1 has been described.
However, in the display device 1 according to an embodiment, as shown in
For example, the cover member 178 may be also positioned at the boundary portion where the third semiconductors 133a, 133b, and 133c and the initialization voltage line 173 overlap. As shown in
In Equation 1, the Skew may be a skew value during etching of the first and third conductive layers CL1 and CL3, and the CD deviation and the overlay tolerance may be unique values derived from each process. For example, the width W of the cover member 178 may vary according to materials and process situations of respective conductive layers included in the display device 1.
As described above, the display device 1 may connect the semiconductor layer ACT and the first conductive layer CL1 with the third conductive layer CL3 so that the semiconductor layer ACT and the first conductive layer CL1 may not overlap, or the third conductive layer CL3 may cover the boundary portion of the overlapping area of the semiconductor layer ACT and the first conductive layer CL1. Accordingly, the semiconductor layer ACT or the inorganic insulating layer (e.g., 120, 140, or 160) on the semiconductor layer ACT may be prevented from being damaged in the overlapping area of the semiconductor layer ACT and the first conductive layer CL1, and in case that the semiconductor layer ACT or the inorganic insulating layer (e.g., 120, 140, or 160) is damaged. For example, hydrogen may be prevented from diffusing into the semiconductor layer ACT by covering the upper portion of the damaged area with the third conductive layer CL3. Accordingly, the performance of the transistor may be stably maintained.
For example, in the display device 1, a light emitting diode including an anode, a light emitting layer, and a cathode may be formed on the fourth insulating layer, and an encapsulation layer, a color converting layer, or a color filter may be additionally included on the light emitting diode. Hereinafter, a cross-sectional structure of the display device 1 will be described in detail with reference to
In
The display device 1 according to
As shown in
The definition wall 350 may be positioned on the anode 191, and the definition wall 350 may include an opening exposing a portion of the anode 191.
The light emitting layer 370 may be positioned on the anode 191 and the definition wall 350. In an embodiment, the light emitting layer 370 may be positioned on the entire area. For example, the light emitting layer 370 may be a light emitting layer that emits first color light (e.g., blue light). In some embodiments, the light emitting layer 370 may have a multi-layered structure. For example, the light emitting layer 370 may have a multi-layered structure emitting blue light and green light. In another example, the light emitting layer 370 may have a structure in which a layer emitting blue light is multi-layered. In some embodiments, the light emitting layer 370 may have a structure in which layers respectively emitting blue light, green light, and red light are stacked.
In some embodiments, the light emitting layers 370 may be formed to be separated from each other around the opening of each pixel. For example, the light emitting layers of respective pixels may emit light of different colors. The cathode 270 may be disposed (e.g., entirely disposed) on the light emitting layer 370.
The encapsulation layer 380 including insulating layers 381, 382, and 383 may be positioned on the cathode 270. The insulating layer 381 and the insulating layer 383 may include an inorganic insulating material, and the insulating layer 382 positioned between the insulating layer 381 and the insulating layer 383 may include an organic insulating material.
A filling layer 390 including a filler may be positioned on the encapsulation layer 380.
The filling layer 390 may be a layer for combining the display panel 100 including the first substrate 110 and the color converting panel 200 including a second substrate 210. Hereinafter, the color converting panel 200 will be described.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
For example, the blue dummy color filter 231B may be positioned closer to the second substrate 210 than the red dummy color filter 231R and the green dummy color filter 231G. A direction, in which a user views an image, is toward the second substrate 210, and the blue dummy color filter 231B may be positioned on a surface on which the image is viewed. This is because, blue light has a reflectance lower than green light or red light, and is effectively blocked as compared with green light or red light.
Referring to
Banks 320 may be positioned on the low refractive layer 351. The banks 320 may be positioned to be spaced apart from each other with openings therebetween, and each opening may overlap each of the color filters 230R, 230G, and 230B in a direction perpendicular to the surface of the second substrate 210.
The bank 320 may include a scatterer. The scatterer may be one or more of SiO2. BaSO4, Al2O3, ZnO, ZrO2, and TiO2. The bank 320 may include a polymer resin and a scatterer included in the polymer resin. A content of the scatterer may be about 0.1 wt % to about 20 wt %. For example, the content of the scatterer may be about 5 wt % to about 10 wt %. The bank 320 including the scatterer may scatter the light emitted from the display panel to increase the luminous efficiency. In an embodiment, the bank 320 may include a black material to block light, and may prevent color mixing between neighboring light emitting areas.
A red color converting layer 330R and a transmissive layer 330B may be positioned in an area between the banks 320 spaced apart from each other. In
Hereinafter, the quantum dot will be described.
A core of the quantum dot may be selected from a group II-VI compound, a group III-V compound, a group IV-VI compound, a group IV element, a group IV compound, and a combination thereof.
The Group II-VI compound may be selected from a two-element compound selected from CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and a mixture thereof; a three-element compound selected from AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, and a mixture thereof; and a four-element compound selected from HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, and a mixture thereof.
The Group III-V compound may be selected from a two-element compound selected from GaN, GaP, GaAs, GaSb, AlN, AIP, AlAs, AlSb, InN, InP, InAs, InSb, and a mixture thereof; a three-element compound selected from GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InNAs, InNSb, InPAs, InPSb, GaAlNP, and a mixture thereof; and a four-element compound selected from GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GalnNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and a mixture thereof.
The Group IV-VI compound may be selected from a two-element compound selected from SnS, SnSc, SnTe, PbS, PbSe, PbTe, and a mixture thereof; a three-element compound selected from SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and a mixture thereof; and a four-element compound selected from SnPbSSe, SnPbSeTe, SnPbSTe, and a mixture thereof. The Group IV element may be selected from Si, Ge, and a mixture thereof. The Group IV compound may be a two-element compound selected from SiC, SiGe, and a mixture thereof.
For example, the two-element compound, the three-element compound, or the four-element compound may be included in particles at uniform concentrations, or they may be divided into states having partially different concentrations to be included in the same particle, respectively. For example, a core/shell structure in which some quantum dots enclose some other quantum dots may be applied. An interface between the core and the shell may have a concentration gradient in which a concentration of elements of the shell decreases closer to its center.
In some embodiments, the quantum dot may have a core-shell structure that includes a core including the nanocrystal described above and a shell surrounding the core. The shell of the quantum dot may function as a passivation layer for maintaining a semiconductor characteristic and/or as a charging layer for applying an electrophoretic characteristic to the quantum dot by preventing chemical denaturation of the core. The shell may be a single layer or a multilayer. An interface between the core and the shell may have a concentration gradient in which a concentration of elements of the shell decreases closer to the center thereof. An example of the shell of the quantum dot may include a metal or nonmetal oxide, a semiconductor compound, or a combination thereof.
For example, the metal or non-metal oxide may be a binary element compound such as SiO2. Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, NiO, and the like, or a ternary element compound such as MgAl2O4, CoFe2O4, NiFe2O4, CoMn2O4, and the like, but embodiments are not limited thereto.
The semiconductor compound may be CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSc, HgTe, InAs, InP. InGaP, InSb, AlAs, AlP. AlSb, or the like, but embodiments are not limited thereto.
The quantum dot may have a full width at half maximum (FWHM) of the light-emitting wavelength spectrum that is equal to or less than about 45 nm, e.g., equal to or less than about 40 nm, and, e.g., equal to or less than about 30 nm, and in this range, color purity or color reproducibility may be improved. Since light emitted through the quantum dot is emitted in all directions, a viewing angle of light may be improved.
Further, a shape of the quantum dot is not limited to a shape used in the art, and may have a spherical, pyramidal, multi-arm, cubic nanoparticle, nanotube, nano-wire, nano-fiber, nano-plate particle shape, and the like.
The quantum dot may control a color of emitted light according to a particle size thereof, and thus the quantum dot may have various light emitting colors such as blue, red, and green colors.
Referring to
As described above, in the color converting panel according to an embodiment and the display device 1 including the color converting panel, the red light emitting area RLA may convert the incident light to red light to emit the converted red light. The green light emitting area GLA may convert the incident light into green light to emit the converted green light. However, the blue light emitting area BLA may transmit the incident light without color conversion. The incident light may include blue light. The incident light may be blue light alone or a mixture of blue light and green light. In another example, it may include all of blue light, green light, and red light.
In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the embodiments without substantially departing from the principles and spirit and scope of the disclosure. Therefore, the disclosed embodiments are used in a generic and descriptive sense only and not for purposes of limitation.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0033556 | Mar 2022 | KR | national |
