Patent Application
20230360606
The present disclosure relates to a display device.
As information society has developed, various types of display devices have been developed. In recent years, various display devices, such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light-emitting diode (OLED) display, have been used.
Among them, the organic light-emitting diode display displays an image by using an organic light-emitting device. The organic light-emitting device (hereinafter, referred to as light-emitting device) is self-luminous and does not require a separate light source, so that the thickness and the weight of the display device are reduced. In addition, the organic light-emitting diode display has high quality characteristics, such as low power consumption, high luminance, and a high response rate.
The foregoing is intended merely to aid in the understanding of the background of the present disclosure, and is not intended to mean that the present disclosure falls within the purview of the related art that is already known to those skilled in the art.
The embodiments provide a display device in which a high-potential driving voltage and a data signal that are applied to a display panel are coupled.
The embodiments provide a display device including a power supply provided with a capacitor for coupling a gamma compensation voltage and a high-potential driving voltage.
The embodiments provide a display device including a gamma generator provided with a capacitor for coupling a feedback voltage of a high-potential driving voltage and a gamma reference voltage.
According to an embodiment, there is provided a display device includes: an input terminal through which a feedback voltage of a high-potential driving voltage is received from a display panel; an output terminal through which a high reference voltage and a low reference voltage generated on the basis of the feedback voltage are output; and a flexible printed circuit board (FPCB) comprising at least one capacitor connected between the input terminal and the output terminal.
The output terminal may include a first output terminal through which the high reference voltage is output, and a second output terminal through which the low reference voltage is output, and the at least one capacitor may include a first capacitor connected between the input terminal and the first output terminal, and a second capacitor connected between the input terminal and the second output terminal.
The FPCB may include at least one voltage division circuit that divides a voltage between the high reference voltage and the low reference voltage and thus generates a gamma compensation voltage.
The high reference voltage and the low reference voltage may be coupled with the feedback voltage by the first capacitor and the second capacitor, respectively, and the gamma compensation voltage may be coupled with the high reference voltage and the low reference voltage.
The FPCB may further include: a third output terminal through which a driver driving voltage is output to the at least one voltage division circuit; a fourth output terminal through which the high-potential driving voltage is output to the display panel; and a third capacitor connected between the third output terminal and the fourth output terminal.
The at least one voltage division circuit may generate the gamma compensation voltage on the basis of the driver driving voltage.
The driver driving voltage and the high-potential driving voltage may be coupled with each other by the third capacitor.
The display device may further include: the display panel including pixels driven by the high-potential driving voltage, and being connected to the FPBC; and a data driver placed on the FPCB, and applying a data signal generated on the basis of the gamma compensation voltage to the pixels.
A phase of the data signal may be synchronized with a phase of the gamma compensation voltage, and a phase of the high-potential driving voltage and the phase of the data signal that are applied to the pixels may be synchronized with each other.
The at least one voltage division circuit may include: an adaptive voltage adjustment circuit adaptively adjusting the feedback voltage received through the input terminal and outputting an adjusted power supply voltage; a first voltage generator generating the high reference voltage from the adjusted power supply voltage and outputting the high reference voltage through the first output terminal; and a second voltage generator generating the low reference voltage from the adjusted power supply voltage and outputting the low reference voltage through the second output terminal.
The at least one voltage division circuit may further include: a first voltage division circuit dividing a voltage between the high reference voltage and the low reference voltage, and thus generating multiple voltages; a first voltage selector selecting a voltage indicated by a register setting value among the multiple voltages generated by the first voltage division circuit, and thus generating multiple reference voltages; a second voltage division circuit dividing the multiple reference voltages, and thus generating multiple voltages at different voltage levels; a multiplexer selecting, as a reference voltage, a voltage indicated by a register setting value among the multiple voltages generated by the second voltage division circuit; and a gamma voltage generator dividing the selected reference voltage and thus generating the gamma compensation voltages corresponding to all grayscales.
According to an embodiment, a display device including: a display panel provided with a plurality of pixels; a power supply applying a high-potential driving voltage to the pixels; a gamma generator receiving a feedback voltage of the high-potential driving voltage from the display panel, and generating a gamma compensation voltage on the basis of the feedback voltage; and a data driver supplying a data voltage to the pixels on the basis of the gamma compensation voltage supplied from the gamma generator, wherein the gamma generator includes: an input terminal through which the feedback voltage is received; an output terminal through which a high reference voltage and a low reference voltage generated on the basis of the feedback voltage are output; at least one voltage division circuit dividing a voltage between the high reference voltage and the low reference voltage, and thus generating the gamma compensation voltage; and at least one capacitor connected between the input terminal and the output terminal.
The output terminal may include a first output terminal through which the high reference voltage is output, and a second output terminal through which the low reference voltage is output, and the at least one capacitor may include a first capacitor connected between the input terminal and the first output terminal, and a second capacitor connected between the input terminal and the second output terminal.
The high reference voltage and the low reference voltage may be coupled with the feedback voltage by the first capacitor and the second capacitor, respectively, and the gamma compensation voltage may be coupled with the high reference voltage and the low reference voltage.
The power supply may include: a third output terminal through which a driver driving voltage is output to at least one among the data driver and the gamma generator; a fourth output terminal through which the high-potential driving voltage is output to the display panel; and a third capacitor connected between the third output terminal and the fourth output terminal.
The at least one voltage division circuit may generate the gamma compensation voltage on the basis of the driver driving voltage.
The driver driving voltage and the high-potential driving voltage may be coupled with each other by the third capacitor.
A phase of the high-potential driving voltage and a phase of the data voltage that are applied to the pixels may be synchronized with each other.
According to an embodiment, there is provided a display device including: a display panel including pixels; a data driver generating a data signal on the basis of a gamma compensation voltage, and applying the data signal to the pixels; and an FPCB connected to the display panel and the data driver, wherein the FPCB includes: a third output terminal through which a driver driving voltage is output to the data driver; at least one voltage division circuit generating the gamma compensation voltage on the basis of the driver driving voltage; a fourth output terminal through which a high-potential driving voltage is output to the pixels; and a third capacitor connected between the third output terminal and the fourth output terminal.
The driver driving voltage and the high-potential driving voltage may be coupled with each other by the third capacitor.
The display device according to the embodiments synchronizes the phase of the high-potential driving voltage and the phase of the data signal, so that it is possible to prevent a glitch in the high-potential driving voltage caused by an rapid decrease in the current applied to the panel and prevent the dip effect in the high-potential driving voltage caused by a rapid increase in the current.
The display device according to the embodiments may solve the problem of a bright line and a dark line that are caused by the occurrence of the rapid difference in phase between the high-potential driving voltage and the data signal.
The display device according to the embodiments synchronizes the phase of the high-potential driving voltage and the phase of the data signal in real time without using a separate processor, whereby a rapid-driving display device is implemented.
The above and other objectives, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:
Hereinafter, embodiments will be described with reference to the accompanying drawings. In the specification, when an element (area, layer, part, or the like) is referred to as being “coupled to,” or “combined with” another element, it may be directly coupled to/combined with the other element or an intervening element may be present therebetween. The term “and/or” includes one or more combinations that the associated elements may define.
Terms “first,” “second,” etc., can be used to describe various elements, but the elements are not to be construed as being limited to the terms. The terms are only used to differentiate one element from other elements. For example, the “first” element may be named the “second” element without departing from the scope of the embodiments, and the “second” element may also be similarly named the “first” element. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It is to be understood that terms such as “including,” “having,” etc., are intended to indicate the existence of the features, numbers, steps, actions, elements, components, or combinations thereof disclosed in the specification, and are not intended to preclude the possibility that one or more other features, numbers, steps, actions, elements, components, or combinations thereof may exist or may be added.
Referring to
The timing controller 10 may receive an image signal RGB and a control signal CS from outside. The image signal RGB may include multiple grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.
The timing controller 10 may process the image signal RGB and the control signal CS to make the signals appropriate for an operation condition of the display panel 70, so that the timing controller 10 may generate and output image data DATA, a gate driving control signal CONT1, a data driving control signal CONT2, a light-emission driving control signal CONT4, and a power supply control signal CONT3.
The gate driver 20 may be connected to pixels (or subpixels) PXs of the display panel 70 through multiple gate lines GL1 to GLn. The gate driver 20 may generate gate signals on the basis of the gate driving control signal CONT1 output from the timing controller 10. The gate driver 20 may provide the generated gate signals to the pixels PXs through the multiple gate lines GL1 to GLn.
The light-emission driver 30 may be connected to the pixels PXs of the display panel 70 through multiple light-emission lines EL1 to ELn. The light-emission driver 30 may generate light-emission signals on the basis of the light-emission driving control signal CONT4 output from the timing controller 10. The light-emission driver 30 may provide the generated light-emission signals to the pixels PXs through the multiple light-emission lines EL1 to ELn.
The data driver 40 may be connected to the pixels PXs of the display panel 70 through multiple data lines DL1 to DLm. The data driver 40 may generate data signals on the basis of the image data DATA and the data driving control signal CONT2 output from the timing controller 10. The data driver 40 may receive gamma compensation voltages VGs generated from the gamma generator 50, may select the voltage, among the gamma compensation voltages VGs, which corresponds to the grayscale of the image data DATA, and may generate data signals. The data driver 40 may provide the generated data signals to the pixels PXs through the multiple data lines DL1 to DLm.
The gamma generator 50 generates the gamma compensation voltages VGs on the basis of a driver driving voltage DDVDH generated from the power supply 60. In an embodiment, the gamma generator 50 may generate gamma compensation voltages VGs on the basis of a feedback voltage VDDEL′, which is applied from the display panel 70, for a high-potential driving voltage VDDEL. The gamma generator 50 may transmit the generated gamma compensation voltages VGs to the data driver 40.
The power supply 60 may be connected to the pixels PXs of the display panel 70 through multiple power lines PL1 and PL2. The power supply 60 may generate a driving voltage to be provided to the display panel 70, on the basis of the power supply control signal CONT3. The driving voltage may include, for example, a high-potential driving voltage VDDEL and a low-potential driving voltage VSSEL. The power supply 60 may provide the generated driving voltages VDDEL and VSSEL to the pixels PXs, through the corresponding power lines PL1 and PL2.
In an embodiment, the power supply 60 may further generate the driver driving voltage DDVDH for driving the data driver 40 and the gamma generator 50. The power supply 60 may supply the generated driver driving voltage DDVDH to the data driver 40 and the gamma generator 50.
In the display panel 70, the multiple pixels PXs (or, referred to as subpixels) are arranged. The pixels PXs may be, for example, arranged in a matrix form on the display panel 70.
Each of the pixels PXs may be electrically connected to the corresponding gate line, the corresponding light-emission line, and the corresponding data line. Such pixels PXs may emit light with luminance corresponding to the gate signals, the light-emission signals, and the data signals that are supplied through the gate lines GL1 to GLn, the light-emission lines EL1 to ELn, and the data lines DL1 to DLm, respectively.
Each pixel PX may display any one among a first to a third color. In an embodiment, each pixel PX may display any one among red, green, and blue colors. In another embodiment, each pixel PX may display any one among cyan, magenta, and yellow colors. In various embodiments, the pixels PXs may be configured to display any one among four or more colors. For example, each pixel PX may display any one among red, green, blue, and white colors.
The timing controller 10, the gate driver 20, the data driver 40, and the power supply 60 may be configured as separate integrated circuits (ICs), or ICs in which at least some thereof are integrated. For example, at least one or some of the timing controller 10, the data driver 40, the gamma generator 50, and the power supply 60 may be configured as an integrated circuit. Such an integrated circuit may be implemented in the form of, for example, a flexible printed circuit board (FPCB). An embodiment in which the gamma generator 50 and the power supply 60 are implemented as an FPCB is show in
In
Referring to
A first transistor M1 is connected between a first node N1 and a second node N2. A gate electrode of the first transistor M1 is connected to the i-th gate line GLi. The first transistor M1 is turned on when a gate signal at a gate-on level is applied through the i-th gate line GLi, and connects the first node N1 and the second node N2. Herein, the first node N1 is further connected to a gate electrode of the driving transistor DT, and a first electrode of the storage capacitor Cst. The second node N2 is further connected to a drain electrode of the driving transistor DT, and a source electrode of a fourth transistor M4.
A second transistor M2 is connected between the data line DLj and a third node N3. A gate electrode of the second transistor M2 is connected to the i-th gate line GLi. The second transistor M2 is turned on when a scan signal at a gate-on level is applied through the i-th gate line GLi, and transmits the data signal applied through the data line DLj, to the third node N3. Herein, the third node N3 is further connected to a source electrode of the driving transistor DT, and a drain electrode of a third transistor M3.
The third transistor M3 is connected between the third node N3 and a first power line PL1 through which the high-potential driving voltage VDDEL is applied. A gate electrode of the third transistor M3 is connected to the i-th light-emission line ELi. The third transistor M3 is turned on when a light-emission signal at a gate-on level is applied through the i-th light-emission line ELi, and applies the high-potential driving voltage VDDEL to the third node N3.
The fourth transistor M4 is connected between the second node N2 and an anode electrode of the light-emitting device EL. A gate electrode of the fourth transistor M4 is connected to the i-th light-emission line ELi. The fourth transistor M4 is turned on when a light-emission signal at a gate-on level is applied through the i-th light-emission line ELi, and connects the second node N2 and the anode electrode of the light-emitting device EL.
A fifth transistor M5 is connected between the first node N1 and an initialization power line PL3 through which an initialization power Vini is applied. A gate electrode of the fifth transistor M5 is connected to an i-1-th gate line GL(i-1). The fifth transistor M5 is turned on when a gate signal at a gate-on level is applied through the i-1-th gate line GL(i-1), and applies the initialization power Vini to the first node N1.
A sixth transistor M6 is connected between the initialization power line PL3 through the initialization power Vini is applied, and the anode electrode of the light-emitting device EL. A gate electrode of the sixth transistor M6 is connected to the i-1-th gate line GL(i-1). The sixth transistor M6 is turned on when a gate signal at a gate-on level is applied through the i-1-th gate line GL(i-1), and applies the initialization power Vini to the anode electrode of the light-emitting device EL.
The driving transistor DT is connected between the second node N2 and the third node N3. The gate electrode of the driving transistor DT is connected to the first node N1. The driving transistor DT adjusts the amount of the current flowing to the light-emitting device EL, in response to the difference in voltage between the first node N1 and the third node N3.
The first electrode of the storage capacitor Cst is connected to the first node N1, and a second electrode of the storage capacitor Cst is connected to the first power line PL1 through which the high-potential driving voltage is applied. The storage capacitor Cst is charged with a data voltage to which compensation for the threshold voltage of the driving transistor DT is applied, and data is sampled. In the pixel PXij, the compensation for the threshold voltage of the driving transistor DT is applied to the data voltage. Thus, compensation for the variations in characteristic between the driving transistors DTs of the respective pixels (PXij) takes place, and the pixels (PXij) may be driven with the uniform characteristics.
The light-emitting device EL outputs light corresponding to a driving current. The amount of driving current flowing to the light-emitting device EL may be controlled through the driving transistor DT. In addition, the current passing to the light-emitting device EL is switched by the third and the fourth transistors M3 and M4.
The light-emitting device EL may output light corresponding to any one among red, green, and blue colors. The light-emitting device EL may be an organic light-emitting diode (OLED) or an ultra-small inorganic light-emitting diode having a size in a micro to nanoscale range, but the present disclosure is not limited thereto. Hereinafter, embodiments in which the light-emitting device EL is configured as an organic light-emitting diode (OLED) will be described.
Such a pixel PXij include an internal compensation circuit for sensing the threshold voltage of the driving transistor DT and compensating for the threshold voltage with respect to the data voltage. Being embedded in each of the pixels (PXij), the internal compensation circuit senses the threshold voltage of the driving transistor DT in each of the pixels (PXij), and compensates with respect to the data voltage in real time accordingly. However, in this embodiment, the structure of the pixels (PXij) is not limited to that shown in
Referring to
The shift register 41 generates a sampling signal by using the data driving control signal CONT2 received from the timing controller 10. For example, the shift register 41 may generate a sampling signal from a source start pulse and a source sampling clock signal included in the data driving control signal CONT2, and may generate a carry signal from the source start pulse.
The latch 42 sequentially samples digital image data DATA received from the timing controller 10 in response to the sampling signal. The latch 42 stores the sampled data, and outputs the sampled data all at once to the digital-to-analog converter 43 in response to a source output enable signal SOE received from the timing controller 10.
The digital-to-analog converter 43 receives a gamma compensation voltage VG from the gamma generator 50, converts the sampled data output from the latch 42 according to the gamma compensation voltage VG, and outputs the resulting data. Herein, the gamma compensation voltage VG may include analog data voltages that correspond to grayscales of the digital image signal RGB, respectively.
The output buffer 44 outputs the data voltages input from the digital-to-analog converter 43, to the data lines DL1 to DLm of the display panel 70, by using a voltage follower implemented as an operational amplifier (OP-AMP).
The gamma generator 50 may receive the feedback voltage VDDEL′ for the high-potential driving voltage VDDEL applied to the display panel 70, and may generate a gamma compensation voltage VG for grayscale voltage compensation, on the basis of the received feedback voltage VDDEL′.
Referring to
The gamma generator 50 receives, from the display panel 70, the feedback voltage VDDEL′ for the high-potential driving voltage VDDEL applied to the display panel 70. The gamma generator 50 generates, on the basis of the received feedback voltage VDDEL′, a gamma reference voltage Vref for generating a gamma compensation voltage VG. The gamma reference voltage Vref may include, for example, a high reference voltage VREG1_REF2047 and a low reference voltage VREG1_REF1.
The gamma voltage generator 52 may generate a gamma compensation voltage VG from the gamma reference voltage Vref output from the reference voltage generator 51. For example, the gamma voltage generator 52 may generate multiple voltages by dividing a voltage between the high reference voltage VREG1_REF2047 and the low reference voltage VREG1_REF1, may select, among the generated voltages, a voltage indicated by a register setting value, and may thus generate gamma compensation voltages VGs corresponding to all the grayscales, respectively.
Hereinafter, the detailed configuration of the gamma generator 50 will be described.
Referring to
A first voltage generator 512 receives the adjusted power supply voltage VDD′ and generates the high reference voltage VREG1_REF2047. A second voltage generator 513 receives the adjusted power supply voltage VDD′ and generates the low reference voltage VREG1_REF1.
In this embodiment, an input terminal IN receives the feedback voltage VDDEL′, and output terminals OUT1 and OUT2 output the high reference voltage VREG1_REF2047 and the low reference voltage VREG1_REF1, respectively. A capacitor C1 may be connected between the input terminal IN and the output terminal OUT1, and a capacitor C2 may be connected between the input terminal IN and the output terminal OUT2. In an embodiment, capacitance values of a first and a second capacitor C1 and C2 may be about 1 uF, but the embodiment is not limited thereto.
The feedback voltage VDDEL′ input to the reference voltage generator 51 may include a ripple component of the high-potential driving voltage VDDEL introduced into the display panel 70. In general, a capacitor has a characteristic of passing an AC component of a signal. Therefore, when the capacitors C1 and C2 are connected between the input terminal IN and the output terminal OUT1, and between the input terminal IN and the output terminal OUT2, respectively, the ripple component of the feedback voltage VDDEL′ is introduced to the gamma reference voltage Vref. That is, the ripple component (phase) of the feedback voltage VDDEL′ and that of the gamma reference voltage Vref may be synchronized. Since the feedback voltage VDDEL′ include the ripple component of the high-potential driving voltage VDDEL introduced to the display panel 70, the ripple component of the high-potential driving voltage VDDEL introduced to the display panel 70 and that of the gamma reference voltage Vref may be synchronized with each other, consequently.
As described later, gamma compensation voltages VGs are generated by dividing the gamma reference voltage Vref provided from the reference voltage generator 51, and a data signal applied to the display panel 70 is generated on the basis of the gamma compensation voltages VGs. Therefore, when the ripple component of the high-potential driving voltage VDDEL and the ripple component of the gamma reference voltage Vref are synchronized with each other, the phase of the data voltage Vdata applied to the display panel 70 and the phase of the high-potential driving voltage VDDEL may be synchronized as shown in
When the data voltage Vdata is applied to the display panel 70, the high-potential driving voltage VDDEL is influenced by the phase of the data voltage Vdata. When the data voltage Vdata is slowly changed, the influence on the high-potential driving voltage VDDEL does not affect the display performance. However, when the data voltage Vdata is rapidly changed, the change in the phase of the data voltage Vdata causes the ripple component of the high-potential driving voltage VDDEL.
When the high-potential driving voltage VDDEL has an abnormal peak (for example, a peak in the opposite phase) due to the ripple component, an unwanted voltage is applied to the pixels PXs of the display panel 70 and a bright line or dark line may be viewed.
In this embodiment, the data voltage Vdata has the phase synchronized with the ripple component of the high-potential driving voltage VDDEL. Thus, even if an abnormal phase variation occurs in the high-potential driving voltage VDDEL, the voltage value of the data voltage Vdata is changed according to the phase and thus an abnormal voltage is not applied to the pixels PXs.
As described above, in this embodiment, the difference in phase between the data voltage Vdata and the high-potential driving voltage VDDEL is minimized or reduced, so that a bright line and a dark line may be prevented from occurring on the display panel 70.
Referring to
A first voltage division circuit RS1 divides a voltage between the high reference voltage VREG1_REF2047 and the low reference voltage VREG1_REF1 and thus generates multiple voltages between the high reference voltage VREG1_REF2047 and the low reference voltage VREG_REF1. A first voltage selector MUX1 selects a voltage indicated by a register setting value among the voltages that result from the division by the first voltage division circuit RS1, and outputs a first to a sixth reference voltages VG0, VG1_REF63, VG1_REF407, VG1_REF815, VG1_REF1227, and VG1_REF1635. A second voltage division circuit RS2 divides the first to the sixth reference voltages VG0, VG1_REF63, VG1_REF407, VG1_REF815, VG1_REF1227, and VG1_REF1635, and thus generates multiple voltages at different voltage levels.
A multiplexer MUX connected to an output terminal of the second voltage division circuit RS2 selects, as a reference voltage VREG1, a value indicated by a register setting value among the voltages that result from the division by the second voltage division circuit RS2.
Through voltage division circuits to which the reference voltage VREG1 is input and voltage selectors, the gamma voltage generator 52 generates multiple voltages at different voltage levels, and generates gamma compensation voltages VG0 to VG256 of all the grayscales in accordance with a voltage indicated by a register setting value.
For example, the gamma voltage generator 52 may first divide the reference voltage VREG1 through a string of registers Rs, and may thus generate multiple voltages at different voltage levels. Herein, the gamma voltage generator 52 may divide a voltage between the reference voltage VREG1 and a gamma ground voltage VGS for limiting a range of gamma compensation voltages, and may thus generate multiple voltages. In an embodiment, the gamma ground voltage VGS may be 0 V, but the embodiment is not limited thereto.
The gamma voltage generator 52 selects voltages indicated by register setting values AM0, AM1, AM2 among the generated multiple voltage, and generates some gamma compensation voltages including a high-potential gamma compensation voltage and a low-potential gamma compensation voltage. The gamma voltage generator 52 second divides a voltage between the some gamma compensation voltages through a string of registers Rs, and thus generates multiple intermediate voltages. The gamma voltage generator 52 selects, among the generated intermediate voltages, voltages indicated by register setting values GRO to GR7, and FP_AM2, as final intermediate voltages.
The gamma voltage generator 52 third divides the selected intermediate voltages through a string of registers Rs, and may thus generate gamma compensation voltages corresponding to all the grayscales.
Referring to
The power supply 60 may include a circuit 61 for generating voltages. The circuit may include, for example, a charge pump, a regulator, a buck converter, a boost converter, and the like.
The voltages generated from the power supply 60 may be applied to the data driver 40, the gamma generator 50, and the display panel 70. The power supply 60 may supply the driver driving voltage DDVDH to the data driver 40. In an embodiment, the driver driving voltage DDVDH may be applied to the digital-to-analog converter 43, the output buffer 44, and the like of the data driver 40. In addition, the power supply 60 may supply the driver driving voltage DDVDH to the gamma generator 50. The driver driving voltage DDVDH supplied to the data driver 40 and the gamma generator 50 may be used to generate a data signal and a gamma compensation voltage VG.
The power supply 60 may apply the high-potential driving voltage VDDEL and the low-potential driving voltage VSSEL to the pixels PXs of the display panel 70.
In this embodiment, the power supply 60 may include a third capacitor C3 connected between output lines of the driver driving voltage DDVDH and the high-potential driving voltage VDDEL. In an embodiment, a capacitance value of the third capacitor C3 may be about 10 uF, but the embodiment is not limited thereto.
By the third capacitor C3, the phase of the driver driving voltage DDVDH and the phase of the high-potential driving voltage VDDEL may be synchronized. Accordingly, the difference in phase among the data voltage, the high-potential driving voltage VDDEL, and the gamma compensation voltage VG generated on the basis of the driver driving voltage DDVDH is minimized or reduced, so that a bright line and a dark line occurring in the display panel 70 may be prevented.
In an FPCB according to an embodiment, the gamma generator 50 and the power supply 60 are integrated.
The gamma generator 50 is provided with an input terminal IN through which the feedback voltage VDDEL′ is received from the display panel 70, and with output terminals OUT1 and OUT2 through which the high reference voltage VREG1_REF2047 and the low reference voltage VREG1_REF1 are output, respectively. In this embodiment, a capacitor C1 may be connected between the input terminal IN and the output terminal OUT1, and a capacitor C2 may be connected between the input terminal IN and the output terminal OUT2. The first and the second capacitor C1 and C2 couple the feedback voltage VDDEL′ and the reference voltages (Vref). In an embodiment, capacitance values of a first and a second capacitor C1 and C2 may be about 1 uF, but the embodiment is not limited thereto.
The power supply 60 is provided with a third output terminal OUT3 through which the driver driving voltage DDVDH is output, and with a fourth output terminal OUT4 through which the high-potential driving voltage VDDEL is output. In this embodiment, a third capacitor C3 may be connected between the third output terminal OUT3 and the fourth output terminal OUT4. The third capacitor C3 couples the driver driving voltage DDVDH and the high-potential driving voltage VDDEL. In an embodiment, a capacitance value of the third capacitor C3 may be about 10 uF, but the embodiment is not limited thereto.
The FPCB according to the embodiment as described above includes the capacitors C1, C2, and C3 among the high-potential driving voltage VDDEL and the voltages related to the gamma compensation voltage VG, specifically, the driver driving voltage DDVDH and the gamma reference voltage Vref, so as to couple the high-potential driving voltage VDDEL to the voltages related to the gamma compensation voltage VG. Accordingly, the difference in phase between the data voltage, which is generated from the gamma compensation voltage VG and is applied to the display panel 70, and the high-potential driving voltage VDDEL applied from the power supply 60 to the display panel 70 is minimized or reduced, so that even when the data voltage is rapidly changed, the phases of the high-potential driving voltage VDDEL and the data voltage are set to be the same, whereby image quality is improved.
It will be understood by those skilled in the art that the present disclosure can be embodied in other specific forms without changing the technical idea or essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and not restrictive. The scope of the present disclosure is characterized by the appended claims rather than the detailed description described above, and it should be construed that all alterations or modifications derived from the meaning and scope of the appended claims and the equivalents thereof fall within the scope of the present disclosure.
The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2019-0179738 | Dec 2019 | KR | national |
The present application is a Continuation of U.S. patent application Ser. No. 17/890,190, filed Aug. 17, 2022, which a Continuation of U.S. patent application Ser. No. 17/136,977, filed Dec. 29, 2020, which claims priority to Korean Patent Application No. 10-2019-0179738, filed Dec. 31, 2019, the entire contents of which are incorporated herein for all purposes by this reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17890190 | Aug 2022 | US |
| Child | 18356523 | US | |
| Parent | 17136977 | Dec 2020 | US |
| Child | 17890190 | US |
