CROSS-REFERENCE TO RELATED APPLICATION
This application claims the benefit of priority from Japanese Patent Application No. 2023-010351 filed on Jan. 26, 2023, the entire contents of which are incorporated herein by reference.
BACKGROUND
1. Technical Field
What is disclosed herein relates to a display device.
2. Description of the Related Art
Japanese Patent Application Laid-open Publication No. 2018-021974 (JP-A-2018-021974) describes a display device that includes a first light-transmitting substrate, a second light-transmitting substrate disposed so as to face the first light-transmitting substrate, a liquid crystal layer including polymer-dispersed liquid crystals filled between the first and the second light-transmitting substrates, and at least one light emitter disposed so as to face at least one of side surfaces of the first and the second light-transmitting substrates.
In the display device described in JP-A-2018-021974, a viewer on one surface side of a display panel can view a background on the other surface side opposite to the one surface side. Unless a peripheral region outside a display region transmits light, the background cannot be seen, which may cause a sense of discomfort. Therefore, the peripheral region outside the display region preferably also allows the background on the other surface side opposite to the one surface side to be seen from the one surface side. When the peripheral region outside the display region is see-through, unintended light may be visible in the peripheral region outside the display region
For the foregoing reasons, there is a need for a display device that restrains the unintended light from being visible in peripheral region outside the display region.
SUMMARY
According to an aspect, a display device includes: a display panel that comprises a first light-transmitting substrate, a second light-transmitting substrate facing the first light-transmitting substrate, and a liquid crystal layer between the first light-transmitting substrate and the second light-transmitting substrate, and has an active region capable of displaying an image as viewed in a direction orthogonal to the first light-transmitting substrate and a peripheral region outside the active region; a light-transmitting first base member bonded to the display panel; and a light source disposed so that light enters at least one of a side surface of the first light-transmitting substrate, a side surface of the second light-transmitting substrate, and a side surface of the first base member. The first base member is sized so as to overlap the active region and not to overlap the peripheral region.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view illustrating an example of a display panel according to an embodiment of the present disclosure;
FIG. 2 is a block diagram illustrating a display device according to a first embodiment of the present disclosure;
FIG. 3 is a timing diagram explaining timing of light emission by a light source in a field-sequential system of the first embodiment;
FIG. 4 is an explanatory diagram illustrating a relation between a voltage applied to a pixel electrode and a scattering state of a pixel;
FIG. 5 is a sectional view illustrating an example of a section of the display device;
FIG. 6 is a plan view illustrating a planar surface of the display device of FIG. 1;
FIG. 7 is an enlarged sectional view obtained by enlarging a liquid crystal layer portion of FIG. 5;
FIG. 8 is a sectional view for explaining a non-scattering state in the liquid crystal layer;
FIG. 9 is a sectional view for explaining the scattering state in the liquid crystal layer;
FIG. 10 is a plan view illustrating scan lines, signal lines, and a switching element in the pixel;
FIG. 11 is a plan view illustrating a holding capacitance layer in the pixel;
FIG. 12 is a plan view illustrating an auxiliary metal layer and an opening region in the pixel;
FIG. 13 is a plan view illustrating the pixel electrode in the pixel;
FIG. 14 is a plan view illustrating a light-blocking layer in the pixel;
FIG. 15 is a sectional view along XV-XV′ of FIG. 14;
FIG. 16 is a sectional view along XVI-XVI′ of FIG. 14;
FIG. 17 is a sectional view along XVII-XVII′ of FIG. 14;
FIG. 18 is a plan view for explaining a peripheral region of the first embodiment;
FIG. 19 is a plan view for explaining a display device of a first comparative example;
FIG. 20 is a plan view for explaining a display device of a second comparative example;
FIG. 21 is a sectional view illustrating an exemplary section of a display device according to a first modification;
FIG. 22 is a plan view illustrating a planar surface of the display device of FIG. 21; and
FIG. 23 is a plan view illustrating a planar surface of a display device different from that of the first modification.
DETAILED DESCRIPTION
The following describes a mode (embodiment) for carrying out the present disclosure in detail with reference to the drawings. The present disclosure is not limited to the description of the embodiment given below. Components described below include those easily conceivable by those skilled in the art or those substantially identical thereto. In addition, the components described below can be combined as appropriate. What is disclosed herein is merely an example, and the present disclosure naturally encompasses appropriate modifications easily conceivable by those skilled in the art while maintaining the gist of the disclosure. To further clarify the description, the drawings schematically illustrate, for example, widths, thicknesses, and shapes of various parts as compared with actual aspects thereof, in some cases. However, they are merely examples, and interpretation of the present disclosure is not limited thereto. The same element as that illustrated in a drawing that has already been discussed is denoted by the same reference numeral through the description and the drawings, and detailed description thereof will not be repeated in some cases where appropriate.
In this disclosure, when an element is described as being “on” another element, the element can be directly on the other element, or there can be one or more elements between the element and the other element.
First Embodiment
FIG. 1 is a perspective view illustrating an example of a display panel according to an embodiment of the present disclosure. FIG. 2 is a block diagram illustrating a display device according to a first embodiment of the present disclosure. FIG. 3 is a timing diagram explaining timing of light emission by a light source in a field-sequential system.
As illustrated in FIG. 1, a display device 1 includes a display panel 2, a light source 3, and a drive circuit 4. A direction PX denotes one direction in the plane of the display panel 2. A second direction PY denotes a direction orthogonal to the direction PX. A third direction PZ denotes a direction orthogonal to the PX-PY plane.
The display panel 2 includes an array substrate 10, a counter substrate 20, and a liquid crystal layer 50 (refer to FIG. 5). The array substrate 10 serves as a first light-transmitting substrate, and the counter substrate 20 serves as a second light-transmitting substrate. The counter substrate 20 faces a surface of the array substrate 10 in a direction orthogonal thereto (in the direction PZ illustrated in FIG. 1). In the liquid crystal layer 50 (refer to FIG. 5), polymer-dispersed liquid crystals LC are sealed by the array substrate 10, the counter substrate 20, and a sealing portion 18.
As illustrated in FIG. 1, the display panel 2 has an active region AA capable of displaying images and a peripheral region FR outside the active region AA. A plurality of pixels Pix are arranged in a matrix having a row-column configuration in the active region AA. In the present disclosure, a row refers to a pixel row including m pixels Pix arranged in one direction. In addition, a column refers to a pixel column including n pixels Pix arranged in a direction orthogonal to the direction in which the rows extend. The values of m and n are determined in accordance with a display resolution in the vertical direction and a display resolution in the horizontal direction. A plurality of scan lines GL are provided corresponding to the rows, and a plurality of signal lines SL are provided corresponding to the columns. As illustrated in FIG. 2, the light source 3 includes a plurality of light emitters 31. A light source controller (light source control circuit) 32 is provided on a wiring substrate 93. The wiring substrate 93 is a flexible printed circuit board or a printed circuit board (PCB) substrate. A light source control signal LCSA is transmitted from an image transmitter 91 of an external higher-level controller 9 to the light source controller 32. The light source control signal LCSA is a signal including information on light quantities of the light emitters 31 set according to, for example, input gradation values given to the pixels Pix.
As illustrated in FIG. 1, the drive circuit 4 is fixed to the surface of the array substrate 10. As illustrated in FIG. 2, the drive circuit 4 includes a signal processing circuit 41, a pixel control circuit 42, gate drive circuits 43, a source drive circuit 44, and a common potential drive circuit 45. The array substrate 10 has an area in the PX-PY plane larger than that of the counter substrate 20, and the drive circuit 4 is provided on a projecting portion of the array substrate 10 exposed from the counter substrate 20.
The signal processing circuit 41 receives a first input signal (such as a red-green-blue (RGB) signal) VS from the image transmitter 91 of the external higher-level controller 9 through a flexible printed circuit board 92.
The signal processing circuit 41 includes an input signal analyzer 411, a storage 412, and a signal adjuster 413. The input signal analyzer 411 generates a second input signal VCS based on the externally received first input signal VS.
The second input signal VCS is a signal for determining a gradation value to be given to each of the pixels Pix of the display panel 2 based on the first input signal VS. In other words, the second input signal VCS is a signal including gradation information on the gradation value of each of the pixels Pix.
The signal adjuster 413 generates a third input signal VCSA from the second input signal VCS. The signal adjuster 413 transmits the third input signal VCSA to the pixel control circuit 42.
The pixel control circuit 42 generates a horizontal drive signal HDS and a vertical drive signal VDS based on the third input signal VCSA. In the present embodiment, since the display device 1 is driven based on the field-sequential system, the horizontal drive signal HDS and the vertical drive signal VDS are generated for each color emittable by the light emitters 31.
The gate drive circuits 43 sequentially select the scan lines GL of the display panel 2 based on the horizontal drive signal HDS within one vertical scan period. The scan lines GL can be selected in any order. The gate drive circuits 43 are electrically coupled to the scan lines GL through first wiring lines GPL1 and second wiring lines GPL2 arranged in the peripheral region FR outside the active region AA (refer to FIG. 1).
The source drive circuit 44 supplies gradation signals corresponding to output gradation values of the pixels Pix to the signal lines SL of the display panel 2 based on the vertical drive signal VDS within one horizontal scan period.
In the present embodiment, the display panel 2 is an active matrix panel. Therefore, the display panel 2 includes the signal (source) lines SL extending in the second direction PY and the scan (gate) lines GL extending in the first direction PX in plan view, and includes switching elements Tr at intersecting portions between the signal lines SL and the scan lines GL.
A thin-film transistor is used as each of the switching elements Tr. A bottom-gate transistor or a top-gate transistor may be used as an example of the thin-film transistor. Although a single-gate thin film transistor is exemplified as the switching element Tr, the switching element Tr may be a double-gate transistor. One of the source electrode and the drain electrode of the switching element Tr is coupled to a corresponding one of the signal lines SL. The gate electrode of the switching element Tr is coupled to a corresponding one of the scan lines GL. The other of the source electrode and the drain electrode is coupled to one end of a capacitor of the polymer-dispersed liquid crystals LC to be described later. The capacitor of the polymer-dispersed liquid crystals LC is coupled at one end thereof to the switching element Tr through a pixel electrode PE, and coupled at the other end thereof to common potential wiring COML through a common electrode CE. Holding capacitance HC is generated between the pixel electrode PE and a holding capacitance electrode IO electrically coupled to the common potential wiring COML. A potential of the common potential wiring COML is supplied by the common potential drive circuit 45.
Each of the light emitters 31 includes a light emitter 33R of a first color (such as red), a light emitter 33G of a second color (such as green), and a light emitter 33B of a third color (such as blue). The light source controller 32 controls the light emitter 33R of the first color, the light emitter 33G of the second color, and the light emitter 33B of the third color so as to emit light in a time-division manner based on the light source control signal LCSA. In this manner, the light emitter 33R of the first color, the light emitter 33G of the second color, and the light emitter 33B of the third color are driven based on the field-sequential system.
As illustrated in FIG. 3, in a first sub-frame (first predetermined time) RF, the light emitter 33R of the first color emits light during a first color light emission period RON, and the pixels Pix selected during one vertical scan period GateScan scatter light to perform display. On the entire display panel 2, if the gradation signal corresponding to the output gradation value of each of the pixels Pix is supplied to the above-described signal lines SL for the pixels Pix selected during the one vertical scan period GateScan, only the first color is lit up during the first color light emission period RON.
Then, in a second sub-frame (second predetermined time) GF, the light emitter 33G of the second color emits light during a second color light emission period GON, and the pixels Pix selected during the one vertical scan period GateScan scatter light to perform display. On the entire display panel 2, if the gradation signal corresponding to the output gradation value of each of the pixels Pix is supplied to the above-described signal lines SL for the pixels Pix selected during the one vertical scan period GateScan, only the second color is lit up during the second color light emission period GON.
Further, in a third sub-frame (third predetermined time) BF, the light emitter 33B of the third color emits light during a third color light emission period BON, and the pixels Pix selected during the one vertical scan period GateScan scatter light to perform display. On the entire display panel 2, if the gradation signal corresponding to the output gradation value of each of the pixels Pix is supplied to the above-described signal lines SL for the pixels Pix selected during the one vertical scan period GateScan, only the third color is lit up during the third color light emission period BON.
Since a human eye has limited temporal resolving power and produces an afterimage, an image with a combination of three colors is recognized in a period of one frame (1F). The field-sequential system can eliminate the need for a color filter, and thus can reduce an absorption loss by the color filter. As a result, higher transmittance can be obtained. In the color filter system, one pixel is made up of sub-pixels obtained by dividing each of the pixels Pix into the sub-pixels of the first color, the second color, and the third color. In contrast, in the field-sequential system, the pixel need not be divided into the sub-pixels in such a manner. A fourth sub-frame may be further included to emit light in a fourth color different from any one of the first color, the second color, and the third color.
FIG. 4 is an explanatory diagram illustrating a relation between a voltage applied to the pixel electrode and a scattering state of the pixel. FIG. 5 is a sectional view illustrating an example of a section of the display device of FIG. 1. FIG. 6 is a plan view illustrating a planar surface of the display device of FIG. 1. FIG. 7 is an enlarged sectional view obtained by enlarging the liquid crystal layer portion of FIG. 5. FIG. 8 is a sectional view for explaining a non-scattering state in the liquid crystal layer. FIG. 9 is a sectional view for explaining the scattering state in the liquid crystal layer.
If the gradation signal corresponding to the output gradation value of each of the pixels Pix is supplied to the above-described signal lines SL for the pixels Pix selected during the one vertical scan period GateScan, a voltage applied to the pixel electrode PE changes with the gradation signal. The change in the voltage applied to the pixel electrode PE changes the voltage between the pixel electrode PE and the common electrode CE. The scattering state of the liquid crystal layer 50 for each of the pixels Pix is controlled in accordance with the voltage applied to the pixel electrode PE, and the scattering ratio in the pixels Pix changes, as illustrated in FIG. 4.
As illustrated in FIG. 4, the change in the scattering ratio in the pixel Pix is smaller when the voltage applied to the pixel electrode PE is equal to or higher than a saturation voltage Vsat. Therefore, the drive circuit 4 changes the voltage applied to the pixel electrode PE in accordance with the vertical drive signal VDS within a voltage range Vdr lower than the saturation voltage Vsat.
As illustrated in FIG. 5, the display device 1 includes a light-transmitting first base member 25, the display panel 2, and a light-transmitting second base member 27. A protective layer 75 is provided on one surface of the light-transmitting first base member 25. A protective layer 76 is provided on one surface of the second base member 27.
The display panel 2 includes the array substrate 10, the counter substrate 20, and the liquid crystal layer 50. The counter substrate 20 faces a surface of the array substrate 10 in a direction orthogonal thereto (in the direction PZ illustrated in FIG. 1). In the liquid crystal layer 50, the polymer-dispersed liquid crystals are sealed by the array substrate 10, the counter substrate 20, and the sealing portion 18.
As illustrated in FIGS. 5 and 6, the array substrate 10 has a first principal surface 10A, a second principal surface 10B, a first side surface 10C, a second side surface 10D, a third side surface 10E, and a fourth side surface 10F. The first principal surface 10A and the second principal surface 10B are parallel flat surfaces. The first side surface 10C and the second side surface 10D are parallel flat surfaces. The third side surface 10E and the fourth side surface 10F are parallel flat surfaces.
As illustrated in FIGS. 5 and 6, the counter substrate 20 has a first principal surface 20A, a second principal surface 20B, a first side surface 20C, a second side surface 20D, a third side surface 20E, and a fourth side surface 20F. The first principal surface 20A and the second principal surface 20B are parallel flat surfaces. The first side surface 20C and the second side surface 20D are parallel flat surfaces. The third side surface 20E and the fourth side surface 20F are parallel flat surfaces.
As illustrated in FIGS. 5 and 6, the first base member 25 has a first principal surface 25A, a second principal surface 25B, a first side surface 25C, a second side surface 25D, a third side surface 25E, and a fourth side surface 25F. The first principal surface 25A and the second principal surface 25B are parallel flat surfaces. The first side surface 25C and the second side surface 25D are parallel flat surfaces. The third side surface 25E and the fourth side surface 25F are parallel flat surfaces.
The first base member 25 is attached to the first principal surface 20A of the counter substrate 20 with an optical resin 23 interposed therebetween. The first base member 25 is a protective substrate for the counter substrate 20, and is formed, for example, of glass or a light-transmitting resin. When the first base member 25 is formed of a glass base material, it is also called a cover glass. When the first base member 25 is formed of a light-transmitting resin, it may be flexible. The same base member as the first base member 25 may be bonded to the first principal surface 10A of the array substrate 10 with an optical resin interposed therebetween.
As illustrated in FIGS. 5 and 6, the second base member 27 has a first principal surface 27A, a second principal surface 27B, a first side surface 27C, a second side surface 27D, a third side surface 27E, and a fourth side surface 27F. The first principal surface 27A and the second principal surface 27B are parallel flat surfaces. The first side surface 27C and the second side surface 27D are parallel flat surfaces. The third side surface 27E and the fourth side surface 27F are parallel flat surfaces.
The second base member 27 is bonded to the first principal surface 10A of the array substrate 10 with an optical resin 26 interposed therebetween. The second base member 27 is a protective substrate for the array substrate 10, and is formed of, for example, glass or a light-transmitting resin. When the second base member 27 is formed of a glass base material, it is also called a cover glass. When the second base member 27 is formed of a light-transmitting resin, it may be flexible.
As illustrated in FIGS. 5 and 6, the light source 3 includes a light guide 33L provided in the first direction PX along the second side surface 25D of the first base member 25 and the light emitters 31 arranged so as to face the light guide 33L. The light source 3 may also be called a side light source. The light guide 33L does not face the second side surface 20D of the counter substrate 20 of the light source 3, but faces only the second side surface 25D of the first base member 25. As illustrated in FIG. 5, the light source 3 emits light-source light L to the second side surface 25D of the first base member 25. The light guide 33L guides the light to only the second side surface 25D of the first base member 25 as a plane of light incidence from the light source 3. The plane of light incidence facing the light source 3 may be the second side surface 20D of the counter substrate 20 or the second side surface 27D of the second base member 27.
The light source 3 includes the light emitters 31 and the light guide 33L. Each of the light emitters 31 includes the light emitter 33R of the first color (such as red), the light emitter 33G of the second color (such as green), and the light emitter 33B of the third color (such as blue). The light guide 33L transmits the light emitted by the light emitter 33R of the first color, the light emitter 33G of the second color, and the light emitter 33B of the third color to the second side surface 25D of the first base member 25. The light guide 33L receives light simultaneously from the light emitters 31, internally diffuses the received light, and emits the diffused light to the display panel 2. As a result, the distribution per unit area of light irradiating the second side surface 20D of the counter substrate 20 and the second side surface 25D of the first base member 25 is made uniform.
The light guide 33L is a single light guide 33L formed integrally from the third side surface 25E to the fourth side surface 25F. The light guide 33L may be formed by arranging a plurality of divided light guides from the third side surface 25E to the fourth side surface 25F. The light guide 33L may be formed by arranging the divided light guides from the third side surface 25E to the fourth side surface 25F and connecting the adjacent light guides to each other.
The light emitters 31 and the light guide 33L are fixed together with an adhesive material or the like, and assembled to a support 33M to form a light source module. The support 33M is mounted so as to overlap the first principal surface 25A of the first base member 25 and is fixed to the first base member 25 with an adhesive material or the like.
The wiring substrate 93 (flexible printed circuit board or PCB substrate) is provided with an integrated circuit of the light source controller 32, and the light source controller 32 is coupled to the light source 3 through the wiring substrate 93 (flexible printed circuit board or PCB substrate).
As illustrated in FIG. 5, the light-source light L emitted from the light source 3 propagates in a direction (second direction PY) away from the second side surface 20D while being reflected by any of the first base member 25, the array substrate 10, the counter substrate 20, and the second base member 27.
As illustrated in FIG. 5, the light-source light L that has propagated in any of the first base member 25, the array substrate 10, the counter substrate 20, and the second base member 27 is scattered by the pixels Pix including the liquid crystals placed in the scattering state, and the angle of incidence of the scattered light becomes an angle smaller than the critical angle. Thus, emission light 68 and 68A is emitted outward from the first principal surface 20A of the counter substrate 20 (the first principal surface 25A of the first base member 25) and the first principal surface 10A of the array substrate 10, respectively. The emission light 68 and 68A emitted outward from the first principal surface 20A of the counter substrate 20 and the first principal surface 10A of the array substrate 10, respectively, is viewed by a viewer.
As illustrated in FIG. 6, the light emitters 31 are arranged at a predetermined pitch in a region that corresponds to the first direction PX of the active region AA. The light emitters 31 are not arranged outside a second region AAA corresponding to the first direction PX of the peripheral region FR.
The size of the first and the second base members 25 and 27 in the first direction PX is equal to the size from one end to the other end of the light emitters 31 arranged at the predetermined pitch in the first direction PX. Each of the first and the second base members 25 and 27 is sized so as to overlap the active region AA and not to overlap the peripheral region FR. The second base member 27 may be sized so as to overlap the peripheral region FR.
As illustrated in FIG. 6, the drive circuit 4 described above includes a plurality of integrated circuits of the gate drive circuits 43 and a plurality of integrated circuits of the source drive circuit 44.
The following describes the polymer-dispersed liquid crystals placed in the scattering state and the polymer-dispersed liquid crystals in the non-scattering state, using FIGS. 7 to 9.
As illustrated in FIG. 7, the array substrate 10 is provided with a first orientation film AL1. The counter substrate 20 is provided with a second orientation film AL2. When the orientation films are subjected to orientation treatment, for example, the orientation treatment is applied such that the orientation direction of the first orientation film AL1 is oriented toward one side of the first direction PX and the orientation direction of the second orientation film AL2 is oriented toward the other side of the first direction PX. The first and the second orientation films AL1 and AL2 may be, for example, vertical orientation films, or may be orientation films oriented in the first direction PX in which the light emitters 31 are arranged. The orientation treatment is applied by rubbing treatment or photo-orientation treatment.
The polymer-dispersed liquid crystals LC of the liquid crystal layer 50 illustrated in FIG. 7 are sealed between the array substrate 10 and the counter substrate 20. Then, in a state where the monomer and the liquid crystals are oriented by the first and the second orientation films AL1 and AL2, the monomer is polymerized by ultraviolet rays or heat to form a three-dimensional mesh-like polymer network 51. This process forms the liquid crystal layer 50 including the reverse-mode polymer-dispersed liquid crystals LC in which liquid crystal molecules 52 are dispersed in gaps of the three-dimensional mesh-like polymer network 51 formed in the mesh shape.
Thus, the polymer-dispersed liquid crystals LC include the three-dimensional mesh-like polymer network 51 and the liquid crystal molecules 52.
The orientation of the liquid crystal molecules 52 is controlled by a voltage difference between the pixel electrode PE and the common electrode CE. The voltage applied to the pixel electrode PE changes the orientation of the liquid crystal molecules 52. The degree of scattering of light passing through the pixels Pix changes with change in the orientation of the liquid crystal molecules 52.
For example, as illustrated in FIG. 8, the direction of an optical axis AX1 of the polymer network 51 is substantially equal to the direction of an optical axis AX2 of the liquid crystal molecules 52 when no voltage is applied between the pixel electrode PE and the common electrode CE. The optical axis AX2 of the liquid crystal molecules 52 is parallel to the first direction PX (FIG. 6) of the liquid crystal layer 50. The optical axis AX1 of the polymer network 51 is parallel to the first direction PX of the liquid crystal layer 50 regardless of whether a voltage is applied.
Ordinary-ray refractive indices of the polymer network 51 and the liquid crystal molecules 52 are equal to each other. When no voltage is applied between the pixel electrode PE and the common electrode CE, the refractive index difference between the polymer network 51 and the liquid crystal molecules 52 is substantially zero in all directions. The liquid crystal layer 50 is placed in the non-scattering state of not scattering the light-source light. The light-source light propagates in a direction away from the light source 3 (light emitters 31). When the liquid crystal layer 50 is in the non-scattering state of not scattering the light-source light, a background on the first principal surface 20A side of the counter substrate 20 is visible from the first principal surface 10A of the array substrate 10, and a background on the first principal surface 10A side of the array substrate 10 is visible from the first principal surface 20A of the counter substrate 20.
As illustrated in FIG. 9, in the gap between the pixel electrode PE and the common electrode CE having a voltage applied thereto, the optical axis AX2 of the liquid crystal molecules 52 is inclined by an electric field generated between the pixel electrode PE and the common electrode CE.
Since the optical axis AX1 of the polymer network 51 is not changed by the electric field, the direction of the optical axis AX1 of the polymer network 51 differs from the direction of the optical axis AX2 of the liquid crystal molecules 52. The light-source light is scattered in the pixel Pix including the pixel electrode PE having a voltage applied thereto. As described above, the viewer views a part of the scattered light-source light emitted outward from the first principal surface 10A of the array substrate 10 or the first principal surface 20A of the counter substrate 20.
In the pixel Pix including the pixel electrode PE having no voltage applied thereto, the background on the first principal surface 20A side of the counter substrate 20 is visible from the first principal surface 10A of the array substrate 10, and the background on the first principal surface 10A side of the array substrate 10 is visible from the first principal surface 20A of the counter substrate 20. In the display device 1 of the present embodiment, when the first input signal VS is received from the image transmitter 91, the voltage is applied to the pixel electrode PE of the pixel Pix for displaying an image, and an image based on the third input signal VCSA becomes visible together with the background. In this manner, the image is displayed in the display region when the polymer-dispersed liquid crystals LC are in the scattering state.
The light-source light is scattered in the pixel Pix including the pixel electrode PE having a voltage applied thereto, and emitted outward to display the image, which is displayed so as to be superimposed on the background. In other words, the display device 1 of the present embodiment can display the image so as to be superimposed on the background by combining the emission light 68 or 68A with the background.
A potential of each of the pixel electrodes PE (refer to FIG. 7) written during the one vertical scan period GateScan illustrated in FIG. 3 needs to be held during at least one of the first color light emission period RON, the second color light emission period GON, and the third color light emission period BON after each vertical scan period GateScan. If the written potential of each of the pixel electrodes PE (refer to FIG. 7) cannot be held during at least one of the first color light emission period RON, the second color light emission period GON, and the third color light emission period BON after each vertical scan period GateScan, what are called flickers, for example, are likely to occur. In other words, in order to shorten the one vertical scan period GateScan serving as a time for selecting the scan lines and increase the visibility in the driving based on what is called the field-sequential system, the written potential of each of the pixel electrodes PE (refer to FIG. 7) is required to be easily held during each of the first color light emission period RON, the second color light emission period GON, and the third color light emission period BON.
FIG. 10 is a plan view illustrating the scan lines, the signal lines, and the switching element in the pixel. FIG. 11 is a plan view illustrating a holding capacitance layer in the pixel. FIG. 12 is a plan view illustrating an auxiliary metal layer and an opening region in the pixel. FIG. 13 is a plan view illustrating the pixel electrode in the pixel. FIG. 14 is a plan view illustrating a light-blocking layer in the pixel. FIG. 15 is a sectional view along XV-XV′ of FIG. 14. FIG. 16 is a sectional view along XVI-XVI′ of FIG. 14. FIG. 17 is a sectional view along XVII-XVII′ of FIG. 14. As illustrated in FIGS. 1, 2, and 10, the array substrate 10 is provided with the signal lines SL and the scan lines GL so as to form a grid in plan view. In other words, one surface of the array substrate 10 is provided with the signal lines arranged in the first direction PX with gaps interposed therebetween and the scan lines arranged in the second direction PY with gaps interposed therebetween.
As illustrated in FIG. 10, a region surrounded by the adjacent scan lines GL and the adjacent signal lines SL corresponds to the pixel Pix. The pixel Pix is provided with the pixel electrode PE and the switching element Tr. In the present embodiment, the switching element Tr is a bottom-gate thin film transistor. The switching element Tr includes a semiconductor layer SC overlapping, in plan view, a gate electrode GE electrically coupled to a corresponding one of the scan lines GL.
As illustrated in FIG. 10, the scan lines GL are wiring of a metal such as molybdenum (Mo) or aluminum (Al), a multilayered body of these metals, or an alloy thereof. The signal lines SL are wiring of a metal such as aluminum or an alloy thereof.
As illustrated in FIG. 10, the semiconductor layer SC is provided so as not to extend out from the gate electrode GE in plan view. As a result, the light-source light L traveling toward the semiconductor layer SC from the gate electrode GE side is reflected, and light leakage is less likely to occur in the semiconductor layer SC.
As illustrated in FIG. 10, the light-source light L emitted from the light source 3 is incident in the second direction PY serving as a direction of incidence. The direction of incidence refers to a direction from the second side surface 20D closest to the light source 3 toward the first side surface 20C that is a surface opposite the second side surface 20D. When the direction of incidence of the light-source light L is the second direction PY, the length in the first direction PX of the semiconductor layer SC is smaller than the length in the second direction PY of the semiconductor layer SC. This configuration reduces the length in a direction intersecting the direction of incidence of the light-source light L, and thereby, reduces the effect of light leakage.
As illustrated in FIG. 10, two electrical conductors of a source electrode SE that are the same as the signal line SL extend from the signal line SL in the same layer as that of the signal line SL and in a direction intersecting the signal line SL. With this configuration, the source electrode SE electrically coupled to the signal line SL overlaps one end of the semiconductor layer SC in plan view.
As illustrated in FIG. 10, in plan view, a drain electrode DE is provided in a position between the adjacent electrical conductors of the source electrode SE. The drain electrode DE overlaps the semiconductor layer SC in plan view. A portion of the semiconductor layer SC overlapping neither the source electrode SE nor the drain electrode DE serves as a channel of the switching element Tr. As illustrated in FIG. 13, a contact electrode DEA electrically coupled to the drain electrode DE is electrically coupled to the pixel electrode PE through a contact hole CH.
As illustrated in FIG. 15, the array substrate 10 includes a first light-transmitting base member 19 formed of glass, for example. The first light-transmitting base member 19 may be made of a resin such as polyethylene terephthalate, as long as having a light transmitting capability.
As illustrated in FIG. 15, the scan line GL (refer to FIG. 10) and the gate electrode GE are provided on the first light-transmitting base member 19.
In addition, as illustrated in FIG. 15, a first insulating layer 11 is provided so as to cover the scan line GL and the gate electrode GE. The first insulating layer 11 is formed of, for example, a transparent inorganic insulating material such as silicon nitride.
The semiconductor layer SC is stacked on the first insulating layer 11. The semiconductor layer SC is formed of, for example, amorphous silicon, but may be formed of polysilicon or an oxide semiconductor. When viewed in the same section, a length Lsc of the semiconductor layer SC is smaller than a length Lge of the gate electrode GE overlapping the semiconductor layer SC. With this configuration, the gate electrode GE can block light Ld1 that has propagated in the first light-transmitting base member 19. As a result, the light leakage of the switching element Tr of the first embodiment is reduced.
The source electrode SE and the signal line SL covering a portion of the semiconductor layer SC and the drain electrode DE covering a portion of the semiconductor layer SC are provided on the first insulating layer 11. The drain electrode DE is formed of the same material as that of the signal line SL. A second insulating layer 12 is provided on the semiconductor layer SC, the signal line SL, and the drain electrode DE. The second insulating layer 12 is formed of, for example, a transparent inorganic insulating material such as silicon nitride, in the same manner as the first insulating layer 11.
A third insulating layer covering a portion of the second insulating layer 12 is formed on the second insulating layer 12. A third insulating layer 13 is formed of, for example, a light-transmitting organic insulating material such as an acrylic resin. The third insulating layer 13 has a larger film thickness than other insulating films formed of an inorganic material.
As illustrated in FIGS. 15, 16, and 17, some regions have the third insulating layer 13 while the other regions do not have the third insulating layer 13. As illustrated in FIGS. 16 and 17, the regions having the third insulating layer 13 are located over the scan lines GL and over the signal lines SL. The third insulating layer 13 has a grid shape that extends along the scanning lines GL and the signal lines SL and overlies (i.e., covers) the scan lines GL and the signal lines SL. As illustrated in FIG. 15, the regions having the third insulating layer 13 are also located over the semiconductor layer SC, that is, over the switching elements Tr. As a result, the switching element Tr, the scan line GL, and the signal line SL are located at relatively long distances from the holding capacitance electrode IO, and are thereby less affected by a common potential from the holding capacitance electrode IO. In addition, regions on the array substrate 10 not having the third insulating layer 13 are provided in the regions surrounded by the scan lines GL and the signal lines SL. Thus, regions are provided in which the thickness of the insulating layer is smaller than the thickness of the insulating layer overlapping the signal lines SL and the scan lines GL in plan view. The regions surrounded by the scan lines GL and the signal lines SL have relatively higher optical transmittance than the regions over the scan lines GL and over the signal lines SL, and thus, are improved in light transmitting capability.
As illustrated in FIG. 15, a metal layer TM is provided on the third insulating layer 13. The conductive metal layer TM is wiring of a metal such as molybdenum (Mo) or aluminum (Al), a multilayered body of these metals, or an alloy thereof. As illustrated in FIG. 12, the metal layer TM is provided in a region overlapping the signal lines SL, the scan lines GL, and the switching elements Tr in plan view. With this configuration, the metal layer TM is formed into a grid shape, and openings AP surrounded by the metal layer TM are formed.
As illustrated in FIG. 15, the holding capacitance electrode IO is provided above the third insulating layer 13 and the metal layer TM. The holding capacitance electrode IO is formed of a light-transmitting conductive material such as indium tin oxide (ITO). The holding capacitance electrode IO is also called “third light-transmitting electrode”. As illustrated in FIG. 11, the holding capacitance electrode IO has a region IOX including no light-transmitting conductive material in each of the regions surrounded by the scan lines GL and the signal lines SL. The holding capacitance electrode IO extends across the adjacent pixels Pix and is provided over the pixels Pix. A region of the holding capacitance electrode IO including the light-transmitting conductive material overlaps the scan line GL or the signal line SL, and extends to the adjacent pixel Pix.
The holding capacitance electrode IO has a grid shape that extends along the scanning lines GL and the signal lines SL and overlies (i.e., covers) the scan lines GL and the signal lines SL. With this configuration, the holding capacitance HC between the region IOX including no light-transmitting conductive material and the pixel electrode PE is reduced. Therefore, the holding capacitance HC is adjusted by the size of the region IOX including no light-transmitting conductive material.
As illustrated in FIG. 12, the switching element Tr coupled to the scan line GL and the signal line SL is provided. At least the switching element Tr is covered with the third insulating layer 13 serving as an organic insulating layer, and the metal layer TM having a larger area than that of the switching element Tr is located above the third insulating layer 13. This configuration can reduce the light leakage of the switching element Tr.
More specifically, the array substrate 10 includes the third insulating layer 13 serving as an organic insulating layer that covers at least the switching element Tr, and the metal layer TM that is provided on the upper side of the third insulating layer 13 so as to overlap the third insulating layer 13, and has a larger area than that of the switching element Tr. The region surrounded by the scan lines GL and the signal lines SL has a region having a smaller thickness than that of the third insulating layer 13 that overlaps the scan lines GL and the signal lines SL in plan view. As a result, a slant surface along which the thickness of the third insulating layer 13 changes is formed on a side of the third insulating layer 13 closer, in plan view, to the light source 3 than the switching element Tr is. As illustrated in FIG. 5, the light-source light L emitted from the light source 3 is incident in the second direction PY serving as a direction of incidence. As illustrated in FIG. 15, the slant surfaces described above include a first slant surface 13F on a side of the third insulating layer 13 on which light Lu of the light-source light L is incident, and a second slant surface 13R on a side opposite the side on which the light Lu is incident. As illustrated in FIG. 15, a metal layer TMt covers the first slant surface 13F on the side of the third insulating layer 13 on which the light Lu is incident. The metal layer TMt is a tapered portion that is formed of the same material as that of the metal layer TM, and is formed by extending the metal layer TM.
As illustrated in FIG. 15, the light Lu arrives in the direction of incidence. The light Lu is a part of the light-source light L that arrives from a side closer to the light source 3 than the switching element Tr is. The metal layer TMt blocks the light Lu, and thereby, reduces light leakage.
If the second slant surface 13R is covered with the metal layer TM and the background of the counter substrate 20 is viewed from the array substrate 10, light Ld2 viewed by the viewer is reflected by the metal layer TM covering the second slant surface 13R, and the reflected light may be viewed by the viewer. In the first embodiment, no metal layer TM covers the second slant surface 13R. As a result, the display device of the first embodiment reduces the reflected light that hinders the vision of the viewer.
The metal layer TM may be located on the upper side of the holding capacitance electrode IO, and only needs to be stacked with the holding capacitance electrode IO. The metal layer TM has a lower electrical resistance than that of the holding capacitance electrode IO. Therefore, the potential of the holding capacitance electrode IO is restrained from varying with the position where the pixel Pix is located in the active region AA.
As illustrated in FIG. 12, the width of the metal layer TM overlapping the signal line SL is larger than that of the signal line SL in plan view. This configuration restrains reflected light reflected by edges of the signal line SL from being emitted from the display panel 2. The width of the metal layer TM and the width of the signal line SL are lengths in a direction intersecting the extending direction of the signal line SL. The width of the metal layer TM overlapping the scan line GL is larger than the width of the scan line GL. The width of the metal layer TM and the width of the scan line GL are lengths in a direction intersecting the extending direction of the scan line GL.
As illustrated in FIG. 15, a fourth insulating layer 14 is provided on the upper side of the holding capacitance electrode IO and the metal layer TM. The fourth insulating layer 14 is an inorganic insulating layer formed of, for example, a transparent inorganic insulating material such as silicon nitride.
As illustrated in FIG. 15, the pixel electrode PE is provided on the fourth insulating layer 14. The pixel electrode PE is formed of a light-transmitting conductive material such as ITO. The pixel electrode PE is electrically coupled to the contact electrode DEA through the contact hole CH provided in the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12. As illustrated in FIG. 13, the pixel electrodes PE are partitioned on a per pixel Pix basis. The first orientation film AL1 is provided on the upper side of the pixel electrode PE.
As illustrated in FIG. 15, the counter substrate 20 includes a second light-transmitting base member 29 formed of glass, for example. The second light-transmitting base member 29 may be made of a resin such as polyethylene terephthalate, as long as having a light transmitting capability. The second light-transmitting base member 29 is provided with the common electrode CE. The common electrode CE is formed of a light-transmitting conductive material such as ITO. The second orientation film AL2 is provided on a surface of the common electrode CE. The counter substrate 20 includes a light-blocking layer LS between the second light-transmitting base member 29 and the common electrode CE. The light-blocking layer LS is formed of a resin or a metal material colored in black. A spacer PS is formed between the array substrate 10 and the counter substrate 20. The spacer PS is located between the common electrode CE and the second orientation film AL2.
As illustrated in FIGS. 12 and 16, in the display device of the first embodiment, a light-blocking layer GS located in the same layer as that of the scan line GL is provided in a position extending along the signal line SL and overlapping a portion of the signal line SL. The light-blocking layer GS is formed of the same material as that of the scan line GL. The light-blocking layer GS is not provided at a portion where the scan line GL intersects the signal line SL in plan view.
As illustrated in FIG. 12, the light-blocking layer GS is electrically coupled to the signal line SL through a contact hole CHG. With this configuration, the wiring resistance obtained by combining the light-blocking layer GS with the signal line SL is lower than that of only the signal line SL. As a result, the delay of the gradation signal supplied to the signal line SL is reduced. The contact hole CHG need not be provided, and the light-blocking layer GS need not be coupled to the signal line SL.
As illustrated in FIG. 16, the light-blocking layer GS is provided on an opposite side to the metal layer TM with the signal line SL therebetween. The width of the light-blocking layer GS is larger than that of the signal line SL and smaller than that of the metal layer TM. The width of the light-blocking layer GS, the width of the metal layer TM, and the width of the signal line SL are lengths in a direction intersecting the extending direction of the signal line SL. In this manner, the light-blocking layer GS has a larger width than that of the signal line SL, and thus, restrains the reflected light reflected by the edges of the signal line SL from being emitted from the display panel 2. As a result, the visibility of images is improved in the display device 1.
As illustrated in FIGS. 14 and 15, the counter substrate 20 is provided with the light-blocking layer LS. The light-blocking layer LS is provided in a region overlapping the signal lines SL, the scan lines GL, and the switching elements Tr in plan view.
As illustrated in FIGS. 14, 15, 16, and 17, the light-blocking layer LS has a larger width than that of the metal layer TM. This configuration restrains reflected light reflected by edges of the signal line SL, the scan line GL, and the metal layer TM from being emitted from the display panel 2. As a result, the visibility of images is improved in the display device 1.
The contact hole CH and the contact hole CHG are likely to diffusely reflect the light-source light L emitted thereto. Therefore, the light-blocking layer LS is provided in an area overlapping the contact holes CH and CHG in plan view.
As illustrated in FIG. 15, the spacer PS is disposed between the array substrate 10 and the counter substrate 20, and improves the uniformity of the distance between the array substrate 10 and the counter substrate 20.
FIG. 18 is a plan view for explaining the peripheral region of the first embodiment. The peripheral region FR illustrated in FIG. 1 has a first peripheral region FR1 and a second peripheral region FR2 that are illustrated in FIG. 18. The first peripheral region FR1 and the second peripheral region FR2 interpose the active region AA therebetween in the first direction PX.
If the first peripheral region FR1 does not include the first wiring lines GPL1 electrically coupling the gate drive circuit 43 to the scan lines GL, the transmittance of the first peripheral region FR1 can be increased, but the second peripheral region FR2 where the second wiring lines GPL2 are formed has lower transmittance than that of the first peripheral region FR1. If the transmittance of the first peripheral region FR1 greatly differs from that of the second peripheral region FR2, the viewer may feel discomfort. Therefore, the first wiring lines GPL1 are disposed in a first portion Q1 of the first peripheral region FR1, as illustrated in FIG. 18. The first wiring lines GPL1 are formed in the same layer and of the same material as the scan lines GL. Therefore, the transmittance of the first peripheral region FR1 is substantially equal to that of the second peripheral region FR2. Thus, the first wiring lines GPL1 are disposed in the first portion Q1 of the first peripheral region FR1. The plurality of second wiring lines GPL2 coupled to the scan lines GL are arranged in a second portion Q2 of the second peripheral region FR2.
The second wiring lines GPL2 of the second peripheral region FR2 are coupled to the gate drive circuit 43 on the third side surface 10E side, and the first wiring lines GPL1 of the first peripheral region FR1 are coupled to the gate drive circuit 43 on the fourth side surface 10F side. The wiring lines are coupled to the corresponding scan lines GL.
The shape occupied by the plurality of second wiring lines GPL2 in the second peripheral region FR2 is a shape obtained by inverting the shape occupied by the plurality of first wiring lines GPL1 in the first peripheral region FR1 into a mirror image. As a result, it is difficult for the viewer to notice a difference in contrast between the first peripheral region FR1 and the second peripheral region FR2.
If the first and the second peripheral regions FR1 and FR2 outside the active region AA do not transmit light, the background is not visible, possibly causing a sense of discomfort. A gap is provided between adjacent wire lines of the first wiring lines GPL1, thus, allowing light to be transmitted. A gap is provided between adjacent wire lines of the second wiring lines GPL2, thus, allowing light to be transmitted. With this configuration, the first and the second peripheral regions FR1 and FR2 also allow the background on the other side opposite to one side of the display device 1 to be viewed from the one side of the display device 1.
FIG. 19 is a plan view for explaining a display device of a first comparative example. FIG. 20 is a plan view for explaining a display device of a second comparative example. As illustrated in FIG. 19, in the display device of the first comparative example, the light emitters 31 are arranged at intervals of a first pitch P1 in the second region AAA corresponding to the second direction PY of the active region AA. The light emitters 31 are not arranged in a portion overlapping a first region FRA corresponding to the second direction PY of the peripheral region FR. The second side surface 25D of the first base member 25 is irradiated with the light emitted by the light emitters 31 in the second region AAA, but not irradiated with the light emitted by the light emitters 31 in the first region FRA. Therefore, when the viewer views the display panel 2 at an angle with respect to the normal direction of the display panel 2, an unintended shadow BP starting from the first region FRA corresponding to the peripheral region FR outside the active region AA may be viewed.
In contrast, in the display device of the first embodiment, although the light emitters 31 are not arranged in the first regions FRA that overlap areas obtained by extending, in the second direction PY, the peripheral regions FR located on both sides in the first region PX of the active region AA, the size in the first direction PX of the first base member 25 is equal to the size in the first direction PX of the active region AA. With this configuration, the light from the light emitters 31 enters the second side surface 25D of the first base member 25 from the first regions FRA through the light guide 33L. Therefore, the shadow BP is difficult to occur even when the viewer views the display panel 2 at an angle with respect to the normal direction of the display panel 2.
As illustrated in FIG. 20, in the display device of the second comparative example, the light emitters 31 are arranged in portions overlapping the first and the second peripheral regions FR1 and FR2. As a result, the light-source light L from the light emitters 31 enters the first and the second peripheral regions FR1 and FR2. The first wiring lines GPL1 disposed in the first peripheral region FR1 and the second wiring lines GPL2 disposed in the second peripheral region FR2 reflect the light-source light L, and the reflected light brightens the first and the second peripheral regions FR1 and FR2, which may degrade the display quality.
In contrast, in the display device of the first embodiment, the first and the second base members 25 and 27 have sizes that overlap the active region AA and do not overlap the first and the second peripheral regions FR1 and FR2. Since the second side surface 25D of the first base member 25 corresponding to the first and the second peripheral regions FR1 and FR2 is not present, the light of the light emitters 31 does not enter the first base member 25 overlapping the first and the second peripheral regions FR1 and FR2.
This configuration can restrain the light from the light emitters 31 from entering the peripheral regions FR that include the first wiring lines GPL1 of the first peripheral region FR1 and the second wiring lines GPL2 of the second peripheral region FR2. Furthermore, the occurrence of the unintended shadows can be reduced in the first and the second peripheral regions FR1 and FR2.
First Modification of First Embodiment
FIG. 21 is a sectional view illustrating an exemplary section of a display device according to a first modification of the first embodiment of the present disclosure. FIG. 22 is a plan view illustrating a planar surface of the display device of FIG. 21. The same components as those described in the present embodiment above are denoted by the same reference numerals, and the description thereof will not be repeated.
As illustrated in FIGS. 21 and 22, the light source 3 includes the light guide 33L provided in the first direction PX along the second side surface 25D of the first base member 25 and the second side surface 20D of the counter substrate 20, and the light emitters 31 arranged so as to face the light guide 33L. The light guide 33L faces the second side surface 20D of the counter substrate 20 and the second side surface 25D of the first base member 25. As illustrated in FIG. 21, the light source 3 emits the light-source light L to the second side surface 20D of the counter substrate 20. The second side surface 20D of the counter substrate 20 facing the light source 3 serves as a plane of light incidence. The second side surface 25D of the first base member 25 facing the light source 3 also serves as a plane of light incidence.
As illustrated in FIGS. 21 and 22, unlike in the first embodiment, in the first modification, the light guide 33L faces the second side surface 20D of the counter substrate 20 and the second side surface 25D of the first base member 25.
The light guide 33L transmits the light emitted by the light emitter 33R of the first color, the light emitter 33G of the second color, and the light emitter 33B of the third color to the second side surface 20D of the counter substrate 20 and the second side surface 25D of the first base member 25. The light guide 33L receives the light simultaneously from the light emitters 31, internally diffuses the received light, and emits the diffused light to the display panel 2. As a result, the distribution per unit area of light irradiating the second side surface 20D of the counter substrate 20 and the second side surface 25D of the first base member 25 is made uniform.
The light guide 33L is a single light guide 33L formed integrally from the third side surface 20E (or the third side surface 25E) to the fourth side surface 20F (or the fourth side surface 25F). The light guide 33L may be formed by arranging a plurality of divided light guides from the third side surface 20E (or the third side surface 25E) to the fourth side surface 20F (or the fourth side surface 25F). The light guide 33L may be formed by arranging a plurality of divided light guides from the third side surface 20E (or the third side surface 25E) to the fourth side surface 20F (or the fourth side surface 25F) and connecting the adjacent light guides to each other.
As illustrated in FIG. 21, the light-source light L emitted from the light source 3 propagates in a direction (second direction PY) away from the second side surface 20D while being reflected by the first base member 25, the first principal surface 10A of the array substrate 10, and the first principal surface 20A of the counter substrate 20 or the first base member 25. When the light-source light L travels outward from the first principal surface 10A of the array substrate 10 or the first principal surface 20A of the counter substrate 20, the light-source light L passes from a medium having a higher refractive index to a medium having a lower refractive index. Hence, if the angle of incidence of the light-source light L incident on the first principal surface 10A of the array substrate 10 or the first principal surface 20A of the counter substrate 20 is larger than a critical angle, the light-source light L is totally reflected by the first principal surface 10A of the array substrate 10 or the first principal surface 20A of the counter substrate 20.
As illustrated in FIG. 21, the light-source light L that has propagated in the array substrate 10 and the counter substrate 20 is scattered by the pixels Pix including the liquid crystals placed in the scattering state, and the angle of incidence of the scattered light becomes an angle smaller than the critical angle. Thus, the emission light 68 and 68A are emitted outward from the first principal surface 20A of the counter substrate 20 (the first principal surface 25A of the first base member 25) and the first principal surface 10A of the array substrate 10, respectively. The emission light 68 and 68A emitted outward from the first principal surface 20A of the counter substrate 20 and the first principal surface 10A of the array substrate 10, respectively, is viewed by a viewer.
As illustrated in FIG. 22, the light emitters 31 are arranged at a predetermined pitch in a region that corresponds to the first direction PX of the active region AA. The light emitters 31 are not arranged in the first region FRA corresponding to the first direction PX of the peripheral region FR.
The size of the first and the second base members 25 and 27 in the first direction PX is equal to the size from one end to the other end of the light emitters 31 arranged at the predetermined pitch in the first direction PX. Each of the first and the second base members 25 and 27 is sized so as to overlap the active region AA and not to overlap the peripheral region FR.
That is, the first base member 25 and the second base member 27 are not located in the peripheral region FR provided with the first wiring lines GPL1 and the second wiring lines GPL2. The light emitters 31 are not arranged in the first region FRA.
This configuration can restrain the light from the light emitters 31 from entering the peripheral region FR provided with the first wiring lines GPL1 of the first peripheral region FR1 and the second wiring lines GPL2. Furthermore, the occurrence of the unintended shadow starting from the first region FRA can be reduced.
FIG. 23 is a plan view illustrating a planar surface of a display device different from that of the first modification. The same components as those described in the present embodiment above are denoted by the same reference numerals, and the description thereof will not be repeated.
As illustrated in FIG. 23, the second base member 27 is disposed and sized so as to overlap the active region AA and the peripheral region FR in the first direction PX.
As a result, since the second base member 27 overlaps the counter substrate 20, the strength of the display panel 2 in the third direction Dz is increased, making the display panel 2 difficult to crack.
While the preferred embodiment has been described above, the present disclosure is not limited to such an embodiment. The content disclosed in the embodiments is merely an example, and can be variously modified within the scope not departing from the gist of the present disclosure. Any modifications appropriately made within the scope not departing from the gist of the present disclosure also naturally belong to the technical scope of the present disclosure.
Patent Application
20240255803
