Patent Application
20100231493
The present invention relates to a display device. More particularly, the present invention relates to an active matrix driving display device in which a storage capacitor is formed in a pixel.
An active matrix liquid crystal display device including TFTs (thin film transistors) as a switching element is known now. This liquid crystal display device includes a liquid crystal display panel including a liquid crystal layer interposed between two insulating substrates facing each other. On one of the two substrates, gate lines (scanning signal lines) and source lines (image signal lines) are arranged in a lattice pattern, and pixel electrodes for drawing an image are arranged in a matrix pattern. Near an intersection of the gate line and the source line, a TFT is arranged to control application of a voltage into the pixel electrode. On the other substrate, a common electrode for applying a voltage between itself and the pixel electrode is arranged. A liquid crystal capacitor is formed by the pixel electrode and the common electrode.
According to such a liquid crystal display device, the gate lines are selected one by one every horizontal scanning period. So application of a scanning signal to the gate line is repeated with a period of one vertical scanning. Therefore, charges accumulated in each liquid crystal capacitor formed by the pixel electrode and the common electrode need to be stored during almost one vertical scanning period. If the accumulated charges are not stored only by the liquid crystal capacitor, a storage capacitor is also formed along the liquid crystal capacitor. The storage capacitor is generally formed by a pixel electrode or a storage capacitor electrode electrically connected to a pixel electrode, and a storage capacitor wiring.
In a field of display devices such as a liquid crystal display device, pixels are more and more finely formed along with improvement in resolution and downsizing, and a need for a technique of increasing an aperture ratio of a pixel is now growing. As a technique of increasing an aperture ratio, FIGS. 29 and 30 in Patent Document 1 discloses the following technique: with respect to a transparent dielectric layer that gives a difference in thickness of the liquid crystal layer between a reflective region and a transmissive region so that the thickness in the reflective region is smaller than that in the transmissive region, a transparent dielectric layer is formed in continuity over pixel regions adjacent in row and/or column directions.
Thus, while the increase in aperture ratio of the pixel is requested, the aperture ratio is decreased if a large storage capacitor is tried to be secured, generally. For this problem, Patent Document 2 discloses, as a technology of forming a storage capacitor without decreasing the aperture ratio, a technology of forming a storage capacitor by: an electrode wiring that is arranged between pixels in adjacent two rows; and an extended portion of a gate insulating film of a transistor and an extended portion of a semiconductor thin film of the transistor.
Japanese Kokai Publication No. 2005-189351
Japanese Kokai Publication No. Hei-02-176725
However, Patent Document 2 discloses a configuration in which source lines, the number of which is twice that of columns of pixels, are arranged, and gate lines, the number of which is half that of rows of pixels, are arranged. In such a configuration, for an aperture ratio, rather than advantages due to the decrease in the number of gate lines, disadvantages due to the increase in the number of source lines are created. In such a point, this configuration has room for improvement. In addition, the source lines are arranged close to each other, which easily causes a short-circuit therebetween.
The present invention has been made in view of the above-mentioned state of the art. The present invention has an object to provide a display device capable of improving display qualities.
The present inventors made various investigations on a way of improving display qualities of a high-definition display device, and noted arrangement of a storage capacitor wiring in the display device. Then, the inventors found the followings.
If in a configuration where n-source lines and m-gate lines are arranged in a lattice pattern, a configuration of a pixel in an odd-numbered row and a configuration of a pixel in an even-numbered row are in an inverse relationship, with respect to a boundary line between these pixels, these pixels can be configured to share a storage capacitor wiring. As a result, an effect of increasing an aperture ratio, attributed to a decrease in the number of storage capacitor wirings, and an effect of decreasing electric resistance, attributed to an increase in line width of respective storage capacitor wirings, can be sufficiently exhibited. As a result, the above-mentioned problems have been admirably solved, leading to completion of the present invention.
That is, the present invention is a display device including:
pixels arrayed in a matrix pattern in n-rows and m-columns (n and m being each an integer of 2 or more);
n-source lines; and
m-gate lines,
the n-source lines and the m-gate lines being arranged in a lattice pattern,
wherein a configuration of a pixel in an odd-numbered row of the n-rows and a configuration of a pixel in an even-numbered row of the n-rows are in an inverse relationship,
the display device further includes a storage capacitor wiring shared between the pixel in the odd-numbered row and the pixel in the even-numbered row,
the storage capacitor wiring is arranged in a boundary region between the pixel in the odd-numbered row and the pixel in the even-numbered row, and
the storage capacitor wiring faces a storage capacitor electrode for the pixel in the odd-numbered row and a storage capacitor electrode for the pixel in the even-numbered row, each with an insulating film therebetween. The pixels arrayed in a matrix pattern may be pixels arranged in a delta pattern as long as they are arranged in row and column directions. The wirings (lines) may not be necessarily perpendicular to each other as long as the wirings are almost arranged in a lattice pattern in the whole region where the wirings are arranged.
The above-mentioned shared storage capacitor wiring is arranged to face a storage capacitor electrode for the pixel in an odd-numbered row with an insulating film therebetween to form a storage capacitor for the pixel in the odd-numbered row. Further, the above-mentioned shared storage capacitor wiring is arranged to face a storage capacitor electrode for the pixel in an even-numbered row with an insulating film therebetween to form a storage capacitor for the pixel in the even-numbered row. In other words, the above-mentioned shared storage capacitor wiring is shared between the pixel in the odd-numbered row and the pixel in the even-numbered row, and one storage capacitor wiring forms storage capacitors for the pixels in two rows. The storage capacitor wirings, which are conventionally arranged one for pixels in each row, are arranged one for the pixels in every two rows. Thus, the above-mentioned shared storage capacitor wiring is generally arranged in every other boundary region that is positioned in parallel, between the pixel in the odd-numbered row and the pixel in the even-numbered row. As a result, according to the present invention, the area of the region where the storage capacitor wiring is arranged is decreased, which leads to an increase in aperture ratio. Instead of or in addition to the decrease in such an area, the line width of the respective storage capacitor wiring is increased, and thereby electric resistance can be reduced, which leads to suppression of cross-talk, for example. In addition, the storage capacitor wiring is formed in a simplified pattern, which improves yield. In the present invention, at least one of the storage capacitor wiring and the storage capacitor electrode is preferably made of a light-shielding conductive material such as metal.
As a preferable embodiment of the present invention, an embodiment in which the storage capacitor electrode for the pixel in the odd-numbered row and the storage capacitor electrode for the pixel in the even-numbered row are aligned in series along an extending direction of the storage capacitor wiring is mentioned. According to this embodiment, the storage capacitor electrode for the pixel in the odd-numbered row and that for the pixel in the even-numbered row can be arranged to overlap with the storage capacitor wiring without increasing the line width of the storage capacitor wiring. Accordingly, this embodiment is preferably employed when an aperture ratio is increased by decreasing the area of the region where the storage capacitor wiring is arranged. The storage capacitor electrode may be arranged in a layer upper or lower than the storage capacitor wiring.
As another preferable embodiment of the present invention, an embodiment in which the display device includes a thin film transistor including a semiconductor layer in each pixel,
the semiconductor layer has a portion overlapping with any one of the m-gate lines,
the semiconductor layer for the pixel in the odd-numbered row and the semiconductor layer for the pixel in the even-numbered row are integrally formed and connected to any one of the n-source lines through a shared contact hole is mentioned. This embodiment can be adopted in a configuration where n-source lines are arranged for pixels in n-rows, and the pixels in the odd-numbered rows and the pixels in the even-numbered rows are connected to the same source line. According to this embodiment, the semiconductor layer for the pixel in the odd-numbered row and the semiconductor layer for the pixel in the even-numbered row are integrally formed, and thereby these semiconductor layers can be connected to the source line through the shared contact hole. Thus, the pixels in the odd-numbered and even-numbered rows share the same contact hole, and thereby the number of the contact holes can be decreased. The aperture ratio can be further increased in the present invention.
Examples of a preferable embodiment of the above-mentioned shared contact hole include an embodiment in which the shared contact hole is arranged in a boundary region between the pixel in the odd-numbered row and the pixel in the even-numbered row, where the storage capacitor wiring is not arranged. In the present invention, the storage capacitor wiring, which is conventionally arranged for the pixels in each row, can be arranged for the pixels in every two rows. As a result, a region between the pixel in the odd-numbered row and the pixel in the even-numbered row, where no storage capacitor wiring is arranged, can be utilized. The above-mentioned shared contact hole is arranged in this region, which can increase the aperture ratio compared with a case where a contact hole is arranged in another region of each pixel.
The above-mentioned shared contact hole may be one or two or more for one semiconductor layer. One contact hole conventionally needs to be arranged in each pixel, but if one contact hole is formed for one semiconductor layer, the number of the contact holes can be decreased by half because the semiconductor layer is integrally formed over the pixels in the odd-numbered and even-numbered rows. As a result, the aperture ratio can be increased. If two or more contact holes are formed for one semiconductor layer, the reduction in aperture ratio can be suppressed, and further connection reliability can be improved with efficiency, compared with the case where two or more contact holes that are connected to the semiconductor layer individually formed in each pixel are formed.
As another preferable embodiment of the display device of the present invention, an embodiment in which the display device includes an additional circuit shared between the pixel in the odd-numbered row and the pixel in the even-numbered row, and
the additional circuit being arranged in a boundary region between the pixel in the odd-numbered row and the pixel in the even-numbered row, where the storage capacitor wiring is not arranged is mentioned. In the present invention, the storage capacitor wiring, which is conventionally arranged for pixels in each row, can be arranged for pixels in every two rows. As a result, the region where the storage capacitor wiring is not arranged between the pixel in the odd-numbered row and the pixel in the even-numbered row can be utilized. The above-mentioned shared additional circuit is arranged in this region, and thereby the aperture ratio can be increased compared with a case where an additional circuit is individually formed in another region in each pixel. Examples of the above-mentioned additional circuit include a photo sensor circuit and a memory circuit.
Examples of a preferable embodiment of the display device of the present invention include and embodiment in which the display device includes a reflective region and a transmissive region in each pixel,
the configuration of the pixel in the odd-numbered row of the n-rows and the configuration of the pixel in the even-numbered row of the n-rows are in an inverse relationship,
the reflective region of the pixel in the odd-numbered row is adjacent to the reflective region of the pixel in the even-numbered row, and
the display device includes a projection formed over adjacent reflective regions of the pixels in the odd-numbered row and in the even-numbered row. If the display device of the present invention is a liquid crystal display device, the above-mentioned projection may be arranged to overlap with the reflective electrode on a substrate where a reflective electrode is arranged, or may be arranged to face the reflective electrode on a substrate that faces a substrate where a reflective electrode is arranged with a liquid crystal layer therebetween. A spacer is typically arranged on a projection that is arranged in a reflective region of a pixel. In such a case, a region where the spacer is arranged is secured, and a margin for misarrangement of the spacer needs to be secured. So it is difficult to downsize the projection, but in this embodiment, the projection can be enlarged without changing the area of the region where the projection is arranged in the pixel, compared with the case where the projection is individually formed in each pixel. As a result, problems that are generated when the projection is formed can be solved, and the area of the reflective region of the pixel can be more decreased, which allows the aperture ratio of the transmissive region to be increased.
If the projection is made of a photosensitive resin by photolithography, for example, the projection is formed to have an inclined side surface, which is a production technique problem. The region on the substrate where this inclined side surface is positioned possible becomes an ineffective region where a desired display is not provided. In the above-mentioned embodiment in which the projection is integrally formed, the area of the ineffective region can be decreased compared with the case where the projection is individually formed in every pixel.
In the present invention, the storage capacitor wiring, which is conventionally arranged for the pixels in the every row, can be arranged for the pixels in every two rows. As a result, the region where the storage capacitor wiring is not arranged between the pixel in the odd-numbered row and the pixel in the even-numbered row can be utilized. Accordingly, it is preferable that the above-mentioned integrated projection is arranged in this region. The above-mentioned projection is arranged in a semi-transmissive liquid crystal display device, generally, in order to decrease the thickness of the liquid crystal layer in the reflective region to uniform the optical path length of the liquid crystal layer between the reflective and transmissive regions.
According to the display device of the present invention, the area of the region where the storage capacitor wiring is arranged is decreased, which results in an increase in aperture ratio. Instead of or in addition to the decrease in such an area, the line width of the respective storage capacitor wirings is increased, and thereby the electric resistance can be reduced, which leads to suppression of cross talk and the like. In addition, the pattern of the storage capacitor wiring is simplified, leading to an improvement in yield.
The present invention is mentioned in more detail below with reference to Embodiments, but not limited thereto. For example, the following Embodiments relate to a liquid crystal display device, but the display device of the present invention is not limited thereto.
A liquid crystal display device includes a liquid crystal display panel having a liquid crystal layer between a pair of substrates. Such a device provides display by applying a voltage to the liquid crystal layer from electrodes arranged on the substrates, thereby changing alignment of liquid crystal molecules. According to the present Embodiment, driving of pixels is controlled on an active matrix substrate where TFTs (thin film transistors) and pixel electrodes are arranged in respective pixels in a matrix pattern.
As shown in
According to the present Embodiment, as shown in
The active matrix substrate in accordance with the present Embodiment has a structure in which the TFT semiconductor layer 12, the gate insulating film 13, the gate line 14, a first interlayer insulating film 15, the source line 16, a second interlayer insulating film 17, the pixel electrode 18, and an alignment film 19 are arranged one above the other in this order from a substrate 11 side, as shown in
In the present Embodiment, the pixel electrode 18 is formed to have a square shape, and for convenience of explanation, a region where the pixel electrode 18 is arranged in the substrate plane is referred to as a pixel, the direction of the long side of the region is defined as a longitudinal direction, and the direction of the short side of the region is referred to as a transverse direction. The gate line 14 extends in the transverse direction so that it bisects the pixel, and the source line 16 extends in the longitudinal direction between the pixels. The gate line 14 and the source line 16 are perpendicular to each other. The gate line 14 has a branched portion 14a near an intersection to the source line 16. The branched portion 14a also overlaps with the TFT semiconductor layer 12 with the gate insulating film 13 therebetween. Thus, the gate line 14 and the TFT semiconductor layer 12 overlap with each other in each pixel at two positions, including the branched portion 14a. Thus, a dual gate structure is formed.
In
According to the present Embodiment, as shown in
According to the present Embodiment, the storage capacitor electrode 22a for the pixel in the odd-numbered row and the storage capacitor electrode 22b for the pixel in the even-numbered row are aligned in parallel to each other along the extending direction of the storage capacitor wiring 24. The electrodes 22a and 22b may be aligned in series along the extending direction of the storage capacitor wiring 24 when the line width of the wiring 24 is decreased or when the electrodes 22a and 22b are positioned on the long side of the pixel electrodes 18. As shown in
In the present Embodiment, the first contact holes 31 that penetrate the first interlayer insulating film 15 and the gate insulating film 13 and that electrically connects the source line 16 and the TFT semiconductor layer 12 are arranged one for each TFT semiconductor layer 12. As shown in one example in
The present Embodiment relates to an embodiment where a storage capacitor wiring is arranged in a boundary region between pixels in an odd-numbered row (Nth row) and pixels in an even-numbered row (N+1th row), and an additional circuit is arranged between the pixels in the even-numbered row (N+1th row) and pixels in the next even-numbered row (N+2th row).
In the present Embodiment, in a boundary region between the pixels, where no storage capacitor wiring is arranged, a part of an optical sensor circuit is formed as the additional circuit. As shown in
The operation principle of the photo sensor circuit in accordance with the present Embodiment is mentioned below with reference to
By changing a potential of RSI (N+1, N+2) from −10V to 0V, a forward bias potential is applied to the photodiode 41, and the node 44 is reset at 0V. After the reset, the potential of RSI (N+1, N+2) is changed back to −10V.
If an amount of light radiated to the photodiode 41 arranged for the pixel in the (N+1)th row is large, the resistance of the photodiode 41 is significantly decreased, and the potential of the node 44 becomes close to the potential −10V of RSI (N+1, N+2). If the amount is small, the resistance of the photodiode 41 for the pixel in the (N+1)th row is not so decreased, and the potential of the node 44 does not so change from 0V. Thus, among the photodiodes 41 arrayed in a matrix pattern, the resistance of the photodiode 41 that is positioned in a bright region is significantly decreased, and the potential of the node 44 connected to the corresponding photodiode 41 becomes close to the potential of the corresponding RSI. In contrast, the resistance of the photodiode 41 that is positioned in a dark region is not so decreased, and the potential of the node 44 connected to the corresponding photodiode 41 does not so change.
By changing a potential of RWI (N+1, N+2) from 0V to 10V, the potential of the node 44 connected to RWI (N+1, N+2) through the capacitor is increased by about 10V. The node 44 is connected to the gate electrode of the readout TFT 42, and so a potential in accordance with that of the node 44 is applied from SL (M+1) to SL (M). That is, when the potential of SL (M) in floating state is increased to a potential corresponding to a value obtained by subtracting the threshold voltage Vth (=1V) of the readout TFT 42 from the potential of the node 44, the readout TIT 42 becomes in an off-state. In this readout, SL (M+1) functions as a readout reference potential line of the photo sensor, and SL (M) functions as a readout line of the photo sensor.
According to the photo sensor circuit of the present Embodiment, the above-mentioned (1) to (3) are periodically repeated. The photo sensor circuit is provided in the display device of the present invention, which enables the device to have a touch panel function, and the like.
In the present Embodiment, storage capacitor wirings, which are conventionally arranged one for pixels in one row, are arranged one for pixels in two rows, and this can create a space. Within this space, an additional space is arranged, which can suppress a reduction in aperture ratio.
The present Embodiment relates to a semi-transmissive liquid crystal display device.
According to the present Embodiment, the projection 51 is arranged in the counter substrate, and it may be arranged in the active matrix substrate. In a color filter-on-array liquid crystal display device, for example, a color filter is arranged in an active matrix substrate including TFTs, wirings, and the like. In such a case, the projection may be arranged in the active matrix substrate.
The present Embodiment shows a case where pixels are arrayed in a delta-pattern.
According to the present Embodiment, the red, green, and blue pixels in the Nth row are out of alignment with those in N+1th row by 1.5 pixels. For example, a boundary line between the green pixel and the blue pixel in the Nth row is positioned at an extension of the center line of the red pixel in the N+1th row. Similarly, the red, green, and blue pixels in the N+1th row are out of alignment with those in the N+2th row by 1.5 pixels.
The red, green, and blue pixels in the Nth row are aligned with those in the N+2th row, respectively. Thus, also when the pixels are arrayed in a delta-pattern, as shown in
The liquid crystal display device of the present invention is not limited to the above-mentioned Embodiments 1 to 4, and various changes and modifications can be made within the scope and spirit of the present invention. For example, the storage capacitor electrode in Embodiments 1 to 4 is positioned in a layer lower than the storage capacitor wiring, but may be positioned in a layer upper than the storage capacitor wiring. In this case, the storage capacitor electrode may be integrally formed with the pixel electrode. That is, an opening is provided with an interlayer insulating film in a region where the storage capacitor electrode is to be formed, and a conductive film is formed over the entire substrate, and as a result, the pixel electrode on the interlayer insulating film and the storage capacitor electrode below the opening of the interlayer insulating film can be integrally formed from the conductive film.
With regard to display mode, the pixel electrodes and the common electrodes may be arranged in different substrates, like in TN (twisted nematic) mode, VA (vertical alignment) mode, and the like, or these electrodes may be arranged in the same substrate, like in IPS (in-plane switching) mode.
In Embodiment 3, the semi-transmissive liquid crystal display device is described, but the liquid crystal display devices of Embodiments 1, 2, and 4 may be a transmissive, reflective, or semi-transmissive liquid crystal display device.
The present application claims priority to Patent Application No. 2007-252180 filed in Japan on Sep. 27, 2007 under the Paris Convention and provisions of national law in a designated State, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-252180 | Sep 2007 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2008/058660 | 5/9/2008 | WO | 00 | 3/19/2010 |
