Patent Application
20240145484
This application claims the benefit of priority to Japanese Patent Application No. 2022-171597, filed on Oct. 26, 2022, the entire contents of which are incorporated herein by reference.
An embodiment of the present invention relates to a display device. In particular, an embodiment of the present invention relates to a display device in which a transistor including an oxide semiconductor is used. In addition, an embodiment of the present invention relates to an array substrate of a display device.
Recently, a transistor using an oxide semiconductor as a channel has been developed instead of amorphous silicon, low-temperature polysilicon, and single-crystal silicon (for example, Japanese laid-open patent publication No. 2014-146819 and Japanese laid-open patent publication No. 2015-159315). Similar to a transistor in which amorphous silicon is used as a channel, a transistor in which an oxide semiconductor is used as a channel is formed with a simple structure and a low-temperature process. The transistor using the oxide semiconductor as the channel is known to have higher mobility and very lower off-state current than the transistor using amorphous silicon as the channel.
For example, an IPS type liquid crystal display device is known as a display device (Japanese laid-open patent publication No. 2015-087600). A source electrode of a transistor is connected to a pixel electrode via an opening arranged in an organic passivation film and an interlayer insulating film.
A display device according to an embodiment of the present invention includes a plurality of pixels arranged in a matrix on a substrate along a first direction and a second direction intersecting the first direction, each of the plurality of pixels including a transistor, a first wiring arranged over the transistor and electrically connected to the transistor, a first transparent conductive layer arranged over the first wiring and electrically connected to the transistor, a first insulating layer arranged on the first transparent conductive layer, and having a contact hole, and a second transparent conductive layer arranged on the first insulating layer and electrically connected to the first transparent conductive layer via the contact hole, wherein the first insulating layer has a recess portion overlapping the first transparent conductive layer, the recess portion is continuous with the contact hole, and the contact hole is arranged at a bottom part of the recess portion.
A display device according to an embodiment of the present invention includes a plurality of pixels arranged in a matrix on a substrate along a first direction and a second direction intersecting the first direction, each of the plurality of pixels including a transistor, a first wiring arranged over the transistor and electrically connected to the transistor, a first transparent conductive layer arranged over the first wiring and electrically connected to the transistor, a first insulating layer arranged on the first transparent conductive layer, and having a contact hole, and a second transparent conductive layer arranged on the first insulating layer and electrically connected to the first transparent conductive layer via the contact hole, wherein the first insulating layer has a recess portion extending over a plurality of pixels arranged side-by-side in the second direction, the recess portion is arranged continuously with the contact hole, and the contact hole is arranged at a bottom part of the recess portion overlapping the first transparent conductive layer.
A display device according to an embodiment of the present invention includes a substrate, a pixel arranged on the substrate, and having a transistor, a pixel electrode, and a common electrode, a wiring connected to a first electrode of the transistor, a conductive layer connected to a second electrode of the transistor, an insulating layer arranged over the conductive layer, and having a contact hole, wherein the pixel electrode is connected to the conductive layer via the contact hole, the contact hole includes a first region having a first side surface and a second region having a second side surface located between the first region and the conductive layer, a bottom part of the first region is continuous with a top of the second region, a tangent line of the first side surface at a bottom of the first region makes a first angle with a main surface of the substrate, a tangent line of the second side surface at a bottom of the second region makes a second angle with the main surface of the substrate, the first angle is less than the second angle, and a portion of the insulating layer is located between the wiring and the common electrode.
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following invention is merely an example. A configuration that can be easily conceived by a person skilled in the art by appropriately changing the configuration of the embodiment while keeping the gist of the invention is naturally included in the scope of the present invention. In order to make the description clearer, the drawings may schematically show the widths, thicknesses, shapes, and the like of the respective parts in comparison with the actual embodiments. However, the illustrated shapes are merely examples, and do not limit the interpretation of the present invention. In the present specification and the drawings, the same components as those described above with respect to the above-described drawings are denoted by the same reference signs, and a detailed description thereof may be omitted as appropriate.
In the embodiments of the present invention, a direction from a substrate toward an oxide semiconductor layer is referred to as upper or above. Conversely, a direction from an oxide semiconductor layer to a substrate is referred to as lower or below. In this way, for convenience of explanation, although the phrases “above” or “below” are used in the description, for example, the upper and lower relationship between the substrate and the oxide semiconductor layer may be arranged in a different direction from that shown in the drawings. In the following explanation, for example, the expression “oxide semiconductor layer on substrate” merely describes the upper and lower relationship between the substrate and the oxide semiconductor layer as described above, and another member may be arranged between the substrate and the oxide semiconductor layer. The phrases “above” or “below” means a stacking order of a structure in which a plurality of layers is stacked, and may be a positional relationship in which a transistor and a pixel electrode do not overlap in a plan view when expressed as a pixel electrode above the transistor. On the other hand, when expressed as a pixel electrode vertically above the transistor, it means the positional relationship in which the transistor and the pixel electrode overlap in a plan view.
A “display device” refers to a structure that displays an image using an electro-optic layer. For example, the term display device may refer to a display panel including the electro-optic layer, or may refer to a structure with other optical members (for example, a polarized member, a backlight, a touch panel, and the like) attached to a display cell. The “electro-optic layer” may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer and an electrophoretic layer, unless there is a technical inconsistency. Therefore, although embodiments described later will be described by exemplifying a liquid crystal display device including a liquid crystal layer as a display device, the configuration in the present embodiment can be applied to a display device including the other electro-optic layers described above.
In this specification, the expression “α includes A, B, or C,” “α includes any of A, B, and C,” “α includes one selected from a group consisting of A, B, and C,” and the like does not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.
In addition, the following embodiments can be combined with each other as long as there is no technical inconsistency.
An outline of a display device 10 according to an embodiment of the present invention will be described with reference to
In addition, the display device 10 includes a backlight unit on the back of the array substrate 300, and when emitted light from the backlight unit is transmitted through the image display region 23, the transmitted light is modulated in each pixel PIX, so that an image is displayed.
A seal region 24 arranged with the seal part 400 is a region around the liquid crystal region 22. The FPC 600 is attached to a terminal region 26. The terminal region 26 is arranged in a region where the array substrate 300 does not overlap the counter substrate 500 and is arranged outside the seal region 24. In addition, the outside of the seal region 24 means the outside of the region arranged with the seal part 400 and the region surrounded by the seal part 400. The IC chip 700 is arranged on the FPC 600. The IC chip 700 supplies a signal for driving a pixel circuit of each pixel PIX. In the following explanation, the seal region 24, the outside of the seal region 24, and the terminal region 26 may be collectively referred to as a frame region. The IC chip 700 may be mounted on the frame region.
A source wiring 321 extends from the source driver circuit SD in the direction D2 and is connected to pixel circuits of the plurality of pixels PIX arranged in the direction D2. A gate wiring 331 extends from the gate driver circuit GD-1 or the gate driver circuit GD-2 in the direction D1 and is connected to pixel circuits of the plurality of pixels PIX arranged in the direction D1.
A terminal part 333 is arranged in the terminal region 26. The terminal part 333 and the source driver circuit SD are connected by a connecting wiring 341. Similarly, the terminal part 333 and the gate driver circuits GD-1 and GD-2 are connected by the connecting wiring 341. When the FPC 600 is connected to the terminal part 333, an external device to which the FPC 600 is connected is connected to a display device 20, and pixel circuits included in each pixel PIX arranged in the display device 10 are driven by a signal from the external device.
Detailed configurations of the display device 10 according to an embodiment of the present invention will be described with reference to
As shown in
The transistor Tr1 (the transistor 800) has an oxide semiconductor layer OS, a gate insulating layer GI1, and a gate electrode GL1 (the first gate electrode 810). The gate electrode GL1 faces the oxide semiconductor layer OS. In addition, part of the gate wiring 331 functions as the gate electrode GL1. The gate insulating layer GI1 is arranged between the oxide semiconductor layer OS and the gate electrode GL1. In the present embodiment, although a top-gate transistor in which the oxide semiconductor layer OS is arranged closer to the substrate SUB than the gate electrode GL1 is exemplified, a bottom-gate transistor in which the positional relationship between the gate electrode GL1 and the oxide semiconductor layer OS is reversed may be used.
The oxide semiconductor layer OS includes oxide semiconductor regions OS1 and OS2. The oxide semiconductor region OS1 is an oxide semiconductor layer in a region overlapping the gate electrode GL1 in a plan view. The oxide semiconductor region OS1 functions as a semiconductor and is switched between a conductive state and a non-conductive state depending on a voltage supplied to the gate electrode GL1. That is, the oxide semiconductor region OS1 functions as a channel of the transistor Tr1. The oxide semiconductor region OS2 functions as a conductor.
An insulating layer IL2 is arranged above the gate electrode GL1. A wiring W1 (the source wiring 321) is arranged above the insulating layer IL2. The wiring W1 is connected to the oxide semiconductor region OS2 via a contact hole WCON arranged in the insulating layer IL2 and the gate insulating layer G11. A data signal related to the grayscale of the pixels is transmitted to the wiring W1. An insulating layer IL3 is arranged above the insulating layer IL2 and the wiring W1. The connecting electrode ZTCO (the drain electrode 840) is arranged above the insulating layer IL3. The connecting electrode ZTCO is connected to the oxide semiconductor region OS2 via a contact hole ZCON arranged in the insulating layers IL3 and IL2 and the gate insulating layer G11. The connecting electrode ZTCO is in contact with the oxide semiconductor region OS2 at a bottom part of the contact hole ZCON. The connecting electrode ZTCO is a transparent conductive layer.
A region where the connecting electrode ZTCO (also referred to as a first transparent conductive layer) is in contact with the oxide semiconductor region OS2 is referred to as a first contact region CON1. Although details will be described later, the connecting electrode ZTCO contacts the oxide semiconductor region OS2 in the first contact region CON1 that does not overlap the gate electrode GL1 and the wiring W1 in a plan view. In a plan view, the first contact region CON1 is included in the display region of the pixel.
For example, in the case where an ITO layer or other transparent conductive layer is formed so as to be in contact with a semiconductor layer such as a silicon layer, a surface of the semiconductor layer is oxidized by process gases and oxygen ions at the time of ITO deposition. Since the oxide layer formed on the surface of the semiconductor layer has a high resistance, the contacting resistance between the semiconductor layer and the transparent conductive layer increases. As a result, defects occur in the electrical contact between the semiconductor layer and the transparent electrode layer. On the other hand, even if the transparent conductive layer is formed to be in contact with the oxide semiconductor layer, the high resistance oxide layer as described above is not formed on the oxide semiconductor layer. Therefore, no defects occur in the electric contact between the oxide semiconductor layer and the transparent conductive layer.
An insulating layer IL4 is arranged above the connecting electrode ZTCO. The insulating layer IL4 relieves a step formed by a structure arranged below the insulating layer IL4. The insulating layer IL4 may be referred to as a planarization film. The pixel electrode PTCO (also referred to as a second transparent conductive layer) is arranged above the insulating layer IL4.
The pixel electrode PTCO is connected to the connecting electrode ZTCO via a contact hole PCON arranged in the insulating layer IL4. A region where the connecting electrode ZTCO and the pixel electrode PTCO are in contact is referred to as a contact region CON2. In a plan view, the contact region CON2 overlaps the gate electrode GL1. The pixel electrode PTCO is the transparent conductive layer.
As shown in
An insulating layer IL5 is arranged above the pixel electrode PTCO and the insulating layer IL4. The insulating layer IL5 is also arranged on a side surface of the contact hole PCON and above the pixel electrode PTCO inside the contact hole PCON. A filling member FM is arranged above the insulating layer IL5 so as to fill the inside of the contact hole PCON. In a region where the filling member FM is arranged, the filling member FM has a projecting portion protruding above a top surface of the pixel electrode PTCO arranged above the insulating layer IL4. The projecting portion functions as a spacer SP. In addition, a part of the filling member FM that substantially coincides with the top surface of the pixel electrode PTCO or a top surface of the insulating layer IL5 arranged above the insulating layer IL4 is also referred to as a filling part FP.
The spacer SP is arranged for some of the pixels. For example, the spacer SP may be arranged for any one of the red pixel, the green pixel, and the blue pixel. However, the spacer SP may be arranged for all the pixels. A height of the spacer SP is half the height of a cell gap. A spacer is also arranged in the counter substrate, and the spacer of the counter substrate and the spacer SP overlap in a plan view. In addition, a configuration in which the height of the spacer SP corresponds to the cell gap can also be applied. A detailed configuration of the spacer SP will be described later in detail.
As shown in
A light-shielding layer LS is arranged between the transistor Tr1 and the substrate SUB. In the present embodiment, the light-shielding layers LS1 and LS2 are arranged as the light-shielding layer LS. However, the light-shielding layer LS may be formed of the light-shielding layer LS1 only or LS2 only. In a plan view, the light-shielding layer LS is arranged in a region where the gate electrode GL1 and the oxide semiconductor layer OS overlap. In other words, in a plan view, the light-shielding layer LS is arranged in a region overlapping the oxide semiconductor region OS1. The light-shielding layer LS suppresses the light entering from the substrate SUB side from reaching the oxide semiconductor region OS1. In the case where a conductive layer is used as the light-shielding layer LS, a voltage may be applied to the light-shielding layer LS to control the oxide semiconductor region OS1. In the case where the voltage is applied to the light-shielding layer LS, the light-shielding layer LS and the gate electrode GL1 may be connected in the frame region. In a plan view, the first contact region CON1 is arranged in a region not overlapping the light-shielding layer LS. In addition, in a plan view, the second contact region CON2 and the recess portion REC are arranged in a region overlapping the light-shielding layer LS.
The transistor Tr2 has a p-type transistor Tr2-1 and an n-type transistor Tr2-2.
Both the p-type transistor Tr2-1 and the n-type transistor Tr2-2 have a gate electrode GL2, a gate insulating layer GI2, and a semiconductor layer S. The gate electrode GL2 faces the semiconductor layer S. The gate insulating layer GI2 is arranged between the semiconductor layer S and the gate electrode GL2. In the present embodiment, although a bottom-gate transistor in which the gate electrode GL2 is arranged closer to the substrate SUB than the semiconductor layer S is exemplified, a top-gate transistor in which the positional relationship between the gate electrode GL2 and the semiconductor layer S is reversed may be used.
The semiconductor layer S of the p-type transistor Tr2-1 includes semiconductor regions S1 and S2. The semiconductor layer S of the n-type transistor Tr2-2 includes the semiconductor regions S1, S2, and S3. The semiconductor region S1 is a semiconductor region in the region overlapping the gate electrode GL2 in a plan view. The semiconductor region S1 functions as a channel of the transistor Tr2-1. The semiconductor region S2 functions as a conductor. The semiconductor region S3 functions as a conductor having higher resistance than the semiconductor region S2. The semiconductor region S3 suppresses hot carrier degradation by attenuating hot carriers entering the semiconductor region S1.
An insulating layer IL1 and the gate insulating layer GI1 are arranged above the semiconductor layer S. In the transistor Tr2, the gate insulating layer GI1 simply functions as an interlayer film. A wiring W2 is arranged above these insulating layers. The wiring W2 is connected to the semiconductor layer S via an opening arranged in the insulating layer IL1 and the gate insulating layer G11. The insulating layer IL2 is arranged above the wiring W2. The wiring W1 is arranged above the insulating layer IL2. The wiring W1 is connected to the wiring W2 via an opening (also referred to as a contact hole) arranged in the insulating layer IL2.
The gate electrode GL2 and the light-shielding layer LS2 are the same layer. The wiring W2 and the gate electrode GL1 are the same layer. The same layer means that a plurality of members is formed by patterning one layer.
The influence of parasitic capacitance formed by the wiring W1, the pixel electrode PTCO, and the common electrode CTCO will be described with reference to
In order to reduce the parasitic capacitance formed between the wiring W1 and the common electrode CTCO, a distance between the wiring W1 and the common electrode CTCO may be increased. In this case, the insulating layer IL4 may be made thicker. However, when the thickness of the insulating layer IL4 is increased, a hole diameter (a hole diameter on the top surface of the insulating layer IL4) of the contact hole PCON tends to increase. Due to this effect, as shown in
In order to reduce the parasitic capacitance between the wiring W1 and the pixel electrode PTCO, the distance between the wiring W1 and the pixel electrode PTCO may be increased. In this case, the hole diameter of the contact hole PCON may be reduced, but in order to reduce the hole diameter of the contact hole PCON, the thickness of the insulating layer IL4 needs to be reduced. The hole diameter of the contact hole PCON can be reduced, and the angle of the sidewall of the contact hole PCON can be reduced. On the other hand, since the thickness of the insulating layer IL4 is small, as shown in
As described above, in order to improve the definition of the pixel, there is a limitation in the form of the contact hole for connecting the connecting electrode ZTCO and the pixel electrode PTCO.
As described above, in order to achieve high definition of a pixel, it is required to suppress the formation of a parasitic capacitance caused by the contact hole connecting the connecting electrode ZTCO and the pixel electrode PTCO.
In the display device 20 according to an embodiment of the present invention, the hole diameter of the contact hole PCON can be reduced and the angle of the sidewall of the contact hole PCON can be increased without unnecessarily reducing the thickness of the insulating layer IL4. This suppresses an increase in power consumption of the display device 20. In addition, the occurrence of crosstalk in the display device 20 is suppressed.
As shown in
As shown in
As shown in
The insulating layer IL4 is formed using an organic insulating material. As shown in
In the display device according to the present embodiment, arranging the contact hole PCON at the bottom part of the recess portion REC arranged in the insulating layer IL4 makes it possible to reduce the hole diameter of the contact hole PCON without unnecessarily reducing the thickness T1 of the insulating layer IL4. In addition, the angle of the side wall of the contact hole PCON can be increased. As a result, it is possible to suppress the distance L1 between the wiring W1 and the pixel electrode PTCO covering the side wall of the contact hole PCON from being reduced in the direction D1. As a result, it is possible to suppress the formation of the parasitic capacitance by the wiring W1 and the pixel electrode PTCO on the side surface of the contact hole PCON. Therefore, even when the pixel is driven at high speed, it is possible to suppress an increase in the load between the wiring W1 and the pixel electrode PTCO. Therefore, the power consumption of the display device can be reduced.
In addition, since the thickness T1 of the insulating layer IL4 can be sufficiently increased, it is possible to suppress the distance L2 between the wiring W1 and the common electrode CTCO from being reduced. As a result, it is possible to suppress the formation of the parasitic capacitance by the wiring W1 and the common electrode CTCO. Therefore, even when the pixel is driven at high speed, capacitive coupling caused by the parasitic capacitance can suppress the fluctuation in the potential of the pixel electrode PTCO due to the potential of the wiring W1. Therefore, it is possible to suppress the occurrence of crosstalk in the display device.
A plane layout of the pixels of the display device 10 will be described with reference to
As shown in
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A configuration of the spacer SP arranged in the array substrate will be described with reference to
As shown in
As shown in
Next, a method for manufacturing the display device 10 according to an embodiment of the present invention will be described with reference to
Next, the insulating layer IL4 is exposed using a mask 310. The mask 310 has an opening 320 having an area larger than the hole diameter of the contact region CON2 to be formed later. When the insulating layer IL4 is irradiated with light via the opening 320 of the mask 310, the insulating layer IL4 having an area corresponding to the opening 320 is exposed. In this case, the intensity of the exposure is constant, and the insulating layer IL4 is exposed for several 100 seconds of exposure time (referred to as integrated exposure). A depth to which the insulating layer IL4 is exposed from the surface is controlled by the exposure time. In the present embodiment, the thickness T2 of 25% or more and 30% or less from the surface of the insulating layer IL4 is exposed with respect to the thickness T1 of the insulating layer IL4. The region where the insulating layer IL4 is exposed is shown as a region 410.
As described above, the recess portion REC and the contact hole PCON can be formed in the insulating layer IL4. In the case where the exposure is performed on the insulating layer IL4 only by the mask 310 having the wide opening 320, the opening of the contact hole PCON becomes large, and consequently, the display quality of the display device is degraded. In addition, in the case where the exposure is performed on the insulating layer IL4 only by the mask 330 having the narrow opening 340, it is difficult to sufficiently expose the insulating layer IL4 because the thickness T1 of the insulating layer IL4 is large. In the present embodiment, first, the first exposure step is performed on the insulating layer IL4 using the mask 310 having the wide opening 320, and then the second exposure step is performed on the insulating layer IL4 using the mask 330 having the narrow opening 340. Therefore, since the effective thickness of the insulating layer IL4 in the second exposure can be reduced, the hole diameter of the contact hole PCON can be further reduced.
The present embodiment is described with reference to
In the present embodiment, the insulating layer IL4 has the recess portion REC extending over the plurality of pixels arranged side by side in the direction D1. In addition, the contact hole PCON is arranged in the region overlapping the connecting electrode ZTCO at the bottom part of the recess portion REC.
The recess portion REC extends along the gate electrode GL1. In addition, the recess portion REC extends along the light-shielding layer LS. In the present embodiment, the recess portion REC may be referred to as a groove because it extends in the direction D1. A length (width) of the recess portion REC in the direction D2 is, for example, 5.0 μm or more and 8.0 μm or less. A width of the recess portion REC may be any width that is hidden by the light-shielding layer LS. In the first embodiment, the minimum dimension between the recess portions REC in adjacent pixels may be restricted by the resolution of the exposure machine. In the present embodiment, forming the recess portion REC so as to extend over the plurality of pixels makes it possible to eliminate the restriction on the resolution of the exposure machine.
As shown in
As shown in
As shown in
The arrangement of the spacer SP in the display device 10 in the present embodiment is the same as that in the first embodiment except for the shape of the recess portion REC. That is, it is similar to the layout of the display device 10 shown in
In the display device according to the present embodiment as well, arranging the contact hole PCON for each pixel at the bottom part of the recess portion REC extending in the direction D1 arranged in the insulating layer IL4 makes it possible to reduce the hole diameter of the contact hole PCON without unnecessarily reducing the thickness T1. In addition, the angle of the side wall of the contact hole PCON can be increased. As a result, it is possible to suppress the distance L1 between the wiring W1 and the pixel electrode PTCO covering the side wall of the contact hole PCON from being reduced in the direction D1. As a result, it is possible to suppress the formation of the parasitic capacitance by the wiring W1 and the pixel electrode PTCO on the side surface of the contact hole PCON. Therefore, even when the pixel is driven at high speed, it is possible to suppress an increase in the load between the wiring W1 and the pixel electrode PTCO. Therefore, the power consumption of the display device can be reduced.
In addition, since the thickness T1 of the insulating layer IL4 can be sufficiently increased, it is possible to suppress the distance L2 between the wiring W1 and the common electrode CTCO from being reduced. As a result, it is possible to suppress the formation of the parasitic capacitance by the wiring W1 and the common electrode CTCO. Therefore, even when the pixel is driven at high speed, capacitive coupling caused by the parasitic capacitance can suppress the fluctuation in the potential of the pixel electrode PTCO due to the potential of the wiring W1. Therefore, it is possible to suppress the occurrence of crosstalk in the display device.
A rigid substrate having light transmittance and having no flexibility, such as a glass substrate, a quartz substrate, or a sapphire substrate, can be used as the substrate SUB. On the other hand, in the case where the substrate SUB needs to have flexibility, a flexible substrate containing a resin and having flexibility, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, can be used as the substrate SUB. In order to improve the heat resistance of the substrate SUB, impurities may be introduced into the resin.
Metal materials can be used as the gate electrodes GL1 and GL2, the wirings W1 and W2, the light-shielding layer LS, and the common auxiliary electrode CMTL. For example, aluminum (A1), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), or silver (Ag), or an alloy or compound thereof is used as the metal material. The above-described metal material may be used in a single layer or in a stacked layer as a member of the electrode or the like.
For example, a stacked structure of Ti layer, A1 layer, and Ti layer is used as the gate electrode GL1. In the present embodiment, the cross-sectional shape of a pattern end of the gate electrode GL1 having the stacked structure is a forward tapered shape.
Common insulating materials can be used as the gate insulating layers GI1 and GI2 and the insulating layers IL1 to IL5. For example, inorganic insulating layers, such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), or aluminum nitride (AlNx), can be used as the insulating layers IL1 to IL3, and IL5. An insulating layer with few defects can be used as these insulating layers. An organic insulating material such as a polyimide resin, an acryl resin, an epoxy resin, a silicone resin, a fluororesin, or a siloxane resin can be used as the insulating layer IL4. The above-described organic insulating materials may be used as the gate insulating layers GI1 and GI2 and the insulating layers IL1 to IL3, and IL5. The above-described insulating material may be used in a single layer or in a stacked layer as the member of the insulating layer or the like.
The above-described SiOxNy and AlOxNy are a silicon compound and an aluminum compound containing a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiNxOy and AlNxOy are a silicon compound and an aluminum compound containing a smaller proportion (x>y) of oxygen than nitrogen.
An example of the insulating layer includes SiOx with a thickness of 100 nm used as the gate insulating layer G11. A stacked structure of SiOx, SiNx, and SiOx with a total thickness of 600 nm to 700 nm is used as the insulating layer IL1. A stacked structure of SiOx and SiNx with a total thickness of 60 nm to 100 nm is used as the gate insulating layer GI2. A stacked structure of SiOx, SiNx, and SiOx with a total thickness of 300 nm to 500 nm is used as the insulating layer IL2. SiOx (single layer), SiNx (single layer), or a stack thereof with a total thickness of 200 nm to 500 nm is used as the insulating layer IL3. An organic insulating material with the thickness T1 of 2.0 μm to 4.0 μm is used as the insulating layer IL4. SiNx (single layer) with a thickness of 50 nm to 150 nm is used as the insulating layer IL5.
An organic insulating material, such as a polyimide resin, an acryl resin, an epoxy resin, a silicone resin, a fluororesin, or a siloxane resin, is used as the filling member FM.
An oxide semiconductor having semiconductor characteristics can be used as the oxide semiconductor layer OS. The oxide semiconductor layer OS has light transmittance. For example, an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor layer OS. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) may be used as the oxide semiconductor layer OS. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:0=1:1:1:4 may be used. However, the compositions of the oxide semiconductor layer OS used in the present embodiment are not limited to the above, and an oxide semiconductor having a composition other than those described above can also be used. For example, the ratio of In may be larger than the above described ratio in order to improve the mobility. In addition, the ratio of Ga may be larger than the above described ratio in order to increase the bandgap and reduce the effect of light irradiation. The oxide semiconductor layer OS may be amorphous or polycrystalline. The oxide semiconductor layer OS may be a mixed phase of amorphous and crystalline.
In addition, the ratio of indium to the entire oxide semiconductor layer OS may be 50% or more as the oxide semiconductor layer OS. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanoids are used as the oxide semiconductor layer OS. Elements other than those described above may be used as the oxide semiconductor layer OS. In the case where the ratio of indium relative to the total of the oxide semiconductor layer OS is 50% or more, the oxide semiconductor layer OS has a polycrystalline structure.
A transparent conductive layer is used as the connecting electrode ZTCO, the pixel electrode PTCO, and the common electrode CTCO. A mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO) can be used as the transparent conductive layer. A material other than the above may be used as the transparent conductive layer.
Each of the embodiments described above as an embodiment of the present invention can be appropriately combined and implemented as long as no contradiction is caused. Further, the addition, deletion, or design change of components, or the addition, deletion, or condition change of process as appropriate by those skilled in the art based on the display device of each embodiment are also included in the scope of the present invention as long as they are provided with the gist of the present invention.
Further, it is understood that, even if the effect is different from those provided by each of the above-described embodiments, the effect obvious from the description in the specification or easily predicted by persons ordinarily skilled in the art is apparently derived from the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-171597 | Oct 2022 | JP | national |
