Patent Application
20250155753
This application claims the priority of Korean Patent Application No. 10-2023-0158281 filed on Nov. 15, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
The present disclosure relates to a display device, and more particularly, to a display device capable of measuring a cell gap in a bezel area.
Recently, with the increase in interest in information displays and the increasing demand for portable information media, research and commercialization have been focused on lightweight, thin-film flat panel displays (FPD). Among the flat panel displays, a liquid crystal display (LCD) displays images by using optical anisotropy of liquid crystals.
The liquid crystal display broadly includes a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.
An object to be achieved by the present disclosure is to provide a display device capable of measuring and monitoring a cell gap in a bezel area by sensing a capacitance.
Objects of the present disclosure are not limited to the above-mentioned objects, and other objects, which are not mentioned above, may be clearly understood by those skilled in the art from the following descriptions.
A display device according to an aspect of the present disclosure may include a first substrate including a display area and a non-display area; a first liquid crystal layer disposed on the display area and the non-display area of the first substrate; a first sealant bordering the first liquid crystal layer; a second liquid crystal layer bordering the first sealant; a second sealant bordering the second liquid crystal layer; and a capacitor formed based on a first electrode and a second electrode at opposite ends of the second liquid crystal layer for detecting stress applied to the display panel.
According to an aspect of the present disclosure, a display device is disclosed. The display device includes a first substrate including a display area and a non-display area; a second substrate attached to the first substrate including a first sealant; a first liquid crystal layer disposed inside a region formed by the first sealant; a second sealant disposed outside a region formed by the first sealant; a second liquid crystal layer disposed between the first sealant and the second sealant; a first electrode disposed on the first substrate in the non-display area; and a second electrode disposed on the second substrate in the non-display area and forming a capacitance with the first electrode.
Other detailed matters of the exemplary embodiments are included in the detailed description and the drawings.
According to the present disclosure, the sealants are formed in the bezel area of the display panel, and the capacitance sensing structure implemented by the upper and lower electrodes is formed in the sealants, such that the cell gap in the bezel area may be measured and monitored. As a result, it is possible to electrically monitor, in real time, the change in capacitance during the module assembly process and immediately address any detected defect. In addition, it is possible to improve reliability by suppressing an image defect, such as a yellow mura or a bright spot, caused by an external force applied to a display panel.
The effects according to the present disclosure are not limited to the contents exemplified above, and more various effects are included in the present specification.
The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
Advantages and characteristics of the present disclosure and a method of achieving the advantages and characteristics will be clear by referring to exemplary embodiments described below in detail together with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein but will be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art may fully understand the disclosures of the present disclosure and the scope of the present disclosure.
The shapes, sizes, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally denote like elements throughout the specification. Further, in the following description of the present disclosure, a detailed explanation of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. The terms such as “including,” “having,” and “consist of” used herein are generally intended to allow other components to be added unless the terms are used with the term “only”. Any references to singular may include plural unless expressly stated otherwise.
Components are interpreted to include an ordinary error range even if not expressly stated.
When the position relation between two parts is described using the terms such as “on”, “above”, “below”, and “next”, one or more parts may be positioned between the two parts unless the terms are used with the term “immediately” or “directly”.
When an element or layer is disposed “on” another element or layer, another layer or another element may be interposed directly on the other element or therebetween.
Although the terms “first”, “second”, and the like are used for describing various components, these components are not confined by these terms. These terms are merely used for distinguishing one component from the other components. Therefore, a first component to be mentioned below may be a second component in a technical concept of the present disclosure.
Like reference numerals generally denote like elements throughout the specification.
A size and a thickness of each component illustrated in the drawing are illustrated for convenience of description, and the present disclosure is not limited to the size and the thickness of the component illustrated.
The features of various embodiments of the present disclosure may be partially or entirely adhered to or combined with each other and may be interlocked and operated in technically various ways, and the embodiments may be carried out independently of or in association with each other.
Hereinafter, an exemplary aspect of the present disclosure will be described in detail with reference to the drawings.
With reference to
The color filter substrate 105 may include a color filter C including a plurality of sub-color filters 107 configured to implement red (R), green (G), and blue (B) colors, a black matrix 106 configured to separate the sub-color filters 107 and block light passing through the liquid crystal layer 130, and a common electrode 108 configured to apply voltages to the liquid crystal layer 130.
The array substrate 110 may include a plurality of gate lines 116 and a plurality of data lines 117 arranged in longitudinal and transverse directions and configured to define a plurality of sub-pixels P, thin-film transistors (TFTs) T formed in intersection areas between the gate lines 116 and the data lines 117, and pixel electrodes 118 formed on the sub-pixels P.
The color filter substrate 105 and the array substrate 110, which are configured as described above, are attached to be opposite to each other by a sealant (not illustrated) that is formed at an outer periphery of an image display area to form a display panel. The color filter substrate 105 and the array substrate 110 may be attached by alignment keys (not illustrated) that are formed on the color filter substrate 105 or the array substrate 110.
Meanwhile, for convenience of description, an example will be described in which a twisted nematic (TN) method of operating nematic liquid crystal molecules in a direction perpendicular to the substrate is used as a method of operating the liquid crystal display device. However, the present disclosure is not limited thereto. The present disclosure may be applied to an in-plane switching (IPS) type liquid crystal display device that increases a viewing angle to 170 degrees or more by operating liquid crystal molecules in a direction parallel to the substrate.
An example will be described in which the display device in
In the fringe field switching type liquid crystal display device, the pixel electrode is formed at a lower side, and the common electrode is formed at an upper side when the liquid crystal molecules are oriented horizontally, such that an electric field may be generated in the horizontal and vertical directions, and the liquid crystal molecules operate while being twisted and tilted.
In addition,
In addition,
With reference to
In this case, the liquid crystal layer 130 may be referred to as a first liquid crystal layer to be distinguished from a second liquid crystal layer 130a to be described below.
The color filter substrate 105 and the array substrate 110 may include a display area AA and a non-display area NA, and a periphery of the display area AA may be defined as the non-display area NA. For example, the array substrate 110 has a shape in which the non-display area NA extends to the outside of the color filter substrate 105. A drive circuit 180 is connected to a gate pad and a data pad to transmit signals and may be disposed in the extended non-display area NA. A connector, which is fitted with a connector of a terminal line connected to a printed circuit board and transmits signals to the drive circuit 180, may be disposed in the extended non-display area NA.
The color filter, which includes the red, green, and blue sub-color filters 107, may be disposed above the color filter substrate 105. The black matrix 106, which separates the sub-color filters 107 and blocks light passing through the liquid crystal layer 130, may be disposed above the color filter substrate 105. An overcoat layer 109, which planarizes an upper portion of the color filter and an upper portion of the black matrix 106, may be disposed above the color filter substrate 105.
The gate lines (not illustrated) and the data lines 117, which are disposed in the longitudinal and transverse directions and define the pixel area P, may be disposed on the array substrate 110. The thin-film transistor, which are switching elements, may be disposed in the intersection areas (e.g., TFT areas) between the gate lines and the data lines 117.
The color filter substrate 105 and the array substrate 110 are attached by a first sealant 160a in the color filter substrate 105 and the array substrate 110. The first sealant 160a may join the color filter substrate 105 and the array substrate 110 and assist the first spacer 150, which is disposed in the display panel 100, in maintaining the cell gap between the color filter substrate 105 and the array substrate 110.
In addition, the first sealant 160a may retain a liquid crystal injected between the color filter substrate 105 and the array substrate 110.
For example, the first sealant 160a may be provided in the form of a quadrangular frame. However, the present disclosure is not limited thereto.
Meanwhile, in an aspect of the present disclosure, an outer second sealant 160b may be disposed between the color filter substrate 105 and the array substrate 110 in a bezel area BA. The outer second sealant 160b may be disposed outside the first sealant 160a to measure the cell gap. For example, the second sealant 160b may include conductive balls.
For example, the second sealant 160b may be provided in the form of a quadrangular frame that surrounds (e.g., borders) the first sealant 160a. However, the present disclosure is not limited thereto.
In addition, the second liquid crystal layer 130a may be disposed between the first sealant 160a and the second sealant 160b. For example, the second liquid crystal layer 130a may be configured as a liquid crystal having a different type than the liquid crystal of the liquid crystal layer 130 in the display area AA. For example, the second liquid crystal layer 130a may be an IPS crystal and the liquid crystal layer 130 may be a vertical alignment (VA) crystal or a TN crystal. However, the present disclosure is not limited thereto.
In addition, a first electrode 140a and a third electrode 140c may be disposed above the array substrate 110 in the bezel area BA.
For example, the first electrode 140a may be electrically connected to a sensing line 170a through a first contact hole 145a. In addition, the third electrode 140c may be electrically connected to a common signal line 170b through a second contact hole 145b. For example, a gate drive circuit 175 may be disposed between the sensing line 170a and the common signal line 170b. However, the present disclosure is not limited thereto.
In addition, a second electrode 140b may be disposed above the color filter substrate 105 in the bezel area BA. For example, the second electrode 140b may be electrically connected to the third electrode 140c through the conductive balls in the second sealant 160b.
As described above, in the aspect of the present disclosure, the sealants including the first sealant 160a and the second sealant 160b are both formed in the bezel area BA of the display panel 100, and capacitance sensing structures configured by the first electrode 140a and the second electrode 140b are formed in the first sealant 160a and the second sealant 160b. For example, the cell gap in the bezel area BA may be measured and monitored based a capacitance between the first electrode 140a in the first sealant 160a and the second electrode 140b in the sealant 160b. In some examples, an external circuit (e.g., during manufacturing) or an internal circuit (e.g., the gate drive circuit 175) may be configured to detect stress applied to the display panel 100.
Specifically, a gate electrode 121 and a gate line may be disposed in the display area AA (e.g., the TFT area) of the array substrate 110, which is made of a transparent insulating material such as glass.
The gate electrode 121 may constitute a part of the gate line.
For example, the gate line may be disposed in a first direction.
In addition, the gate drive circuit 175, the sensing line 170a, and the common signal line 170b may be disposed in the non-display area NA, e.g., the bezel area BA of the array substrate 110.
The gate electrode 121, the gate line, the gate drive circuit 175, the sensing line 170a, and the common signal line 170b may each be formed by depositing a first metal layer on a front surface of the array substrate 110 and selectively patterning the first metal layer through a photolithography process.
In this case, the first metal layer may include at least any one selected from a group of conductive metals including aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy, molybdenum-tungsten (MoW), molybdenum-titanium (MoTi), and copper/molybdenum-titanium (Cu/MoTi), a combination of two or more of these materials, or other appropriate materials.
The gate drive circuit 175 may be implemented in a gate-on-array (GOA) manner or a gate-in-panel (GIP) manner. However, the present disclosure is not limited thereto. In case that the gate drive circuit 175 is implemented in the GOA or GIP manner, for example, the gate drive circuit 175 may be integrated with the array substrate 110 and included in the array substrate 110, such that the gate drive circuit 175 may be a part of the array substrate 110.
A sensing signal for sensing the cell gap in the bezel area BA may be applied to the sensing line 170a. As shown in
A common electrode signal may be applied to the common signal line 170b. However, the present disclosure is not limited thereto. For example, the common signal line 170b may be disposed outside the gate drive circuit 175 and oriented in the same direction as the data line. One end of the common signal line 170b may extend to the drive circuit 180, such that the common signal line 170b may be supplied with the common electrode signal.
A first insulation layer 115a may be disposed on the front surface of the array substrate 110 on which the gate electrode 121, the gate line, the gate drive circuit 175, the sensing line 170a, and the common signal line 170b are disposed.
The first insulation layer 115a may be a gate insulation layer within the active area AA and include a silicon (Si)-based oxide film, a nitride film, a compound including these films, a metal oxide film containing Al2O3, an organic insulation film, or a material with a dielectric constant (low-k) value.
As shown in
Referring to
The active layer 124 may be configured as a semiconductor layer.
The semiconductor layer may include amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), IGZO-based oxide semiconductors, compound semiconductors, carbon nanotubes, graphene and organic semiconductors, or the like.
The oxide semiconductor may be made of a material, which is made by adding silicon (Si) to an oxide semiconductor including zinc (Zn), and one or more materials selected from a group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga), and aluminum (Al). For example, the semiconductor layer may be made of silicon indium zinc oxide (Si—InZnO: SIZO) made by adding silicon ions to indium zinc composite oxide (InZnO).
In case that the semiconductor layer is made of SIZO, a composition ratio of the silicon (Si) atom content to the total content of zinc (Zn), indium (In), and silicon (Si) atoms in the active layer 124 may be about 0.001 weight % (wt. %) to about 30 wt. %. As the silicon (Si) atom content increases, the function of controlling electron generation may be improved, the mobility may be decreased, and the stability of the elements may be improved. However, the present disclosure is not limited thereto.
For example, in case that the active layer 124 is made of an amorphous silicon thin-film, an n+ amorphous silicon thin-film pattern 125n, which is patterned in substantially the same shape as the active layer 124, may be disposed on the active layer 124. However, the present disclosure is not limited thereto.
A source electrode 122 and a drain electrode 123 may be disposed on the active layer 124.
The data line 117 may be disposed on the same layer as the source electrode 122 and the drain electrode 123.
The data line 117, the source electrode 122, and the drain electrode 123 may constitute a second metal layer.
The second metal layer may include at least any one selected from a group of conductive metals including aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum-tungsten (MoW), molybdenum-titanium (MoTi), and copper/molybdenum-titanium (Cu/MoTi), a combination of two or more of these materials, or other appropriate materials.
As described above, the data lines 117 may be disposed in the second direction that is different from the first direction and separates the plurality of sub-pixels P together with the gate lines.
The gate electrode 121 connected to the gate line, the active layer 124 disposed above the gate electrode 121, the source electrode 122 connected to the data line 117, and the drain electrode 123 disposed to be opposite to the source electrode 122 may constitute the thin-film transistor.
A second insulation layer 115b may be disposed on the same layer on the data line 117, the source electrode 122, and the drain electrode 123.
For example, the second insulation layer 115b may be an interlayer insulation layer and include a silicon (Si)-based oxide film, a nitride film, a compound including these films, a metal oxide film containing Al2O3, an organic insulation film, or a material with a dielectric constant (low-k) value.
As shown in
A third insulation layer 115c may be disposed on the second insulation layer 115b.
For example, the third insulation layer 115c may be a planarization layer and include a silicon (Si)-based oxide film, a nitride film, a compound including these films, a metal oxide film containing Al2O3, an organic insulation film, or a material with a dielectric constant (low-k) value.
The third insulation layer 115c may also extend into the non-display area NA.
The pixel electrode 118 may be disposed on the third insulation layer 115c.
For example, the pixel electrode 118 may be formed in a rectangular shape on the sub-pixel P.
The pixel electrode 118 may be made of a transparent conductive material, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), that has a high transmittance rate. However, the present disclosure is not limited thereto.
A fourth insulation layer 115d may be disposed on the pixel electrode 118.
For example, the fourth insulation layer 115d may include a silicon (Si)-based oxide film, a nitride film, a compound including these films, a metal oxide film containing Al2O3, an organic insulation film, or a material with a dielectric constant (low-k) value.
The fourth insulation layer 115d may also extend into the non-display area NA.
In some cases, predetermined areas of the first insulation layer 115a, the second insulation layer 115b, the third insulation layer 115c are selectively removed to form a drain contact hole and expose a part of the drain electrode 123. In addition, for example, predetermined areas of the first insulation layer 115a, the second insulation layer 115b, the third insulation layer 115c, and the fourth insulation layer 115d are selectively removed, such that the first contact hole 145a, through which a part of the sensing line 170a is exposed, may be formed, and the second contact hole 145b, through which a part of the common signal line 170b is exposed, may be formed.
For example, the first contact hole 145a may be formed for each sensor block SB, and a plurality of second contact hole 145b may be provided for each block SB. However, the present disclosure is not limited thereto.
In addition, the common electrode 108 may include a plurality of slits 108s and may be disposed on the fourth insulation layer 115d.
The plurality of common electrodes 108 may be disposed in a finger or herringbone shape in the sub-pixel P. However, the present disclosure is not limited thereto. The common electrodes 108 may be disposed in a straight shape in the vertical or horizontal direction.
In addition, the first electrode 140a and the third electrode 140c may be disposed on the fourth insulation layer 115d in the non-display area NA.
The first electrode 140a may be electrically connected to the sensing line 170a through the first contact hole 145a. Further, the third electrode 140c may be electrically connected to the common signal line 170b through the second contact hole 145b.
The first electrode 140a and the third electrode 140c may be separated from each other.
The first electrode 140a may have a shape corresponding to the sensor block SB. For example, the first electrode 140a may have a quadrangular shape corresponding to the sensor block SB, and a part of the first electrode 140a may extend toward the sensing line 170a.
The third electrode 140c may be disposed outside the first electrode 140a. For example, the third electrode 140c may be disposed above the common signal line 170b along the common signal line 170b and overlap the common signal line 170b. However, the present disclosure is not limited thereto.
The array substrate 110, which is configured as described above, may be attached to the color filter substrate 105 disposed above the array substrate 110, thereby constituting the display panel 100. The liquid crystal layer 130 is interposed between the array substrate 110 and the color filter substrate 105. Further, the first spacer 150 may be disposed between the color filter substrate 105 and the array substrate 110 to maintain the cell gap between the color filter substrate 105 and the array substrate 110. In this case, for example, the first spacer 150 may be configured as a column spacer.
For example, the array substrate 110, which is configured as described above, is attached to the color filter substrate 105 to be opposite to the color filter substrate 105 based on the first sealant 160a formed at the outer periphery of the display area AA.
In this case, the color filter substrate 105 includes the thin-film transistors, the black matrix 106 to suppress a leak of light to the gate lines and the data lines 117, and the color filter including the red, green, and blue sub-color filters 107.
Meanwhile, in the aspect of the present disclosure, the second sealant 160b may be disposed in the bezel area BA disposed outside the first sealant 160a. For example, the second sealant 160b may be disposed in the bezel area BA disposed between the color filter substrate 105 and the array substrate 110.
For example, the second sealant 160b may include the conductive balls.
In addition, the second liquid crystal layer 130a may be disposed between the first sealant 160a and the second sealant 160b. For example, the second liquid crystal layer 130a may be configured have a different type than the liquid crystal of the liquid crystal layer 130 in the display area AA. However, the present disclosure is not limited thereto.
For example, the second liquid crystal layer 130a may include a liquid crystal with a permittivity of 0 or a low permittivity to not affect electric fields between the first electrode 140a and the third electrode 140c of the array substrate 110 and the second electrode 140b of the color filter substrate 105.
The second electrode 140b may be disposed above the color filter substrate 105 in the bezel area BA. For example, the second electrode 140b may be electrically connected to the third electrode 140c through the conductive balls in the second sealant 160b. Therefore, the second electrode 140b may receive the common electrode signal supplied to the common signal line 170b.
In one example, the second electrode 140b may have a box shape including (or covering) all the plurality of sensor blocks SB. However, the present disclosure is not limited thereto.
A second spacer 150a may be disposed between the first electrode 140a and the second electrode 140b. The second spacer 150a may maintain the cell gap between the color filter substrate 105 and the array substrate 110 in the bezel area BA. For example, the second spacer 150a may be configured as a column spacer.
The second spacer 150a in the non-active area NA may have a different height from the first spacer 150 in the active area AA. The second spacer 150a and the first spacer 150 may be made of the same material or different materials.
In this case, the capacitance sensing structure may be formed between the first electrode 140a, to which the sensing signal is applied, and the second electrode 140b to which the common electrode signal is applied. Therefore, the cell gap in the bezel area BA may be measured and monitored. As a result, it is possible to monitor, in real time, the change in capacitance (Cap) during the module process and immediately cope with detected defects. In addition, it is possible to improve reliability by suppressing an image defect, such as a yellow mura or a bright spot, caused by an external force. For example, the change in capacitance (Cap) may be recognized when the cell gap fluctuates because of stress, such that the stress applied to the display panel 100 may be monitored. For reference, in the related art, the bezel area cannot transmit light because of the black matrix, and the cell gap cannot be measured. In contrast, in the aspect of the present disclosure, the capacitance sensing structure is formed in the bezel area BA, which may monitor the change in capacitance (Cap) in real time. In particular, the aspect of the present disclosure is advantageous in performing quantitative stress analysis on the plurality of sensor blocks SB.
As described above, the present disclosure may actively cope with the non-uniformity of the cell gap in the bezel area BA caused by the increase in narrow bezel models.
The exemplary embodiments of the present disclosure may also be described as follows:
According to an aspect of the present disclosure, a display device is disclosed. The display device includes a first substrate including a display area and a non-display area; a first liquid crystal layer disposed on the display area and the non-display area of the first substrate; a first sealant bordering the first liquid crystal layer; a second liquid crystal layer bordering the first sealant; a second sealant bordering the second liquid crystal layer; and a capacitor formed based on a first electrode and a second electrode at opposite ends of the second liquid crystal layer for detecting stress applied to the display panel.
Another aspect of the present disclosure includes a method for manufacturing a display device. The method includes forming a device layer including a plurality of TFTs; forming an insulation layer over the device layer; forming first holes in the insulation layer along a periphery of an active area of the display panel; forming second holes in the insulation layer that are outside of the first holes; forming a first conductive layer over the first holes and the second holes; forming a first sealant over the first holes; forming a first liquid crystal layer within the active area and the non-active area within the first holes; forming a second sealant over the second holes; forming a second liquid crystal layer between the second sealant and the first sealant; and forming a second conductive layer over the first sealant and the second sealant, wherein the first conductive layer and the second conductive layer form a capacitor.
According to an aspect of the present disclosure, a display device is disclosed. The display device includes a first substrate including a display area and a non-display area; a second substrate attached to the first substrate including a first sealant; a first liquid crystal layer disposed inside a region formed by the first sealant; a second sealant disposed outside a region formed by the first sealant; a second liquid crystal layer disposed between the first sealant and the second sealant; a first electrode disposed on the first substrate in the non-display area; and a second electrode disposed on the second substrate in the non-display area and forming a capacitance with the first electrode.
Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only but not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. All the technical concepts in the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0158281 | Nov 2023 | KR | national |
