DISPLAY DEVICE

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to and the benefit of Korean Patent Application No. 10-2022-0068946, filed on Jun. 7, 2022, filed in the Korean Patent Application Office, the entire content of which is hereby incorporated by reference.

BACKGROUND
1. Field

Aspects of some embodiments relate to a display device.

2. Description of the Related Art

Electronic devices such as smart phones, computers, and tablet PCs may include a display device. Recently, in order to minimize or reduce battery consumption of electronic devices, there is a growing demand for a technology that reduces power consumption of display devices. Accordingly, a low-frequency driving method for driving the display device at a relatively low frequency is being studied.

When the display device is driven at a relatively low frequency (for example, when a period of one frame is relatively long), leakage current in a pixel circuit may increase. Accordingly, a difference in luminance of pixels may occur between successive frames, and a flicker phenomenon may occur in an image displayed on the display device.

The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore the information discussed in this Background section does not necessarily constitute prior art.

SUMMARY

Aspects of some embodiments include a display device with relatively improved low frequency characteristics.

A display device according to some embodiments of the present invention may include a light emitting element, a driving transistor which transmits a driving current to the light emitting element, a first dual transistor including a first sub transistor connected to a gate electrode of the driving transistor, and a second sub transistor connecting an input electrode of the first sub transistor and an output electrode of the driving transistor, an active layer including a first common area defining the input electrode of the first sub transistor and an output electrode of the second sub transistor, a first compensation electrode overlapping at least a portion of the first common area to define the first compensation capacitor, and a first compensation voltage line providing a first compensation voltage to the first compensation electrode.

According to some embodiments, during a first period in which a voltage applied to a gate electrode of the first dual transistor changes from a first turn-on voltage to a first turn-off voltage, the first compensation voltage may change from a first voltage to a second voltage, and a value obtained by multiplying a value obtained by subtracting the first voltage from the second voltage and a value obtained by subtracting the first turn-on voltage from the first turn-off voltage may have a negative value.

According to some embodiments, a planar area of an area where the first common area and the first compensation electrode overlap each other may be larger than a planar area of an area where the active layer and a gate electrode of the first dual transistor overlap each other.

According to some embodiments, the display device may further include a second dual transistor including a third sub transistor connected to the gate electrode of the driving transistor, and a fourth sub transistor connected to an input electrode of the third sub transistor and an initialization voltage line.

According to some embodiments, an output electrode of the third sub transistor may be connected to an output electrode of the first sub transistor.

According to some embodiments, the active layer may further include a second common area defining the input electrode of the third sub transistor and an output electrode of the fourth sub transistor.

According to some embodiments, the display device may further include a second compensation electrode overlapping at least a portion of the second common area to define a second compensation capacitor, and a second compensation voltage line providing a second compensation voltage to the second compensation electrode, and spaced apart from the first compensation voltage line.

According to some embodiments, during a second period in which a voltage applied to a gate electrode of the second dual transistor changes from a second turn-on voltage to a second turn-off voltage, the second compensation voltage may change from a third voltage to a fourth voltage, and a value obtained by multiplying a value obtained by subtracting the third voltage from the fourth voltage and a value obtained by subtracting the second turn-on voltage from the second turn-off voltage may have a negative value.

A display device according to some embodiments of the present invention may include a light emitting element, a driving transistor which transmits a driving current to the light emitting element, a second dual transistor including a third sub transistor connected to a gate electrode of the driving transistor, and a fourth sub transistor connected to an input electrode of the third sub transistor and an initialization voltage line, an active layer including a second common area defining the input electrode of the third sub transistor and an output electrode of the fourth sub transistor, a second compensation electrode overlapping at least a portion of the second common area to define a second compensation capacitor, and a second compensation voltage line providing a second compensation voltage to the second compensation electrode.

According to some embodiments, a planar area of an area where the second common area and the second compensation electrode overlap each other may be larger than a planar area of an area where the active layer and a gate electrode of the second dual transistor overlap each other.

A display device according to some embodiments of the present invention may include a light emitting element, a driving transistor which transmits a driving current to the light emitting element, a first dual transistor including a first sub transistor connected to a gate electrode of the driving transistor, and a second sub transistor connecting an input electrode of the first sub transistor and an output electrode of the driving transistor, a light emitting control transistor connected to the driving transistor, an active layer including a first common area defining the input electrode of the first sub transistor and an output electrode of the second sub transistor, a first compensation electrode overlapping at least a portion of the first common area to define the first compensation capacitor, and a light emitting control line providing a light emitting control voltage to the first compensation electrode and a gate electrode of the light emitting control transistor.

According to some embodiments, during a first period in which a voltage applied to a gate electrode of the first dual transistor changes from a first turn-on voltage to a first turn-off voltage, the light emitting control voltage may change from a first voltage to a second voltage, and a value obtained by multiplying a value obtained by subtracting the first voltage from the second voltage and a value obtained by subtracting the first turn-on voltage from the first turn-off voltage may have a negative value.

According to some embodiments, the light emitting control transistor may include a first light emitting control transistor connecting a first power voltage line providing a first power voltage and an input electrode of the driving transistor, and a second light emitting control transistor connecting an output electrode and the light emitting element.

According to some embodiments, an output electrode of the third sub transistor may be connected to an output electrode of the first sub transistor.

According to some embodiments, the active layer may further include a second common area defining the input electrode of the third sub transistor and an output electrode of the fourth sub transistor.

A display device according to some embodiments may include a first compensation electrode overlapping at least a portion of a first common area of an active layer to define a first compensation capacitor, and a first compensation voltage line providing a first compensation voltage to the first compensation electrode. The first compensation electrode and the first compensation voltage may serve to reduce a leakage current in the first common area, and accordingly, low frequency characteristics of the display device may be relatively improved.

A display device according to some embodiments may include a second compensation electrode overlapping at least a portion of a second common area of an active layer to define a second compensation capacitor, and a second compensation voltage line providing a second compensation voltage to the second compensation electrode. The second compensation electrode and the second compensation voltage may serve to reduce a leakage current in the second common area, and accordingly, low frequency characteristics of the display device may be relatively improved.

A display device according to some embodiments may include a first compensation electrode overlapping at least a portion of a first common area of an active layer to define a first compensation capacitor, and a light emitting control line providing a light emitting control voltage to the first compensation electrode. The first compensation electrode and the light emitting control voltage may serve to reduce a leakage current in the first common area, and accordingly, low frequency characteristics of the display device may be relatively improved.

BRIEF DESCRIPTION OF THE DRAWINGS

Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7, and FIG. 8 are diagrams illustrating a display device according to some embodiments.

FIG. 9, FIG. 10, FIG. 11, FIG. 12, and FIG. 13 are diagrams illustrating a display device according to some embodiments.

FIG. 14, FIG. 15, and FIG. 16 are diagrams illustrating a display device according to some embodiments.

FIG. 17, FIG. 18, FIG. 19, FIG. 20, FIG. 21, and FIG. 22 are diagrams illustrating a display device according to some embodiments.

FIG. 23, FIG. 24, and FIG. 25 are diagrams illustrating a display device according to some embodiments.

DETAILED DESCRIPTION

Hereinafter, aspects of some embodiments of the present disclosure will be explained in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

FIG. 1 is a circuit diagram illustrating a pixel included in a display device according to some embodiments.

Referring to FIG. 1, the display device according to some embodiments may include a pixel PXa. Although a single pixel PXa is illustrated in FIG. 1, a person having ordinary skill in the art would recognize that a display panel comprising the pixel PXa may include a plurality of pixels with the same or similar structure as that of the pixel PXa. The plurality of pixels may be arranged, for example, in a matrix configuration, of a plurality of rows and columns of pixels, and may include any suitable number of pixels according to the design of the display device.

The pixel PXa may be defined as a minimum unit for emitting light. The pixel PXa may include a pixel circuit and a light emitting element DIOD. The pixel circuit may include a plurality of transistors and at least one capacitor. Embodiments according to the present disclosure are not limited to the pixel structure illustrated in FIG. 1. For example, in some embodiments, the pixel circuit of the pixel PXa may include additional components or fewer components without departing from the spirit and scope of embodiments according to the present disclosure.

According to some embodiments, the pixel circuit of the pixel PXa may include a driving transistor, at least one switching transistor, and storage capacitor CST. For example, the pixel circuit may include a first transistor T1 referred to as the driving transistor, a second transistor T2 configured to provide a data voltage to the first transistor T1, a third transistor T3 electrically connecting an output electrode of the first transistor T1 and a gate electrode of the first transistor T1, a storage capacitor CST, and a first compensation capacitor CN.

According to some embodiments, the pixel circuit may further include at least one other switching transistor. For example, the pixel circuit may further include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eight transistor T8.

An input electrode of the first transistor T1 may be connected to the data voltage line DATA, and the output electrode of the first transistor T1 may be connected to the light emitting element DIOD. The first transistor T1 may receive the data voltage from the data voltage line DATA and generate a driving current corresponding to the data voltage. The first transistor T1 may transmit the driving current to the light emitting element DIOD.

An input electrode of the second transistor T2 may be connected to the data voltage line DATA, and an output electrode of the second transistor T2 may be connected to the input electrode of the first transistor T1. A gate electrode of the second transistor T2 may be connected to a gate voltage line GW, and accordingly, the second transistor T2 may be turned on by a first gate voltage provided by the first gate voltage line GW. During a period in which the second transistor T2 is turned on, the second transistor T2 may provide the data voltage to the first transistor T1.

The third transistor T3 may include a first sub transistor T3a and a second sub transistor T3b electrically connected to the first sub transistor T3a through a first common node N3. In other words, the third transistor T3 may be a dual transistor having a dual gate structure. In this case, the third transistor T3 may be referred as a first dual transistor.

An input electrode of the first sub transistor T3a may be connected to an output electrode of the second sub transistor T3b, and an output electrode of the first sub transistor T3a may be connected to the gate electrode of the first transistor T1, and an input electrode of the second sub transistor T3b may be connected to the output electrode of the first transistor T1. A gate electrode of the third transistor T3 may be connected to the second gate voltage line GC, and accordingly, the third transistor T3 may be turned on by a second gate voltage provided by the second gate voltage line GC. During a period in which the third transistor T3 is turned on, the third transistor T3 may compensate a threshold voltage of the first transistor T1 by diode-connecting the first transistor T1.

The fourth transistor T4 may include a third sub transistor T4a and a fourth sub transistor T4b electrically connected to the third sub transistor T4a. In other words, the fourth transistor T4 may be a dual transistor having a dual gate structure. In this case, the fourth transistor T4 may be referred as a second dual transistor.

An output electrode of the third sub transistor T4a may be connected to the gate electrode of the first transistor T1, and an input electrode of the third sub transistor T4a may be connected to an output electrode of the fourth sub transistor T4b, and an input electrode of the fourth sub transistor T4b may be connected to an initialization voltage line VINT. A gate electrode of the fourth transistor T4 may be connected to a third gate voltage line GI, and accordingly, the fourth transistor T4 may be turned on by a third gate voltage provided by the third gate voltage line GI. During a period in which the fourth transistor T4 is turned on, the fourth transistor T4 may provide an initialization voltage provided by the initialization voltage line VINT to the gate electrode of the first transistor T1.

An input electrode of the fifth transistor T5 may be connected to a first power voltage line ELVDD, and an output electrode of the fifth transistor T1 may be connected to the input electrode of the first transistor T1. A gate electrode of the fifth transistor T5 may be connected to the light emitting control line EM, and accordingly, the fifth transistor T5 may be turned on by a light emitting control voltage provided by the light emitting control line EM. A period during a fifth transistor T5 is turned on, the fifth transistor T5 may provide a first power voltage provided by the first power voltage line ELVDD to the first transistor T1.

An input electrode of the sixth transistor T6 may be connected to the output electrode of the first transistor T1, and an output electrode of the sixth transistor T6 may be connected to the light emitting element DIOD. A gate electrode of the sixth transistor T6 may be connected to the light emitting control line EM, and accordingly, the sixth transistor T6 may be turned on by the light emitting control voltage. A period during the sixth transistor T6 is turned on, the sixth transistor T6 may provide the driving current to the light emitting element DIOD. According to some embodiments, the fifth transistor T5 and the sixth transistor T6 may be referred to as a first light emitting control transistor and a second light emitting control transistor.

An input electrode of the seventh transistor T7 may be connected to a light emitting initialization voltage line VAINT, and an output electrode of the seventh transistor T7 may be connected to the light emitting element DIOD. A gate electrode of the seventh transistor T7 may be connected to a fourth gate voltage line GB, and accordingly, the seventh transistor T7 may be turned on by a fourth gate voltage provided by the fourth gate voltage line GB. A period during the seventh transistor T7 is turned on, the seventh transistor T7 may provide a light emitting initialization voltage provide by the light emitting initialization voltage line VAINT to the light emitting element DIOD.

An input electrode of the eight transistor T8 may be connected to a bias voltage line VBIAS, and an output electrode of the eight transistor T8 may be connected to the input electrode of the first transistor T1. A gate electrode of the eight transistor T8 may be connected to the fourth gate voltage line GB, and accordingly, the eight transistor T8 may be turned on by the fourth gate voltage. A period during the eight transistor T8 is turned on, the eight transistor T8 may provide a bias voltage to the first transistor T1.

A first electrode of the storage capacitor CST may be connected to the gate electrode of the first transistor T1, and a second electrode of the storage capacitor CST may be connected to the first power voltage line ELVDD. The storage capacitor CST may maintain voltage level of the gate electrode of the first transistor T1 during an inactivation period of the first gate voltage provided by the first gate voltage line GW.

A first electrode of the first compensation capacitor CN may be connected to the first common node N3, and a second electrode of the first compensation capacitor CN may be connected to a first compensation voltage line C-GC providing a first compensation voltage. The first compensation capacitor CN and the first compensation voltage line C-GC may serve to maintain relatively constant voltage at the first common node N3. Accordingly, a leakage current of the third transistor T3 having the dual gate structure may be relatively reduced, and low frequency characteristics of the display device may be relatively improved.

A first electrode (for example, an anode electrode) of the light emitting element DIOD may be connected to the output electrode of the sixth transistor T6, and a second electrode (for example, a cathode electrode) of the light emitting element DIOD may be connected to the second power voltage line ELVSS. The first electrode of the light emitting element DIOD may receive the driving current, and the light emitting element DIOD may generate light having a luminance corresponding to the driving current.

FIG. 2 is a waveform diagram illustrating an example in which the pixel of FIG. 1 operates. In FIG. 2, an example in which the first sub transistor T3a and the second sub transistor T3b are P-MOS transistors will be described, but the present invention is not limited thereto. For example, the first sub transistor T3a and the second sub transistor T3b may be N-MOS transistors.

Referring to FIG. 2, during a first timing TM1, the second gate voltage provided from the second gate voltage line GC may change from a first turn-off voltage VOFF to ta first turn-on voltage VON, and then change from the first turn-on voltage VON to the first turn-off voltage VOFF. The first turn-off voltage VOFF may be a voltage which turns off the first sub transistor T3a and the second sub transistor T3b, and the first turn-on voltage VON is a voltage which turns on the first sub transistor T3a and the second sub transistor T3b.

During a partial period (for example, a first period D1) of the first timing TM1 in which the second gate voltage changes from the first turn-on voltage VON to the first turn-off voltage VOFF, a voltage at the first common node N3 may increase (for example, a kick-back voltage increase AKV). A leakage current may occur in the first sub transistor T3a and the second sub transistor T3b due to the kick-back voltage increase AKV, and accordingly, a voltage at the gate electrode of the first transistor T1 may increase, so that a flicker phenomenon may occur.

According to some embodiments, the first compensation capacitor CN connected to the first common node N3 may form a capacitance in the first common node N3, and accordingly, the kick-back voltage increase AKV at the first common node N3 may be suppressed.

In addition, according to some embodiments, the first compensation voltage may be provided to the second electrode of the first compensation capacitor CN. According to some embodiments, the first compensation voltage provided form the first compensation voltage line C-GC may change from a first voltage V1 to a second voltage V2 during the first period D1. In this case, a value obtained by multiplying a value obtained by subtracting the first voltage V1 from the second voltage V2 and a value obtained by subtracting the first turn-on voltage VON from the first turn-off voltage VOFF may have a negative value. Accordingly, the first compensation voltage may compensate the second gate voltage during the first period D1 to suppress the kick-back voltage increase AKV at the first common node N3.

FIG. 3 and FIG. 4 are plan views illustrating an active layer ATVa and a first conductive layer C1a included in the pixel PXa of FIG. 1.

Referring to FIG. 3 and FIG. 4, the pixel PXa may include the active layer ATVa and the first conductive layer C1a.

The active layer ATVa may include a semiconductor material. For example, the active layer ATVa may include a silicon semiconductor or an oxide semiconductor.

In the active layer ATVa, an area overlapping the first conductive layer C1a may define a channel area of a transistor. In addition, in the active layer ATVa, an area which does not overlap the first conductive layer C1a may define an input electrode and an output electrode of a transistor.

The first conductive layer C1a may be located on the active layer ATVa. An insulation layer (for example, IL1 of FIG. 7) may be located between the first conductive layer C1a and the active layer ATVa. The first conductive layer C1a may include a conductive material.

The first conductive layer C1a may include a first gate electrode G1, a second gate electrode G2, a third gate electrode G3, a fourth gate electrode G4, the light emitting control line EM, and the fourth gate voltage line GB.

The first gate electrode G1 may be the gate electrode of the first transistor T1. In the active layer ATVa, an area overlapping the first gate electrode G1 may define a channel area of the first transistor T1.

The second gate electrode G2 may be the gate electrode of the second transistor T2. In the active layer ATVa, an area overlapping the second gate electrode G2 may define a channel area of the second transistor T2.

The third gate electrode G3 may be the gate electrode of the third transistor T3. In the active layer ATVa, an area overlapping the third gate electrode may define a channel area of the first sub transistor T3a and a channel area of the second sub transistor T3b. In this case, a first common area A1 of the active layer ATVa may be defined as the input electrode of the first sub transistor T3a and the output electrode of the second sub transistor T3b.

The fourth gate electrode G4 may be the gate electrode of the fourth transistor T4. In the active layer ATVa, an area overlapping the fourth gate electrode G4 may define a channel area of the third sub transistor T4a and a channel area of the fourth sub transistor T4b. In this case, a second common area A2 of the active layer ATVa may be defined as the input electrode of the third sub transistor T4a and the output electrode of the fourth sub transistor T4b.

The light emitting control voltage may be provided to the light emitting control line EM. In the light emitting control line EM, a portion overlapping the active layer ATVa may be the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6. In addition, in the active layer ATVa, an area overlapping the light emitting control line EM may define a channel area of the fifth transistor T5 and a channel area of the sixth transistor T6.

The fourth gate voltage may be provided to the fourth gate voltage line GB. In the fourth gate voltage line GB, a portion overlapping the active layer ATVa may be the gate electrode of the seventh transistor T7 and the gate electrode of the eight transistor T8. In addition, in the active layer ATVa, an area overlapping the fourth gate voltage line GB may define a channel area of the seventh transistor T7 and a channel area of the eight transistor T8.

FIG. 5 is a plan view illustrating the active layer ATVa, the first conductive layer C1a, and a second conductive layer C2a.

Referring to FIG. 5, the second conductive layer C2a may be located on the first conductive layer C1a. An insulation layer (for example, IL2 of FIG. 7) may be located between the second conductive layer C2a and the first conductive layer C1a. The second conductive layer C2a may include a conductive material.

The second conductive layer C2a may include a capacitor electrode CE and a first compensation electrode CM.

The capacitor electrode CE may define the storage capacitor CST by overlapping the first gate electrode G1. In this case, the first gate electrode G1 may be the first electrode of the storage capacitor CST, and the capacitor electrode CE may be the second electrode of the storage capacitor CST.

The first compensation electrode CM may define the first compensation capacitor CN by overlapping the first common area A1 of the active layer ATVa. In this case, the first common area A1 of the active layer ATVa may be the first electrode of the first compensation capacitor CN, and the first compensation electrode CM may be the second electrode of the first compensation capacitor CN.

FIG. 6 is a plan view illustrating the active layer ATVa, the first conductive layer C1a, the second conductive layer C2a, and a third conductive layer C3a.

Referring to FIG. 6, the third conductive layer C3a may be located on the second conductive layer C2a. An insulation layer (for example, IL3 of FIG. 7) may be located between the third conductive layer C3a and the second conductive layer C2a. The third conductive layer C3a may include a conductive material.

The third conductive layer C3a may include a first bridge electrode BR1, a second bridge electrode BR2, a third bridge electrode BR3, a fourth bridge electrode BR4, a fifth bridge electrode BR5, the first gate voltage line GW, the second gate voltage line GC, the third gate voltage line GI, the first compensation voltage line C-GC, a first horizontal power voltage line ELVDD_H, a horizontal light emitting initialization voltage line VAINT_H, and the bias voltage line VBIAS.

The first bridge electrode BR1 may be connected to the input electrode of the fourth sub transistor T4b.

The second bridge electrode BR2 may be connected to the input electrode of the second transistor T2.

The third bridge electrode BR3 may be connected to the output electrode of the first sub transistor T3a, the output electrode of the third sub transistor T4a, and the first gate electrode G1.

The fourth bridge electrode BR4 may be connected to the input electrode of the first transistor T1, the output electrode of the fifth transistor T5, and the output electrode of the eight transistor T8.

The fifth bridge electrode BR5 may be connected to the output electrode of the sixth transistor T6 and the output electrode of the seventh transistor T7.

The first gate voltage may be provided to the first gate voltage line GW. The first gate voltage line GW may be connected to the second gate electrode G2.

The second gate voltage may be provided to the second gate voltage line GC. The second gate voltage line GC may be connected to the third gate electrode G3.

The third gate voltage may be provided to the third gate voltage line GI. The third gate voltage line GI may be connected to the fourth gate electrode G4.

The first compensation voltage may be provided to the first compensation voltage line C-GC. The first compensation voltage line C-GC may be connected to the first compensation electrode CM.

The first power voltage may be provided to the first horizontal power voltage line ELVDD_H. The first horizontal power voltage line ELVDD_H may be connected to the capacitor electrode CE and the input electrode of the fifth transistor T5.

The light emitting initialization voltage may be provided to the horizontal light emitting initialization voltage line VAINT_H. The horizontal light emitting initialization voltage line VAINT_H may be connected to the input electrode of the seventh transistor T7.

The bias voltage may be provided to the bias voltage line VBIAS. The bias voltage line VBIAS may be connected to the input electrode of the eight transistor T8.

FIG. 7 is a cross-sectional view taken along a line I-I′ of FIG. 6.

Referring to FIG. 7, the pixel PXa may include a base substrate BS, the active layer ATVa, a first insulation layer IL1, the third gate electrode G3, a second insulation layer IL2, the first compensation electrode CM, a third insulation layer 113, and a first compensation voltage line C-GC.

The base substrate BS may include glass, plastic, etc. According to some embodiments, the base substrate BS may include a material having flexibility, and accordingly, the base substrate BS may have flexibility.

The active layer ATVa may be located on the base substrate BS, and the first insulation layer IL1 may be located on the active layer ATVa. The first insulation layer IL1 may include an inorganic insulation material.

The third gate electrode G3 may be located on the first insulation layer IL1, and the second insulation layer IL2 may be located on the third gate electrode G3. The second insulation layer IL2 may include an inorganic insulation material.

The first compensation electrode CM may be located on the second insulation layer IL2, and the third insulation layer IL3 may be located on the first compensation electrode CM. The third insulation layer IL3 may include an inorganic insulation material.

The first compensation voltage line C-GC may be located on the third insulation layer 113. The first compensation voltage line C-GC may be connected to the first compensation electrode CM through a through hole penetrating the third insulation layer IL3 and exposing at least a portion of the first compensation electrode CM. Accordingly, the first compensation voltage line C-GC may provide the first compensation voltage to the first compensation electrode CM.

In the active layer ATVa, an area overlapping the third gate electrode G3 may define a channel area T3a_C of the first sub transistor T3a and a channel area T3b_C of the second sub transistor T3b.

In addition, in the first common area A1 of the active layer ATVa, an area overlapping the first compensation electrode CM may define a first overlapping area N3_C. The first overlap area N3_C may be the first compensation capacitor CN. In this case, as an planar area of the first overlapping area N3_C increases, a capacitance of the first compensation capacitor CN may increase.

According to some embodiment, the planar area of the first overlapping area N3_C may be relatively large so that the first compensation capacitor CN may have a relatively large capacitance. For example, the planar area of the first overlapping area N3_C may be larger than sum of a planar area of the channel area T3a_C of the first sub transistor T3a and a planar area of the channel area T3b_C of the second sub transistor T3b.

As described above, as the first compensation capacitor CN has a relatively large capacitance, the kick-back voltage increase AKV may be effectively suppressed.

FIG. 8 is a plan view illustrating the active layer ATVa, the first conductive layer C1a, the second conductive layer C2a, the third conductive layer C3a, and a fourth conductive layer C4a included in the pixel PXa of FIG. 1.

The fourth conductive layer C4a may be located on the third conductive layer C3a. An insulation layer may be located between the fourth conductive layer C4a and the third conductive layer C3a. The fourth conductive layer C4a may include a conductive material.

The fourth conductive layer C4a may include the data voltage line DATA, a first vertical power voltage line ELVDD_V, a vertical light emitting initialization voltage line VAINT_V, and the initialization voltage line VINT.

The data voltage may be provided to the date voltage line DATA. The data voltage line DATA may be connected to the second bridge electrode BR2.

The first power voltage may be provided to the first vertical power voltage line ELVDD_V. The first vertical power voltage line ELVDD_V may be connected to the first horizontal power voltage line ELVDD_H. The first vertical power voltage line ELVDD_V and the first horizontal power voltage line ELVDD_H may define the first power voltage line ELVDD.

The light emitting initialization voltage may be provided to the vertical light emitting initialization voltage line VAINT_V. The vertical light emitting initialization voltage line VAINT_V may be connected to the horizontal light emitting initialization voltage line VAINT_H. The vertical light emitting initialization voltage line VAINT_V and the horizontal light emitting initialization voltage line VAINT_H may define the light emitting initialization voltage line VAINT.

The initialization voltage may be provided to the initialization voltage line VINT. The initialization voltage line VINT may be connected to the first bridge electrode BR1.

FIG. 9 is a circuit diagram illustrating a pixel included in a display device according to some embodiments.

Referring to FIG. 9, the display device according to some embodiments may include a pixel PXb.

The pixel PXb may be defined as a minimum unit for emitting light. The pixel PXb may include a pixel circuit and a light emitting element DIOD. The pixel circuit may include a plurality of transistors and at least one capacitor.

Optionally, the pixel circuit may further include at least one other switching transistor. For example, the pixel circuit may further include a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eight transistor T8.

Hereinafter, description substantially same as or similar to that described with reference to FIG. 1 may be omitted.

The fourth transistor T4 may include a third sub transistor T4a and a fourth sub transistor T4b. The third sub transistor T4a and the fourth sub transistor T4b may be electrically connected to each other through a second common node N4. In other words, the fourth transistor T4 may be a dual transistor having a dual gate structure.

An input electrode of the third sub transistor T4a may be connected to an output electrode of the fourth sub transistor T4b, and an output electrode of the third sub transistor T4a may be connected to a gate electrode of the first transistor T1, and an input electrode of the fourth sub transistor T4b may be connected to the initialization voltage line VINT. Optionally, when the pixel circuit further includes the third transistor T3, the output electrode of the third sub transistor T4a may be connected to an output electrode of a first sub transistor T3a. A gate electrode of the fourth transistor T4 may be connected to a third gate voltage line GI, and accordingly, the fourth transistor T4 may be turned on by a third gate voltage provided by the third gate voltage line GI.

A first electrode of the second compensation capacitor CN′ may be connected to the second common node N4, and a second electrode of the second compensation capacitor CN′ may be connected to a second compensation voltage line C-GI providing a second compensation voltage. The second compensation capacitor CN′ and the second compensation voltage line C-GI may serve to maintain relatively constant voltage at the second common node N4. Accordingly, a leakage current of the fourth transistor T4 having the dual gate structure may be reduced, and low frequency characteristics of the display device may be relatively improved.

FIG. 10 is a waveform diagram illustrating an example in which the pixel of FIG. 9 operates. In FIG. 10, an example in which the third sub transistor T4a and the fourth sub transistor T4b are P-MOS transistors will be described, but embodiments according to the present invention are not limited thereto. For example, the third sub transistor T4a and the fourth sub transistor T4b may be N-MOS transistor.

Referring to FIG. 10, during a second timing TM2, the third gate voltage provided from the third gate voltage line GI may change from a second turn-off voltage VOFF′ to a second turn-on voltage VON′, and then change from the second turn-on voltage VON′ to the second turn-off voltage VOFF. The second turn-off voltage VOFF may be a voltage which turns of the third sub transistor T4a and the fourth sub transistor T4b, and the second turn-on voltage VON′ may be a voltage which turns on the third sub transistor T4a and the fourth sub transistor T4b.

During a partial period (for example, a second period D2) of the second timing TM2 in which the third gate voltage changes from the second turn-on voltage VON′ to the second turn-off voltage VOFF, a voltage at the second common node N4 may increase (for example, a kick-back voltage increase AKV′). A leakage current may occur in the third sub transistor T4a and the fourth sub transistor T4b due to the kick-back voltage increase AKV′, and accordingly, a voltage at the gate electrode of the first transistor T1 may increase, so that a flicker phenomenon may occur.

According to some embodiments, the second compensation capacitor CN′ connected to the second common node N4 may form a capacitance in the second common node N4, and accordingly, the kick-back voltage increase AKV′ at the second common node N4 may be suppressed.

In addition, according to some embodiments, the second compensation voltage may be provided to the second electrode of the second compensation capacitor CN′. According to some embodiments, the second compensation voltage provided form the second compensation voltage line C-GI may change from a third voltage V3 to the fourth voltage V4 during the second period D2. In this case, a value obtained by multiplying a value obtained by subtracting the third voltage V3 from the fourth voltage V4 and a value obtained by subtracting the second turn-on voltage VON′ from the second turn-off voltage VOFF may have a negative value. Accordingly, the second compensation voltage may compensate the third gate voltage during the second period D2 to suppress the kick-back voltage increase AKV′ at the fourth common node N4.

FIG. 11 is a plan view illustrating an active layer ATVa, a first conductive layer C1a, and a second conductive layer C2b included in the pixel PXb of FIG. 9.

Referring to FIG. 11, the pixel PXb may include the active layer ATVa, the first conductive layer C1a, and the second conductive layer C2b.

The active layer ATVa and the first conductive layer C1a included in the pixel PXb may be substantially same as the active layer ATVa and the first conductive layer C1a described with reference to FIG. 3 and FIG. 4.

The second conductive layer C2b may include a capacitor electrode CE and a second compensation electrode CM′.

The capacitor electrode CE included in the second conductive layer C2b may be substantially same as the capacitor electrode CE described with reference to FIG. 5.

The second compensation electrode CM′ may overlap the second common area A2 to define the second compensation capacitor CN′. In this case, the second common area A2 of the active layer ATVa may be the first electrode of the second compensation capacitor CN′, and the second compensation electrode CM′ may be the second electrode of the second compensation capacitor CN′.

FIG. 12 is a plan view illustrating the active layer ATVa, the first conductive layer C1a, the second conductive layer C2b, and a third conductive layer C3b included in the pixel PXb of FIG. 9.

Referring to FIG. 12, the third conductive layer C3b may be located on the second conductive layer C2b. An insulation layer (for example, IL3 of FIG. 13) may be located between the third conductive layer C3b and the second conductive layer C2b. The third conductive layer C3b may include a conductive material.

The third conductive layer C3b may include a first bridge electrode BR1, a second bridge electrode BR2, a third bridge electrode BR3, a fourth bridge electrode BR4, a fifth bridge electrode BR5, a first gate voltage line GW, a second gate voltage line GC, the third gate voltage line GI, the second compensation voltage line C-GI, a first horizontal power voltage line ELVDD_H, a horizontal light emitting initialization line VAINT_H, and a bias voltage line VBIAS.

The first bridge electrode BR1, the second bridge electrode BR2, the third bridge electrode BR3, the fourth bridge electrode BR4, the fifth bridge electrode BR5, the first gate voltage line GW, the second gate voltage line GC, the third gate voltage line GI, the first horizontal power voltage line ELVDD_H, the horizontal light emitting initialization line VAINT_H, and the bias voltage line VBIAS included in the third conductive layer C3b may be substantially same as the first bridge electrode BR1, the second bridge electrode BR2, the third bridge electrode BR3, the fourth bridge electrode BR4, the fifth bridge electrode BR5, the first gate voltage line GW, the second gate voltage line GC, the third gate voltage line GI, the first horizontal power voltage line ELVDD_H, the horizontal light emitting initialization line VAINT_H, and the bias voltage line VBIAS described with reference to FIG. 5.

The second compensation voltage may be provided to the second compensation voltage line C-GI. The second compensation voltage line C-GI may be connected to the second compensation electrode CM′.

According to some embodiments, the fourth conductive layer C4a described with reference to FIG. 8 may be located on the third conductive layer C3b. In this case, an insulation layer may be located between the fourth conductive layer C4a and the third conductive layer C3b.

FIG. 13 is a cross-sectional view taken along a line II-II′ of FIG. 12.

Referring to FIG. 13, the pixel PXb may include a base substrate BS, the active layer ATVa, a first insulation layer IL1, the fourth gate electrode G4, a second insulation layer 112, the second compensation electrode CM′, a third insulation layer IL3, the first gate voltage line GW, the third gate voltage line GI, and the second compensation voltage line C-GI.

The fourth gate electrode G4 may be located on the first insulation layer IL1, and the second insulation layer IL2 may be located on the fourth gate electrode G4. The second insulation layer IL2 may include an inorganic insulation material.

The second compensation electrode CM′ may be located on the second insulation layer IL2, and the third insulation layer IL3 may be located on the second compensation electrode CM′. The third insulation layer IL3 may include an inorganic insulation material.

The first gate voltage line GW, the third gate voltage line GI, and the second compensation voltage line C-GI may be located on the third insulation layer IL3. The second compensation voltage line C-GI may be connected to the second compensation electrode CM′ through a through hole penetrating the third insulation layer IL3 and exposing at least a portion of the second compensation electrode CM′. Accordingly, the second compensation voltage line C-GI may provide the second compensation voltage to the second compensation electrode CM′.

In the active layer ATVa, an area overlapping the fourth gate electrode G4 may define a channel area T4a_C of the third sub transistor T4a and a channel area T4b_C of the fourth sub transistor T4b.

In addition, in the second common area A2 of the active layer ATVa, an area overlapping the second compensation electrode CM′ may define a second overlapping area N4_C. The second overlapping area N4_C may be the first electrode of the second compensation capacitor CN′. In this case, as a planar area of the second overlapping area N4_C increases, capacitance of the second compensation capacitor CN′ may increase.

According to some embodiments, the planar area of the second overlapping area N4_C may be relatively large so that the second compensation capacitor CN′ may have a relatively large capacitance. For example, the planar area of the second overlapping area N4_C may be larger than sum of a planar area of the channel area T4a_C of the third sub transistor T4a and a planar area of the channel area T4b_C of the fourth sub transistor T4b.

As described above, as the second compensation capacitor CN′ has a relatively large capacitance, the kick-back voltage increase AKV′ may be effectively suppressed.

FIG. 14 is a circuit diagram illustrating a pixel included in a display device according to some embodiments.

Referring to FIG. 14, the display device according to some embodiments may include a pixel PXc.

The pixel PXc may be defined as a minimum unit for emitting light. The pixel PXc may include a pixel circuit and a light emitting element DIOD. The pixel circuit may include a plurality of transistors and at least one capacitor.

According to some embodiments, the pixel circuit may include a driving transistor, at least one switching transistor, and a storage capacitor CST. For example, the pixel circuit may include a first transistor T1 referred to as the driving transistor, a second transistor T2 providing a data voltage to the first transistor T1, a third transistor T3 electrically connecting an output electrode of the first transistor T1 and a gate electrode of the first transistor T1, a fourth transistor T4 electrically connecting a gate electrode of the first transistor T1 and an initialization voltage line VINT, the storage capacitor CST, a first compensation capacitor CN, and a second compensation capacitor CN′.

Optionally, the pixel circuit may further include at least one other switching transistor. For example, the pixel circuit may further include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eight transistor T8.

Hereinafter, description substantially same as or similar to that described with reference to FIG. 1 and FIG. 9 may be omitted.

The third transistor T3, the first compensation capacitor CN, and the first compensation voltage line C-GC may be substantially same as the third transistor T3, the first compensation capacitor CN, and the first compensation voltage line C-GC described with reference to FIG. 1.

The first compensation capacitor CN and the first compensation voltage line C-GC may serve to maintain relatively constant voltage at the first common node N3 (Refer to FIG. 2). Accordingly, a leakage current of the third transistor T3 having the dual gate structure may be reduced, and low frequency characteristics of the display device may be relatively improved.

The fourth transistor T4, the second compensation capacitor CN′, and the second compensation voltage line C-GI may be substantially same as the fourth transistor T4, the second compensation capacitor CN′, and the second compensation voltage line C-GI described with reference to FIG. 9.

The second compensation capacitor CN′ and the second compensation voltage line C-GI may serve to maintain relatively constant voltage at the second common node N4 (Refer to FIG. 10). Accordingly, a leakage current of the fourth transistor T4 having the dual gate structure may be reduced, and low frequency characteristics of the display device may be relatively improved.

FIG. 15 is a plan view illustrating an active layer ATVa, a first conductive layer C1a, and a second conductive layer C2c included in the pixel PXc of FIG. 14.

Referring to FIG. 15, the pixel PXc may include the active layer ATVa, the first conductive layer C1a, and the second conductive layer C2c.

The active layer ATVa and the first conductive layer C1a included in the pixel PXc may be substantially same as the active layer ATVa and the first conductive layer C1a described with reference to FIG. 3 and FIG. 4.

The second conductive layer C2c may be located on the first conductive layer C1a. An insulation layer may be located between the second conductive layer C2c and the first conductive layer C1a. The second conductive layer C2c may include a conductive material.

The second conductive layer C2c may include a capacitor electrode CE, a first compensation electrode CM, and a second compensation electrode CM2.

The capacitor electrode CE included in the second conductive layer C2c may be substantially same as the capacitor electrode CE described with reference to FIG. 5.

The first compensation electrode CM included in the second conductive layer C2c may be substantially same as the first compensation electrode CM described with reference to FIG. 5. That is, the first compensation electrode CM may overlap the first common area A1 of the active layer ATVa to define the first compensation capacitor CN.

The second compensation electrode CM′ included in the second conductive layer C2c may be substantially same as the second compensation electrode CM′ described with reference to FIG. 11. That is, the second compensation electrode CM′ may overlap the second common area A2 of the active layer ATVa to define the second compensation capacitor CN′.

FIG. 16 is a plan view illustrating the active layer ATVa, the first conductive layer C1a, the second conductive layer C2c, and a third conductive layer C3c included in the pixel PXc of FIG. 14.

Referring to FIG. 16, the third conductive layer C3c may be located on the second conductive layer C2c. An insulation layer may be located between the third conductive layer C3c and the second conductive layer C2c. The third conductive layer C3c may include a conductive material.

The third conductive layer C3c may include a first bridge electrode BR1, a second bridge electrode BR2, a third bridge electrode BR3, a fourth bridge electrode BR4, a fifth bridge electrode BR5, a first gate voltage line GW, a second gate voltage line GC, the first compensation voltage line C-GC, the second compensation voltage line C-GI, a first horizontal power voltage line ELVDD_H, a horizontal light emitting initialization voltage line VAINT_H, and a bias voltage line VBIAS.

The first bridge electrode BR1, the second bridge electrode BR2, the third bridge electrode BR3, the fourth bridge electrode BR4, the fifth bridge electrode BR5, the first gate voltage line GW, the second gate voltage line GC, the first horizontal power voltage line ELVDD_H, the horizontal light emitting initialization voltage line VAINT_H, and the bias voltage line VBIAS included in the third conductive layer C3c may be substantially same as the first bridge electrode BR1, the second bridge electrode BR2, the third bridge electrode BR3, the fourth bridge electrode BR4, the fifth bridge electrode BR5, the first gate voltage line GW, the second gate voltage line GC, the first horizontal power voltage line ELVDD_H, the horizontal light emitting initialization voltage line VAINT_H, and the bias voltage line VBIAS described with reference to FIG. 6.

The first compensation voltage line C-GC included in the third conductive layer C3c may be substantially same as the first compensation voltage line C-GC described with reference to FIG. 6 and FIG. 7. That is, the first compensation voltage line C-GC may be connected to the first compensation electrode CM, and accordingly, the first compensation voltage line C-GC may provide the first compensation voltage line to the first compensation electrode CM.

The second compensation voltage line C-GI included in the third conductive layer C3c may be substantially same as the second compensation voltage line C-GI described with reference to FIG. 12 and FIG. 13. That is, the second compensation voltage line C-GI may be connected to the second compensation electrode CM′, and accordingly, the second compensation voltage line C-GI may provide the second compensation voltage to the second compensation electrode CM′.

According to some embodiments, the fourth conductive layer C4a described with reference to FIG. 8 may be located on the third conductive layer C3c. In this case, an insulation layer may be located between the fourth conductive layer C4a and the third conductive layer C3c.

FIG. 17 is a circuit diagram illustrating a pixel included in a display device according to some embodiments.

Referring to FIG. 17, a display device according to some embodiments may include a pixel PXd.

The pixel PXd may be defined as a minimum unit for emitting light. The pixel PXd may include a pixel circuit and a light emitting element DIOD. The pixel circuit may include a plurality of transistors and at least one capacitor.

According to some embodiments, the pixel circuit may include a driving transistor, at least one switching transistor, and a storage capacitor CST. For example, the pixel circuit may include a first transistor T1 referred to as the driving transistor, a second transistor T2 providing a data voltage to the first transistor T1, a third transistor T3 electrically connecting an output electrode of the first transistor T1 and a gate electrode of the first transistor T1, the storage capacitor CST, and a first compensation capacitor CN. In this case, the pixel circuit may further include at least one of a fifth transistor T5 or a sixth transistor T6.

Optionally, the pixel circuit may further include at least one other switching transistor. For example, the pixel circuit may further include a fourth transistor T4, a seventh transistor T7, and an eight transistor T8.

Hereinafter, description substantially same as or similar to that described with reference to FIG. 1 may be omitted.

The fifth transistor T5 and the sixth transistor T6 may be referred to as a light emitting control transistor. According to some embodiments, the fifth transistor T5 may be referred to as a first light emitting control transistor, and the sixth transistor T6 may be referred to as a sixth light emitting control transistor.

A gate electrode of the fifth transistor T5 may be connected to a light emitting control line EM′, and accordingly, the fifth transistor T5 may be turned on by a light emitting control voltage provided by the light emitting control line EM′.

A gate electrode of the sixth transistor T6 may be connected to the light emitting control line EM′, and accordingly, the sixth transistor T6 may be turned on by the light emitting control voltage.

A first electrode of the first compensation capacitor CN may be connected to the first common node N3, and a second electrode of the first compensation capacitor CN may be connected to the light emitting control line EM′. The first compensation capacitor CN and the light emitting control line EM′ may serve to maintain relatively constant voltage at the first common node N3. Accordingly, a leakage current of the third transistor T3 having the dual gate structure may be reduced, and low frequency characteristics of the display device may be relatively improved.

FIG. 18 is a waveform diagram illustrating an example in which the pixel of FIG. 17 operates. In FIG. 18, an example in which the first sub transistor T3a, the second sub transistor T3b, the fifth transistor T5, and the sixth transistor T6 are P-MOS transistors will be described, but the present invention is not limited thereto. For example, at least one of the first sub transistor T3a, the second sub transistor T3b, the fifth transistor T5, or the sixth transistor T6 may be N-MOS transistor.

Referring to FIG. 18, during a first timing TM1, a second gate voltage provided from a second gate voltage line GC may change from a first turn-off voltage VOFF to ta first turn-on voltage VON, and then change from the first turn-on voltage VON to the first turn-off voltage VOFF. The first turn-off voltage VOFF may be a voltage which turns off the first sub transistor T3a and the second sub transistor T3b, and the first turn-on voltage VON is a voltage which turns on the first sub transistor T3a and the second sub transistor T3b.

In addition, according to some embodiments, the light emitting control voltage may be provided to the second electrode of the first compensation capacitor CN. During a third timing TM3 before the first timing TM1, the light emitting control voltage provided from the light emitting control voltage line EM may change from a turn-on voltage to a turn-off voltage. During the first timing TM1, the light emitting control voltage may change from the turn-off voltage to turn-on voltage.

According to some embodiments, the light emitting control voltage provided from the light emitting control voltage line EM may change from a first voltage V1′ to a second voltage V2′ during the first period D1. In this case, a value obtained by multiplying a value obtained by subtracting the first voltage V1′ from the second voltage V2′ and a value obtained by subtracting the first turn-on voltage VON from the first turn-off voltage VOFF may have a negative value. Accordingly, the first compensation voltage may compensate the second gate voltage during the first period D1 to suppress the kick-back voltage increase AKV at the first common node N3.

FIG. 19 is a plan view illustrating an active layer ATVa and a first conductive layer C1b included in the pixel PXd of FIG. 17.

Referring to FIG. 19, the pixel PXd may include the active layer ATVa and the first conductive layer C1b.

The active layer ATVa included in the pixel PXd may be substantially same as the active layer ATVa described with reference to FIG. 3 and FIG. 4.

The first conductive layer C1b may be located on the active layer ATVa. An insulation layer (for example, IL1 of FIG. 22) may be located between the first conductive layer C1b and the active layer ATVa. The first conductive layer C1b may include a conductive material.

The first conductive layer C1b may include a first gate electrode G1, a second gate electrode G2, a third gate electrode G3, a fourth gate electrode G4, the light emitting control line EM′, and a fourth gate voltage line GB.

The first gate electrode G1, the second gate electrode G2, the third gate electrode G3, the fourth gate electrode G4, and the fourth gate voltage line GB included in the first conductive layer C1b may be substantially same as the first gate electrode G1, the second gate electrode G2, the third gate electrode G3, the fourth gate electrode G4, and the fourth gate voltage line GB described with reference to FIG. 3 and FIG. 4.

The light emitting control voltage may be provided to the light emitting control line EM′. In the light emitting control line EM′, a portion overlapping the active layer ATVa may be the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6. In addition, in the active layer ATVa, an area overlapping the light emitting control line EM′ may define a channel area of the fifth transistor T5 and a channel area of the sixth transistor T6.

According to some embodiments, the light emitting control line EM′ may include an extension portion EXP. The extension portion EXP may extends in a direction crossing the extension direction of the light emitting control line EM′. In this case, a portion of the extension portion EXP may be adjacent to the first common area A1 of the active layer ATVa.

FIG. 20 is a plan view illustrating the active layer ATVa, the first conductive layer C1b, and a second conductive layer C2a included in the pixel PXd.

Referring to FIG. 20, the second conductive layer C2a may be located on the first conductive layer C1b. The second conductive layer C2a included in the pixel PXd may be substantially same as the second conductive layer C2a described with reference to FIG. 5. For example, the second conductive layer C2a may include the first compensation electrode CM overlapping the first common area A1 of the active layer ATVa to define the first compensation capacitor CN.

FIG. 21 is a plan view illustrating the active layer ATVa, the first conductive layer C1b, the second conductive layer C2a, and a third conductive layer C3d included in the pixel PXd.

Referring to FIG. 21, the third conductive layer C3d may be located on the second conductive layer C2a. An insulation layer (for example, IL3 of FIG. 22) may be located between the third conductive layer C3d and the second conductive layer C2a. The third conductive layer C3d may include a conductive material.

The third conductive layer C3d may include a first bridge electrode BR1, a second bridge electrode BR2, a third bridge electrode BR3, a fourth bridge electrode BR4, a fifth bridge electrode BR5, a first gate voltage line GW, a second gate voltage line GC, a third gate voltage line GI, a connection electrode CC, a first horizontal power voltage line ELVDD_H, a horizontal light emitting initialization voltage line VAINT_H, and a bias voltage line VBIAS.

The first bridge electrode BR1, the second bridge electrode BR2, the third bridge electrode BR3, the fourth bridge electrode BR4, the fifth bridge electrode BR5, the first gate voltage line GW, the second gate voltage line GC, the third gate voltage line GI, the first horizontal power voltage line ELVDD_H, the horizontal light emitting initialization voltage line VAINT_H, and the bias voltage line VBIAS included in the third conductive layer C3d may be substantially same as the first bridge electrode BR1, the second bridge electrode BR2, the third bridge electrode BR3, the fourth bridge electrode BR4, the fifth bridge electrode BR5, the first gate voltage line GW, the second gate voltage line GC, the third gate voltage line GI, the first horizontal power voltage line ELVDD_H, the horizontal light emitting initialization voltage line VAINT_H, and the bias voltage line VBIAS described with reference to FIG. 6.

The connection electrode CC may connect the first compensation electrode CM and the light emitting control line EM′. According to some embodiments, the connection electrode CC may connect the first compensation electrode CM and the extension portion EXP of the light emitting control line EM′. Accordingly, the light emitting control voltage provided by the light emitting control line EM′ may be provided to the first compensation electrode CM through the connection electrode CC.

According to some embodiments, the fourth conductive layer C4a described with reference to FIG. 8 may be located on the third conductive layer C3d. In this case, an insulation layer may be located between the fourth conductive layer C4a and the third conductive layer C3d.

FIG. 22 is a cross-sectional view taken along a line III-III′ of FIG. 21.

Referring to FIG. 22, the pixel PXd may include a base substrate BS, the active layer ATVa, a first insulation layer IL1, the third gate electrode G3, a second insulation layer IL2, the first compensation electrode CM, a third insulation layer IL3, and the connection electrode CC.

The connection electrode CC may be located on the third insulation layer IL3. The connection electrode CC may be connected to the first compensation electrode CM through a through hole penetrating the third insulation layer IL3 and exposing at least a portion of the first compensation electrode CM.

In the active layer ATVa, an area overlapping the third gate electrode G3 may define a channel area T3a_C of the first sub transistor T3a and a channel area T3b_C of the second sub transistor T3b.

In addition, in the first common area A1 of the active layer ATVa, an area overlapping the first compensation electrode CM may define a first overlapping area N3_C. The first overlapping area N3_C may be the first electrode of the first compensation capacitor CN. In this case, as a planar area of the first overlapping area N3_C increases, a capacitance of the first compensation capacitor CN may increase.

According to some embodiments, the planar area of the first overlapping area N3_C may be relatively large so that the first compensation capacitor CN may have a relatively large capacitance. For example, the planar area of the first overlapping area N3_C may be larger than sum of a planar area of the channel area T3a_C of the first sub transistor T3a and a planar area of the channel area T3b_C of the second sub transistor T3b.

As described above, as the first compensation capacitor CN has a relatively large capacitance, the kick-back voltage increase AKV may be effectively suppressed.

FIG. 23 is a circuit diagram illustrating a pixel included in a display device according to some embodiments.

Referring to FIG. 23, a display device according to some embodiments may include a pixel PXe.

The pixel PXe may be defined as a minimum unit for emitting light. The pixel PXe may include a pixel circuit and a light emitting element DIOD. The pixel circuit may include a plurality of transistors and at least one capacitor.

Optionally, the pixel circuit may further include at least one other switching transistor. For example, the pixel circuit may further include a seventh transistor T7, and an eight transistor T8.

Hereinafter, description substantially same as or similar to that described with reference to FIG. 1, FIG. 9, and FIG. 17 may be omitted.

The third transistor T3, the first compensation capacitor CN, and the light emitting control line EM′ include in the pixel PXe may be substantially same as the third transistor T3, the first compensation capacitor CN, and the light emitting control line EM′ described with reference to FIG. 17.

The first compensation capacitor CN and the light emitting control line EM′ may serve to maintain relatively constant voltage at the first common node N3 (Refer to FIG. 18). Accordingly, a leakage current of the third transistor T3 having the dual gate structure may be reduced, and low frequency characteristics of the display device may be relatively improved.

The fourth transistor T4, the second compensation capacitor CN′, and the second compensation voltage line C-GI included in the pixel PXe may be substantially same as the fourth transistor T4, the second compensation capacitor CN′, and the second compensation voltage line C-GI described with reference to FIG. 9.

FIG. 24 is a plan view illustrating an active layer ATVa, a first conductive layer C1b, and a second conductive layer C2c included in the pixel PXe of FIG. 23.

Referring to FIG. 24, the pixel PXe may include the active layer ATVa, the first conductive layer C1b, and the second conductive layer C2c.

The active layer ATVa included in the pixel PXe may be substantially same as the active layer ATVa described with reference to FIG. 3 and FIG. 4.

The first conductive layer C1b included in the pixel PXe may be substantially same as the first conductive layer C1b described with reference to FIG. 19. For example, the first conductive layer C1b may include the light emitting control line EM′ to which the light emitting control voltage is provided.

The second conductive layer C2c included in the pixel PXe may be substantially same as the second conductive layer C2c described with reference to FIG. 15. For example, the second conductive layer C2c may include a first compensation electrode CM overlapping the first common area A1 of the active layer ATVa to define the first compensation capacitor CN, and the second compensation electrode CM′ overlapping the second common area A2 of the active layer ATVa to define the second compensation capacitor CN′.

FIG. 25 is a plan view illustrating the active layer ATVa, the first conductive layer C1b, the second conductive layer C2c, and a third conductive layer C3e included in the pixel PXe.

Referring to FIG. 25, the third conductive layer C3e may be located on the second conductive layer C2c. An insulation layer may be located between the third conductive layer C3e and the second conductive layer C2c. The third conductive layer C3e may include a conductive material.

The third conductive layer C3e may include a first bridge electrode BR1, a second bridge electrode BR2, a third bridge electrode BR3, a fourth bridge electrode BR4, a fifth bridge electrode BR5, a first gate voltage line GW, a second gate voltage line GC, a third gate voltage line GI, a connection electrode CC, the second compensation voltage line C-GI, a first horizontal power voltage line ELVDD_H, a horizontal light emitting initialization voltage line VAINT_H, and a bias voltage line VIBAS.

The first bridge electrode BR1, the second bridge electrode BR2, the third bridge electrode BR3, the fourth bridge electrode BR4, the fifth bridge electrode BR5, the first gate voltage line GW, the second gate voltage line GC, the third gate voltage line GI, the first horizontal power voltage line ELVDD_H, the horizontal light emitting initialization voltage line VAINT_H, and the bias voltage line VIBAS included in the third conductive layer C3e may be substantially same as the first bridge electrode BR1, the second bridge electrode BR2, the third bridge electrode BR3, the fourth bridge electrode BR4, the fifth bridge electrode BR5, the first gate voltage line GW, the second gate voltage line GC, the third gate voltage line GI, the first horizontal power voltage line ELVDD_H, the horizontal light emitting initialization voltage line VAINT_H, and the bias voltage line VIBAS described with reference to FIG. 6.

The connection electrode CC included in the third conductive layer C3e may be substantially same as the connection electrode CC described with reference to FIG. 21 and FIG. 22. That is, the connection electrode CC may be connected to the first compensation electrode CM and the light emitting control line EM′, and accordingly, the light emitting control voltage provided by the light emitting control line EM′ may be provided to the first compensation electrode CM through the connection electrode CC.

The second compensation voltage line C-GI included in the third conductive layer C3e may be substantially same as the second compensation voltage line C-GI described with reference to FIG. 12 and FIG. 13. That is, the second compensation voltage line C-GI may be connected to the second compensation electrode CM′, and accordingly, the second compensation voltage provided by the second compensation voltage line C-GI may be provided to the second compensation electrode CM′.

According to some embodiments, the fourth conductive layer C4a described with reference to FIG. 8 may be located on the third conductive layer C3e. In this case, an insulation layer may be located between the fourth conductive layer C4a and the third conductive layer C3e.

The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and characteristics of embodiments according to the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims, and their equivalents.

DISPLAY DEVICE

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CPC

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