Patent Application
20230206874
This application claims priority to the Korean Patent Application No. 10-2021-0186121 filed on Dec. 23, 2021 in the Republic of Korea, the entire contents of which are hereby expressly incorporated by reference into the present application.
The present disclosure relates to a display device.
Display devices include liquid crystal display (LCD) devices and light emitting display devices. Each of such display devices can include a display panel which displays an image.
The display devices include a gate driver which includes stages for outputting gate signals to gate lines included in the display panel.
A period, where the stage outputs a gate off signal, can be longer than a period where a gate pulse is output. While the gate off signal is being output, a gate clock for outputting the gate pulse cam be continuously supplied to the stage, and thus, ripple affecting the driving of the stage can occur.
In order to remove an adverse effect of ripple, a state of the related art can include a ripple removal transistor.
However, it can be difficult to normally remove ripple when the ripple removal transistor is degraded. Further, a dummy transistor needs to be added for determining the degree of degradation of the ripple removal transistor, and a voltage supplied to the ripple removal transistor needs to vary based on a degradation in the ripple removal transistor. As a result, various additional elements may be needed.
Accordingly, the present disclosure is directed to providing a display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An aspect of the present disclosure is directed to providing a display device in which a left ripple transistor provided in a left stage to remove ripple occurring in a Q node of the left stage and a right ripple transistor provided in a right stage to remove ripple occurring in a Q node of the right stage perform an on operation and an off operation repeatedly and simultaneously.
Additional advantages and features of the disclosure will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or can be learned from practice of the disclosure. The objectives and other advantages of the disclosure can be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, there is provided a display device including a display panel including a display area and a non-display area surrounding the display area and including gate lines, a left gate driver provided in a first non-display area of the non-display area to output left gate pulses and left gate off signals to the gate lines, and a right gate driver provided in a second non-display area of the non-display area to output right gate pulses and right gate off signals to the gate lines, wherein the left gate driver includes an nth left stage outputting an nth left gate pulse and the right gate driver includes an nth right stage outputting an nth right gate pulse (where n is a natural number), outputs of the nth left gate pulse and the nth right gate pulse are controlled by Q nodes respectively included in the nth left stage and the nth right stage, and an nth left ripple transistor provided in the nth left stage to remove ripple occurring in an nth left Q node of the nth left stage and an nth right ripple transistor provided in the nth right stage to remove ripple occurring in an nth right Q node of the nth right stage perform an on operation and an off operation repeatedly.
It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain the principle of the disclosure. In the drawings:
Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Further, the present disclosure is only defined by scopes of claims.
A shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing embodiments of the present disclosure are merely an example, and thus, the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted. When “comprise,” “have,” and “include” described in the present specification are used, another part can be added unless “only” is used. The terms of a singular form can include plural forms unless referred to the contrary.
In construing an element, the element is construed as including an error or tolerance range although there is no explicit description of such an error or tolerance range.
In describing a position relationship, for example, when a position relation between two parts is described as, for example, “on,” “over,” “under,” and “next,” one or more other parts can be disposed between the two parts unless a more limiting term, such as “just” or “direct(ly)” is used.
In describing a time relationship, for example, when the temporal order is described as, for example, “after,” “subsequent,” “next,” and “before,” a case that is not continuous can be included unless a more limiting term, such as “just,” “immediate(ly),” or “direct(ly)” is used.
It will be understood that, although the terms “first,” “second,” etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.
In describing elements of the present disclosure, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc. can be used. These terms are intended to identify the corresponding elements from the other elements, and basis, order, or number of the corresponding elements should not be limited by these terms. The expression that an element is “connected,” “coupled,” or “adhered” to another element or layer the element or layer can not only be directly connected or adhered to another element or layer, but also be indirectly connected or adhered to another element or layer with one or more intervening elements or layers “disposed,” or “interposed” between the elements or layers, unless otherwise specified.
The term “at least one” should be understood as including any and all combinations of one or more of the associated listed items. For example, the meaning of “at least one of a first item, a second item, and a third item” denotes the combination of all items proposed from two or more of the first item, the second item, and the third item as well as the first item, the second item, or the third item.
Features of various embodiments of the present disclosure can be partially or overall coupled to or combined with each other, and can be variously inter-operated with each other and driven technically as those skilled in the art can sufficiently understand. The embodiments of the present disclosure can be carried out independently from each other, or can be carried out together in co-dependent relationship.
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Further, all the components of each display device according to all embodiments of the present disclosure are operatively coupled and configured.
The display device according to the present disclosure can configure various electronic devices. The electronic devices can include, for example, smartphones, tablet personal computers (PCs), televisions (TVs), and monitors.
The display device according to the present disclosure, as illustrated in
First, the display panel 100 can include the display area 120 and the non-display area 130. The gate lines GL1 to GLg, the data lines DL1 to DLd, and the pixels 110 can be provided in the display area 120. Accordingly, the display area 120 can display an image. Here, g and d can each be a natural number, e.g., positive integer. In particular, g may be an even number. The non-display area 130 can surround the display area 120.
The display panel 100 can be a liquid crystal display panel which includes the pixel 110 illustrated in
For example, when the display panel 100 is the liquid crystal display panel, as illustrated in
For example, when the display panel 100 is the light emitting display panel, as illustrated in
A structure of the pixel 110 of the liquid crystal display panel and a structure of the pixel 110 of the light emitting display panel are not limited to a structure illustrated in
For example, the display device according to the present disclosure can be an LCD device including the liquid crystal display panel or can be the light emitting display device including the light emitting display panel, but is not limited thereto and can be a display device including various types of display panels.
Hereinafter, for convenience of description, a display device including a light emitting display panel will be described as an example of the present disclosure.
The data driver 300 can be mounted on a chip on film attached on the display panel 100. In this case, the data driver 300 can be connected to the data lines DL1 to DLd included in the display panel 100 and the controller 400 mounted on a main substrate.
The data driver 300 can be directly equipped in the display panel 100, and then, can be connected to the controller 400 provided in the main substrate.
The data driver 300 can be implemented as one integrated circuit (IC) along with the controller 400. In this case, the IC can be mounted on the chip on film, or can be directly equipped in the display panel 100.
The controller 400 can realign input video data Ri, Gi, and Bi transferred from an external system by using a timing synchronization signal TSS transferred from the external system and can generate data control signals DCS which are to be supplied to the data driver 300 and gate control signals GCS which are to be supplied to the gate drivers 200a and 200b.
To this end, as illustrated in
The external system can perform a function of driving the controller 400 and an electronic device. For example, when the electronic device is a TV, the external system can receive various sound information, video information, and letter information over a communication network and can transfer the received video information to the controller 400. In this case, the image information can include input video data Ri, Gi, and Bi.
The power supply 500 can generate various powers and can supply the generated powers to the controller 400, the gate drivers 200a and 200b, the data driver 300, and the display panel 100.
Finally, the gate driver 200 can be implemented as an IC and can be provided in the non-display area 130. Alternatively, the gate driver 200 can be directly embedded in the non-display area 130 by using a gate in panel (GIP) type. When the GIP type is used, transistors configuring the gate driver 200 can be provided in the non-display area through the same process as transistors included in each pixel 110.
When the gate pulse generated by each of the gate drivers 200a and 200b is supplied to a gate of the switching transistor Tsw1 included in the pixel 110, the switching transistor Tsw1 can be turned on. When the switching transistor Tsw1 is turned on, a data voltage supplied through a data line DL can be supplied to the pixel 110. When a gate off signal generated by each of the gate drivers 200a and 200b is supplied to the switching transistor Tsw1, the switching transistor Tsw1 can be turned off. When the switching transistor Tsw1 is turned off, data voltage Vdata may not be supplied to the pixel 100 any longer. The gate signal GS supplied to the gate line GL can include a gate pulse and a gate off signal.
In the present disclosure, as illustrated in
One gate driver 200a can be provided in a first non-display area 131, provided at a left side of the gate line GL, of the non-display area 130. In the following description, a gate driver provided in the first non-display area 131 can be simply referred to as a left gate driver 200a.
The other gate driver 200b can be provided in a second non-display area 132, provided at a right side of the gate line GL, of the non-display area 130. In the following description, a gate driver provided in the second non-display area 132 can be simply referred to as a right gate driver 200b.
In this case, the second non-display area 132 can be provided to face the first non-display area 131, but is not limited thereto. For example, positions of the first non-display area 131 and the second non-display area 132 can be variously changed based on a type where a gate line is provided. Further, in the following description, a left side and a right side can denote one side and the other side of a gate line, and thus, are not limited to a left side and a right side used for expressing a point of the compass.
Detailed structures and functions of the left gate driver 200a and the right gate driver 200b will be described below with reference to
In
As described above, the display panel 100 can include the display area 120 and the non-display area 130 surrounding the display area 120, and the gate lines GL1 to GLg can be included in the display panel 100.
The left gate driver 200a can be provided in the first non-display area 131 of the non-display area 130 and can output left gate pulses L_GP1 to L_GPg and left gate off signals L_Goff1 to L_Goffg to the gate lines GL1 to GLg. In
The right gate driver 200b can be provided in the second non-display area 132 of the non-display area 130 and can output right gate pulses R_GP1 to R_GPg and right gate off signals R_Goff1 to R_Goffg to the gate lines GL1 to GLg. In
At least one gate line can be further provided on the first gate line GL1 in the non-display area 130, and at least one gate line can be further provided on the gth gate line GLg in the non-display area 130. In
In this case, the left gate driver 200a and the right gate driver 200b can output gate pulses and gate off signals to dummy gate lines.
The left gate driver 200a can include first to gth left gate stages L_Stage 1 to L_Stage g. Each of the first to gth left gate stages L_Stage 1 to L_Stage g can output at least one gate pulse. In the following description, when all gate pulses should be described, the order of gate pulses is not needed, or it is not required to limit a gate driver which outputs a gate pulse, a gate pulse can be used as simple expression. When a generic name for all stages is needed or the order of gate pulses is not needed, a stage can be used as simple expression. When a generic name for all gate off signals is needed or the order of gate off signals is not needed, a gate off signal can be used as simple expression. Further, in the following description, a stage which outputs an nth left gate pulse L_GPn and an nth left gate off signal L_Goffn can be referred to as an nth left stage L_Stage n. Here, n can be a natural number which is less than or equal to g. For example, n can be a positive integer.
The right gate driver 200b can include first to gth right gate stages R_Stage 1 to R_Stage g. Each of the first to gth right gate stages R_Stage 1 to R_Stage g can output at least one gate pulse. In the following description, a stage which outputs an nth right gate pulse R_GPn and an nth right gate off signal R_Goffn can be referred to as an nth right stage R_Stage n.
Hereinafter, the present disclosure will be described with reference to the nth left stage L_Stage n and the nth right stage R_Stage n. The following descriptions of the nth left stage L_Stage n and the nth right stage R_Stage n can be identically applied to the other stages.
Each of the stages can include a plurality of transistors, and gate control signals GCS can be supplied to each of the stages. Each of the stages can generate gate pulses by using various kinds of signals and voltages and can sequentially supply the gate pulses to the gate lines GL1 to GLg.
To this end, as illustrated in
The nth right stage R_Stage n can include an nth right signal generator 210b which includes an nth right ripple transistor R_Trpn and an nth right signal output unit 220b which outputs an nth right gate off signal R_Goffn and an nth right gate pulse R_GPn, based on an nth right control signal generated by the nth right signal generator 210b.
In this case, the nth left gate off signal L_Goffn and nth right gate off signal R_Goffn can be alternately output to an nth gate line GLn.
The nth left signal output unit 220a can include an nth left pull-up transistor L_Tun which outputs the nth left gate pulse L_GPn and an nth left pull-down transistor L_Tdn which outputs the nth left gate off signal L_Goffn. A capacitor C for stabilizing an output can be provided between an output terminal and a gate of the nth left pull-up transistor L_Tun.
The nth left signal generator 210a can generate signals for driving the nth left pull-up transistor L_Tun and the nth left pull-down transistor L_Tdn.
The nth right signal output unit 220b can include an nth right pull-up transistor R_Tun which outputs the nth right gate pulse R_GPn and an nth right pull-down transistor R_Tdn which outputs the nth right gate off signal R_Goffn. A capacitor C for stabilizing an output can be provided between an output terminal and a gate of the nth right pull-up transistor R_Tun.
The nth right signal generator 210b can generate signals for driving the nth right pull-up transistor R_Tun and the nth right pull-down transistor R_Tdn.
First, the nth left signal generator 210a can include a plurality of transistors. In
A start transistor Tst can be turned on by a start signal Vst and can supply a high voltage VD to the left signal output unit 220a through an nth left Q node L_Qn. The high voltage VD passing through the start transistor Tst can be shifted to a voltage, which is lower than the high voltage, by the inverter IN and can be transferred to an nth left Qb node L_Qbn.
When the start transistor Tst is turned on and a reset transistor Trs is turned on by a reset signal Rest, a low voltage GVSS can be supplied to the nth left Qb node L_Qbn through the reset transistor Trs. The low voltage GVSS can be shifted to a voltage, which is higher than the low voltage, by the inverter IN and can be supplied to the nth left Qb node L_Qbn. The inverter IN can be formed in various structures including at least one transistor so as to perform a function described above.
A first terminal of the nth left ripple transistor L_Trpn can be connected to the nth left Q node L_Qn, a second terminal of the nth left ripple transistor L_Trpn can be connected to a first voltage terminal, and a gate of the nth left ripple transistor L_Trpn can be connected to a gate of the nth left pull-down transistor L_Tdn which controls an output of the nth left gate off signal L_Goffn.
Here, the first voltage terminal can be supplied with the low voltage GVSS. For example, the first voltage terminal can be supplied with the low voltage GVSS for turning off the nth left pull-up transistor L_Tun.
A gate of the nth left ripple transistor L_Trpn and a gate of the nth left pull-down transistor L_Tdn can be connected to a terminal which is supplied with an nth left ripple clock L_DCLK(n). Accordingly, the gate of the nth left ripple transistor L_Trpn and the gate of the nth left pull-down transistor L_Tdn can be supplied with the nth left ripple clock L_DCLK(n).
Second, the nth right signal generator 210b can include a plurality of transistors. In
A start transistor Tst can be turned on by the start signal Vst and can supply the high voltage VD to the right signal output unit 220b through an nth right Q node R_Qn.
When the start transistor Tst is turned off and a reset transistor Trs is turned on by the reset signal Rest, the low voltage GVSS can be supplied to the nth right Q node R_Qn through the reset transistor Trs. The inverter IN can be formed in various structures including at least one transistor.
A first terminal of the nth right ripple transistor R_Trpn can be connected to the nth right Q node R_Qn, a second terminal of the nth right ripple transistor R_Trpn can be connected to the first voltage terminal, and a gate of the nth right ripple transistor R_Trpn can be connected to a terminal which is supplied with an nth right ripple clock R_DCLK(n).
Therefore, the nth right ripple clock R_DCLK(n) can be supplied to the gate of the nth right ripple transistor R_Trpn.
As described above, the gate of the nth left ripple transistor L_Trpn can be connected to a gate of the nth left pull-down transistor L_Tdn which controls an output of the nth left gate off signal L_Goffn.
However, the gate of the nth right ripple transistor R_Trpn may not be connected to the gate of the nth right pull-down transistor R_Tdn which controls an output of the nth right gate off signal R_Goffn. The gate of the nth right pull-down transistor R_Tdn can be connected to a gate of an n+1th right ripple transistor included in a stage (for example, an n+1th right stage) next to an nth right stage R_Stage n. In this case, the gate of the nth right ripple transistor R_Trpn can be connected to a gate of an n−1th right pull-down transistor included in a previous stage (for example, an n−1th right stage) with respect to the nth right stage R_Stage n.
To provide an additional description, outputs of the nth left gate off signal L_Goffn and the nth right gate off signal R_Goffn can be controlled by Qb nodes included in the nth left stage L_Stage n and the nth right stage R_Stage n. In this case, a gate of an nth left ripple transistor L_Trpn and an nth left Qb node L_Qbn included in the nth left stage L_Stage n can be connected to each other, and an nth right Qb node R_Qbn included in the nth right stage R_Stage n can be connected to a gate of an n+1th right ripple transistor included in an n+1th right stage.
Third, the nth left signal output unit 220a can include an nth left pull-up transistor L_Tun which outputs an nth left gate pulse L_GPn, and a gate of the nth left pull-up transistor L_Tun can be connected to an nth left Q node L_Qn.
The nth left signal output unit 220a can include an nth left pull-down transistor L_Tdn which outputs an nth left gate off signal L_Goffn, and a gate of the nth left pull-down transistor L_Tdn can be connected to a gate of an nth left ripple transistor L_Trpn.
Fourth, the nth right signal output unit 220b can include an nth right pull-up transistor R_Tun which outputs an nth right gate pulse R_GPn, and a gate of the nth right pull-up transistor R_Tun can be connected to an nth right Q node R_Qn.
The nth right signal output unit 220b can include an nth right pull-down transistor R_Tdn which outputs an nth right gate off signal R_Goffn, and a gate of the nth right pull-down transistor R_Tdn can be connected to a gate of an n+1th right ripple transistor included in a stage (for example, an n+1th right stage) next to the nth right stage R_Stage n.
First, the n−1th to n+1th left stages L_Stage n−1 to L_Stage n+1 illustrated in
For example, the inverter IN of the nth left stage L_Stage n illustrated in
A first terminal and a gate of the first transistor T1 can be connected to a terminal to which an nth left ripple clock L_DCLK(n) is input, and a second terminal thereof can be connected to a first terminal of the second transistor T2.
The first terminal of the second transistor T2 can be connected to the second terminal of the first transistor T1, a gate thereof can be connected to an nth left Q node L_Qn, and a second terminal thereof can be connected to a terminal which is supplied with the low voltage GVSS.
A first terminal of the third transistor T3 can be connected to the terminal to which the nth left ripple clock L_DCLK(n) is input, a second terminal thereof can be connected to a first terminal of the fourth transistor T4, and a gate thereof can be connected to the second terminal of the first transistor T1 and the first terminal of the second transistor T2.
The first terminal of the fourth transistor T4 can be connected to the second terminal of the third transistor T3, a gate thereof can be connected to the nth left Q node L_Qn, and a second terminal thereof can be connected to the terminal which is supplied with the low voltage GVSS.
The inverter IN of the nth left stage L_Stage n can be implemented as various types, in addition to a structure described above.
A first terminal and a gate of a start transistor Tst of the nth left stage L_Stage n can be supplied with an n−1th left gate signal L_GS(n−1) output from a previous stage (for example, the n−1th left stage L_Stage n−1).
An n+1th left gate signal L_GS(n+1) output from a next stage (for example, the n+1th left stage L_Stage n+1) can be input to a gate of a reset transistor Trs of the nth left stage L_Stage n.
A structure and a feature of each of the other elements of the nth left stage L_Stage n, except differences described above, can be the same as a structure and a feature of the nth left stage described above with reference to
Second, the n−1th to n+1th right stages R_Stage n−1 to R_Stage n+1 illustrated in
For example, the inverter IN of the nth right stage R_Stage n illustrated in
A first terminal and a gate of the first transistor T1 can be connected to a terminal to which an nth right ripple clock R_DCLK(n) is input, and a second terminal thereof can be connected to a first terminal of the second transistor T2.
The first terminal of the second transistor T2 can be connected to the second terminal of the first transistor T1, a gate thereof can be connected to an nth right Q node R_Qn, and a second terminal thereof can be connected to a terminal which is supplied with the low voltage GVSS.
A first terminal of the third transistor T3 can be connected to the terminal to which the nth right ripple clock R_DCLK(n) is input, a second terminal thereof can be connected to a first terminal of the fourth transistor T4, and a gate thereof can be connected to the second terminal of the first transistor T1 and the first terminal of the second transistor T2.
The first terminal of the fourth transistor T4 can be connected to the second terminal of the third transistor T3, a gate thereof can be connected to the nth right Q node R_Qn, and a second terminal thereof can be connected to the terminal which is supplied with the low voltage GVSS.
The inverter IN of the nth right stage R_Stage n can be implemented as various types, in addition to a structure described above.
In this case, an arrangement structure of the first to fourth transistors T1 to T4 included in the inverter IN of the nth right stage R_Stage n can be the same as an arrangement structure of the first to fourth transistors T1 to T4 included in the inverter IN of the nth left stage L_Stage n.
A first terminal and a gate of a start transistor Tst of the nth right stage R_Stage n can be supplied with an n−1th right gate signal R_GS(n−1) output from a previous stage (for example, the n−1th right stage R_Stage n−1).
An n+1th right gate signal R_GS(n+1) output from a next stage (for example, the n+1th right stage R_Stage n+1) can be input to a gate of a reset transistor Trs of the nth right stage R_Stage n.
A structure and a feature of each of the other elements of the nth right stage R_Stage n, except differences described above, can be the same as a structure and a feature of the nth right stage described above with reference to
Hereinafter, a driving method of a display device according to an embodiment of the present disclosure will be described with reference to
First, in a first process A, an n−1th gate signal GSn−1 having a high level can be input as a start signal of each of the nth left stage L_Stage n and the nth right stage R_Stage n.
Therefore, an nth left Q node L_Qn and an nth right Q node R_Qn can be charged.
In a second process B, an nth left gate clock L_SCCLK(n) and an nth right gate clock R_SCCLK(n) can have a high level. For example, a phase of the nth left gate clock L_SCCLK(n) can be the same as that of the nth right gate clock R_SCCLK(n). Therefore, in
Therefore, a level of the nth left Q node L_Qn and the nth left gate clock L_SCCLK(n) can be boosted, and thus, the nth left pull-up transistor L_Tun can be turned on.
Accordingly, an nth gate pulse GPn can be output to the nth gate line GLn through the nth left pull-up transistor L_Tun.
In this case, the nth gate pulse GPn can be output from the nth right stage R_Stage n, based on the same method.
Subsequently, in a third process C, an n+1th gate signal GSn+1 having a high level can be input as a reset signal of each of the nth left stage L_Stage n and the nth right stage R_Stage n. Accordingly, the nth left pull-up transistor L_Tun can be turned off. In this case, the nth right pull-up transistor R_Tun can also be turned off.
Subsequently, in the third process C, an n+1th right ripple clock R_DCLK(n+1) having a high level can be input from an n+1th right stage R_Stage n+1 to an nth right Qb node R_Qbn.
Accordingly, an n_1th right gate off signal R_Goffn_1st can be output from the nth right stage R_Stage n to the nth gate line GLn. The n_1th right gate off signal R_Goffn_1st can configure an nth right gate off signal R_Goffn.
In this case, because the nth left ripple clock L_DCLK(n) having a low level is input to the nth right stage R_Stage n, a gate off signal may not be output from the nth right stage R_Stage n.
Subsequently, in a fourth process D, the nth left ripple clock L_DCLK(n) having a high level can be input to an nth left Qb node L_Qbn.
Accordingly, an n_2th left gate off signal L_Goffn_2nd can be output from the nth left stage L_Stage n to the nth gate line GLn. The n_2th left gate off signal L_Goffn_2nd can configure an nth left gate off signal L_Goffn.
In this case, a low level can be continuously supplied to an nth left Q node L_Qn.
However, the nth left gate clock L_SCCLK(n) having a high level can be input to the first terminal of the nth left pull-up transistor L_Tun. Accordingly, ripple can occur in the nth left Q node due to the nth left gate clock L_SCCLK(n) having a high level.
In this case, because the nth left ripple clock L_DCLK(n) having a high level is supplied to the nth left Qb node L_Qbn, the nth left ripple transistor L_Trpn can be turned on. Accordingly, ripple occurring in the nth left Q node L_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the nth left ripple transistor L_Trpn.
In this case, the nth right ripple transistor R_Trpn can be driven based on the same method as the nth left ripple transistor L_Trpn. Accordingly, ripple occurring in the nth right Q node R_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the nth right ripple transistor R_Trpn.
For example, because a phase of the nth left ripple clock L_DCLK(n) is the same as that of the nth right ripple clock R_DCLK(n) and the phase of the nth left gate clock L_SCCLK(n) is the same as that of the nth right gate clock R_SCCLK(n), as described above, the same operation can be performed by the nth left stage L_Stage n and the nth right stage R_Stage n.
Subsequently, in a fifth process E, the n+1th right ripple clock R_DCLK(n+1) having a high level can be input from the n+1th right stage R_Stage n+1 to the nth right Qb node R_Qbn.
Therefore, an n_3th right gate off signal R_Goffn_3rd can be output from the nth right stage R_Stage n to the nth gate line GLn. The n_3th right gate off signal R_Goffn_3rd can configure the nth right gate off signal R_Goffn.
Finally, in a sixth process F, the nth left ripple clock L_DCLK(n) having a high level can be input to the nth left Qb node L_Qbn.
Therefore, an n_4th left gate off signal L_Goffn_4th can be output from the nth left stage L_Stage n to the nth gate line GLn. The n_4th left gate off signal L_Goffn_4th can configure the nth left gate off signal L_Goffn.
In this case, a low level can be supplied to the nth left Q node L_Qn. However, the nth left gate clock L_SCCLK(n) having a high level can be input to a first terminal of the nth left pull-up transistor L_Tun. Accordingly, ripple can occur in the nth left Q node due to the nth left gate clock L_SCCLK(n) having a high level.
In this case, because the nth left ripple clock L_DCLK(n) having a high level is supplied to the nth left Qb node L_Qbn, the nth left ripple transistor L_Trpn can be turned on. Therefore, ripple occurring in the nth left Q node L_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the nth left ripple transistor L_Trpn.
In this case, the nth right ripple transistor R_Trpn can be driven based on the same method as the nth left ripple transistor L_Trpn. Accordingly, ripple occurring in the nth right Q node R_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the nth right ripple transistor R_Trpn.
The third to sixth processes C to F can be repeated until another nth gate pulse is output from the nth left stage L_Stage n and the nth right stage R_Stage n, and thus, the nth gate off signal can be continuously output to the nth gate line GLn.
For example, through the processes described above, nth gate pulses GPn can be output from the nth left stage L_Stage n and the nth right stage R_Stage n to the nth gate line GLn.
Moreover, as illustrated in
In this case, the n_1th right gate off signal R_Goffn_1st, the n_3th right gate off signal R_Goffn_3rd, the n_2th left gate off signal L_Goffn_2nd, and the n_4th left gate off signal L_Goffn_4th can configure the nth gate off signal Goffn supplied to the nth gate line GLn.
In this case, in
For example, the nth left stage L_Stage n and the nth right stage R_Stage n can sequentially output the nth gate off signal Goffn to the nth gate line GLn. Accordingly, the nth gate off signal Goffn can be continuously output to the nth gate line GLn.
In the present disclosure, outputs of the nth left gate pulse L_GPn and the nth right gate pulse R_GPn can be controlled by the Q nodes included in the nth left stage L_Stage n and the nth right stage R_Stage n.
In this case, the nth left ripple transistor L_Trpn which is provided in the nth left stage L_Stage n to remove ripple occurring in the nth left Q node L_Qn of the nth left stage L_Stage n and the nth right ripple transistor R_Trpn which is provided in the nth right stage R_Stage n to remove ripple occurring in the nth right Q node R_Qn of the nth right stage R_Stage n can simultaneously and continuously perform an on operation and an off operation.
Because each of the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn repeats a turn-on operation and a turn-off operation, the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn may not be degraded, and a speed at which the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn are degraded can be reduced. Accordingly, the reliability of the display device according to the present disclosure including the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn can be enhanced.
Hereinafter, features of the present disclosure will be described.
First, in the present disclosure, a phase of the nth left gate clock L_SCCLK(n) supplied to the nth left stage L_Stage n to generate the nth left gate pulse L_GPn can be the same as that of the nth left ripple clock L_DCLK(n) supplied for driving the nth left ripple transistor L_Trpn, and a phase of the nth right gate clock R_SCCLK(n) supplied to the nth right stage R_Stage n to generate the nth right gate pulse R_GPn can be the same as that of the nth right ripple clock R_DCLK(n) supplied for driving the nth right ripple transistor R_Trpn.
For example, the nth left ripple transistor L_Trpn can be turned on by the nth left gate clock L_SCCLK(n) having a high level only when ripple occurs in the nth left Q node L_Qn, and the nth right ripple transistor R_Trpn can be turned on by the nth right gate clock R_SCCLK(n) having a high level only when ripple occurs in the nth right Q node R_Qn. Accordingly, as described above, a speed at which the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn are degraded can be reduced.
Second, a phase of the nth left ripple clock L_DCLK(n) supplied for driving the nth left ripple transistor L_Trpn can be the same as that of the nth right ripple clock R_DCLK(n) supplied for driving the nth right ripple transistor R_Trpn.
For example, the nth left ripple clock L_DCLK(n) can be supplied to a gate of the nth left ripple transistor L_Trpn, the nth right ripple clock R_DCLK(n) can be supplied to a gate of the nth right ripple transistor R_Trpn, and a phase of the nth left ripple clock L_DCLK(n) can be the same as that of the nth right ripple transistor R_Trpn.
Therefore, the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn can simultaneously perform an on operation and an off operation.
Third, when the nth left ripple transistor L_Trpn is turned on, the nth left gate off signal L_Goffn can be output from the nth left stage L_Stage n to the nth gate line GLn, and when the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn are turned off, the nth right gate off signal R_Goffn can be output from the nth right stage R_Stage n to the nth gate line GLn.
For example, the nth left gate off signal L_Goffn output from the nth left stage L_Stage n and the nth right gate off signal R_Goffn output from the nth right stage R_Stage n can be alternately output to the nth gate line GLn.
To provide an additional description, in the present disclosure, because a gate off signal is alternately output from two stages which are provided at both sides of a gate line, the gate off signal can be continuously supplied to the gate line. Therefore, the gate line may not be floated, and thus, switching transistors connected to the gate line may not be abnormally driven. Accordingly, the reliability of a display device can be enhanced.
First, a structure of an nth left signal generator 210a of the nth left stage L_Stage n illustrated in
Second, the nth left signal output unit 220a illustrated in
However, an nth left signal output unit 220a illustrated in
In describing the nth left signal output unit 220a illustrated in
A gate of the n_2th left pull-up transistor L_Tun_2 can also be connected to the nth left Q node.
Third, the nth left signal output unit 220a illustrated in
However, the nth left signal output unit 220a illustrated in
In describing the nth left signal output unit 220a illustrated in
A gate of the n_2th left pull-down transistor L_Tdn_2 can also be connected to the nth left Qb node L_Qbn. Therefore, the gate of the n_2th left pull-down transistor L_Tdn_2 can also be connected to a gate of an nth left ripple transistor L_Trpn.
Fourth, a structure of an nth right signal generator 210b of the nth right stage R_Stage n illustrated in
Fifth, the nth right signal output unit 220b illustrated in
However, the nth right signal output unit 220b illustrated in
In describing the nth right signal output unit 220b illustrated in
A gate of the n_2th right pull-up transistor R_Tun_2 can also be connected to the nth right Q node R_Qn.
Sixth, the nth right signal output unit 220b illustrated in
However, the nth right signal output unit 220b illustrated in
In describing the nth right signal output unit 220b illustrated in
A gate of the n_2th right pull-down transistor R_Tdn_2 can be connected to a gate of an n−1th right ripple transistor R_Trpn−1 included in an n−1th right stage R_Stage n−1.
For example, the nth left stage L_Stage n and the nth right stage R_Stage n illustrated in
Hereinafter, a driving method of a display device according to an embodiment of the present disclosure including the stages illustrated in
First, in a first process H, an n−1th gate signal GSn−1 having a high level can be input as a start signal of each of the nth left stage L_Stage n and the nth right stage R_Stage n.
Therefore, an nth left Q node L_Qn and an nth right Q node R_Qn can be charged.
In a second process I, an nth left gate clock L_SCCLK(n) and an n+1th left gate clock L_SCCLK(n+1) can be sequentially shifted to a high level, and an nth right gate clock R_SCCLK(n) and an n+1th right gate clock R_SCCLK(n+1) can be sequentially shifted to a high level. For example, a phase of the nth left gate clock L_SCCLK(n) can be the same as that of the nth right gate clock R_SCCLK(n), and a phase of the n+1th left gate clock L_SCCLK(n+1) can be the same as that of the n+1th right gate clock R_SCCLK(n+1). Therefore, in
Therefore, a level of the nth left Q node L_Qn can be boosted along with the nth left gate clock L_SCCLK(n) and the n+1th left gate clock L_SCCLK(n+1), and thus, the n_1th left pull-up transistor L_Tun_1 and the n_2th left pull-up transistor L_Tun_2 can be turned on.
Accordingly, a 2n−1th gate pulse GP2n−1 and an 2nth gate pulse GP2n can be sequentially output to the 2n−1th gate line GL2n−1 and the 2nth gate line GL2n through the nth left pull-up transistor L_Tun.
In this case, the 2n−1th gate pulse GP2n−1 and the 2nth gate pulse GP2n can be output from the nth right stage R_Stage n, based on the same method.
Subsequently, in a third process J, an n+1th gate signal GSn+1 having a high level can be input as a reset signal of each of the nth left stage L_Stage n and the nth right stage R_Stage n. Accordingly, the n_1th left pull-up transistor L_Tun_1 and the n_2th left pull-up transistor L_Tun_2 can be turned off.
In this case, the n_1th right pull-up transistor R_Tun_1 and the n_2th right pull-up transistor R_Tun_2 can also be turned off.
Subsequently, in the third process J, an n+1th right ripple clock R_DCLK(n+1) having a high level can be input from an n+1th right stage R_Stage n+1 to an nth right Qb node R_Qbn. Therefore, a 2n-1_1th right gate off signal R_Goff2n−1_1st can be output from the nth right stage R_Stage n to a 2n−1th gate line GL2n−1. The 2n−1_1th right gate off signal R_Goff2n-1_1st can configure a 2n−1th right gate off signal.
In this case, an n−1t right ripple clock R_DCLK(n−1) having a high level can be input from the n−1th right stage R_Stage n−1 to an n_2th right Qb node R_Qbn_2. Therefore, a 2n_1th right gate off signal R_Goff2n_1st can be output from the nth right stage R_Stage n to the 2nth gate line GL2n. The 2n_1th right gate off signal R_Goff2n_1st can configure a 2nth right gate off signal.
In this case, because the nth left ripple clock L_DCLK(n) having a low level is supplied to the nth left stage R_Stage n, a gate off signal may not be output from the nth left stage R_Stage n.
Subsequently, in a fourth process K, the nth left ripple clock L_DCLK(n) having a high level can be input to the nth left Qb node L_Qbn. Therefore, a 2n−1_2th left gate off signal L_Goff2n−1_2nd can be output from the nth left stage R_Stage n to the 2n−1th gate line GL2n−1. The 2n−1_2th left gate off signal L_Goff2n−1_2nd can configure a 2n−1th left gate off signal.
In this case, a 2n_2th left gate off signal L_Goff2n_2nd can be output from the nth left stage R_Stage n to the 2nth gate line GL2n. The 2n_2th left gate off signal L_Goff2n_2nd can configure a 2nth left gate off signal.
In this case, a low level can be continuously supplied to the nth left Q node L_Qn. However, the nth left gate clock L_SCCLK(n) and the n+1th left gate clock L_SCCLK(n+1) each having a high level can be sequentially input to a first terminal of the n_1th left pull-up transistor L_Tun_1 and the n_2th left pull-up transistor L_Tun_2. Accordingly, ripple can occur in the nth left Q node L_Qn due to the nth left gate clock L_SCCLK(n) and the n+1th left gate clock L_SCCLK(n+1) each having a high level.
In this case, because the nth left ripple clock L_DCLK(n) having a high level is supplied to the nth left Qb node L_Qbn, the nth left ripple transistor L_Trpn can be turned on. Therefore, ripple occurring in the nth left Q node L_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the nth left ripple transistor L_Trpn.
In this case, the nth right ripple transistor R_Trpn can be driven based on the same method as the nth left ripple transistor L_Trpn. Accordingly, ripple occurring in the nth right Q node R_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the nth right ripple transistor R_Trpn.
Subsequently, in a fifth process L, the n+1th right ripple clock R_DCLK(n+1) having a high level can be input from the n+1th right stage R_Stage n+1 to an n_1th right Qb node R_Qbn_1. Therefore, a 2n−1_3th right gate off signal R_Goff2n−1_3rd can be output from the nth right stage R_Stage n to the 2n−1th gate line GL2n−1. The 2n−1_3th right gate off signal R_Goff2n−1_3rd can configure a 2n−1th right gate off signal.
In this case, the n-1th right ripple clock R_DCLK(n−1) having a high level can be input from the n−1th right stage R_Stage n−1 to the n_2th right Qb node R_Qbn_2. Therefore, a 2n_3th right gate off signal R_Goff2n_3rd can be output from the nth right stage R_Stage n to the 2nth gate line GL2n. The 2n_3th right gate off signal R_Goff2n_3rd can configure a 2nth right gate off signal.
Finally, in a sixth process M, the nth left ripple clock L_DCLK(n) having a high level can be input to the nth left Qb node L_Qbn.
Therefore, a 2n−1_4th left gate off signal L_Goff2n−1_4th can be output from the nth left stage L_Stage n to the 2n−1th gate line GL2n−1. The 2n−1_4th left gate off signal L_Goff2n−1_4th can configure a 2n−1th gate off signal.
Moreover, a 2n_4th left gate off signal L_Goff2n_4th can be output from the nth left stage to the 2nth gate line GL2n. The 2n_4th left gate off signal L_Goff2n_4th can configure a 2nth left gate off signal.
In this case, a low level can be continuously supplied to the nth left Q node L_Qn. However, the nth left gate clock L_SCCLK(n) having a high level can be input to a first terminal of the n_1th left pull-up transistor L_Tun_1, and the n+1th left gate clock L_SCCLK(n+1) having a high level can be input to a first terminal of the n_2th left pull-up transistor L_Tun_2. Accordingly, ripple can occur in the nth left Q node L_Qn due to the nth left gate clock L_SCCLK(n) and the n+1th left gate clock L_SCCLK(n+1) each having a high level.
In this case, because the nth left ripple clock L_DCLK(n) having a high level is supplied to the nth left Qb node L_Qbn, the nth left ripple transistor L_Trpn can be turned on. Therefore, ripple occurring in the nth left Q node L_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the nth left ripple transistor L_Trpn.
In this case, the nth right ripple transistor R_Trpn can be driven based on the same method as the nth left ripple transistor L_Trpn. Accordingly, ripple occurring in the nth right Q node R_Qn can be discharged to a terminal, which is supplied with the low voltage GVSS, through the nth right ripple transistor R_Trpn.
The third to sixth processes J to M can be repeated until another nth gate pulse is output from the nth left stage L_Stage n and the nth right stage R_Stage n, and thus, the 2n−1th gate off signal can be continuously output to the 2n−1th gate line GL2n−1 and the 2nth gate off signal can be continuously output to the 2nth gate line GL2n.
In this case, the 2n−1_1th right gate off signal R_Goff2n−1_1st, the 2n−1_3th right gate off signal R_Goff2n−1_3rd, the 2n−1_2th left gate off signal L_Goff2n−1_2nd, and the 2n-1_4th left gate off signal L_Goff2n−1_4th can configure a 2n−1th gate off signal supplied to the 2n−1th gate line.
For example, the nth left stage L_Stage n and the nth right stage R_Stage n can sequentially output the 2n−1th gate off signal to the 2n−1th gate line GL2n−1. Accordingly, the 2n-1th gate off signal can be continuously output to the 2n−1th gate line GL2n−1.
In this case, the 2n_1th right gate off signal R_Goff2n_1st, the 2n_3th right gate off signal R_Goff2n_3rd, the 2n_2th left gate off signal L_Goff2n_2nd, and the 2n_4th left gate off signal L_Goff2n_4th can configure a 2nth gate off signal supplied to the 2nth gate line.
For example, the nth left stage L_Stage n and the nth right stage R_Stage n can sequentially output the 2nth gate off signal to the 2nth gate line GL2n. Accordingly, the 2nth gate off signal can be continuously output to the 2nth gate line GL2n.
In this case, the nth left ripple transistor L_Trpn which is provided in the nth left stage L_Stage n to remove ripple occurring in the nth left Q node L_Qn of the nth left stage L_Stage n and the nth right ripple transistor R_Trpn which is provided in the nth right stage R_Stage n to remove ripple occurring in the nth right Q node R_Qn of the nth right stage R_Stage n can simultaneously and continuously perform an on operation and an off operation.
Because each of the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn repeats a turn-on operation and a turn-off operation, the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn may not be degraded, and a speed at which the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn are degraded can be reduced. Accordingly, the reliability of the display device according to the present disclosure including the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn can be enhanced.
According to the present disclosure, a ripple transistor for removing ripple occurring in a Q node can repeat an on operation and an off operation, based on a ripple clock. Accordingly, a degradation in the ripple transistor can be prevented, and thus, the reliability of a display device can be enhanced.
According to the present disclosure, a phase of a gate clock supplied to a pull-up transistor connected to the Q node can be the same as that of a ripple clock for driving the ripple transistor. Therefore, even when the gate clock is supplied to the pull-up transistor, an abnormal signal caused by ripple may not be supplied to the Q node. Accordingly, the pull-up transistor connected to the Q node may not abnormally operate, thereby enhancing the reliability of a display device.
According to the present disclosure, because a gate off signal is alternately output from two stages which are provided at both sides of a gate line, the gate off signal can be continuously supplied to the gate line. Therefore, the gate line may not be floated, and thus, switching transistors connected to the gate line may not be abnormally driven. Accordingly, the reliability of a display device can be enhanced.
The above-described feature, structure, and effect of the present disclosure are included in at least one embodiment of the present disclosure, but are not limited to only one embodiment. Furthermore, the feature, structure, and effect described in at least one embodiment of the present disclosure can be implemented through combination or modification of other embodiments by those skilled in the art. Therefore, content associated with the combination and modification should be construed as being within the scope of the present disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the disclosures. Thus, it is intended that the present disclosure covers the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2021-0186121 | Dec 2021 | KR | national |
