Patent Application
20240371338
Embodiments according to the present disclosure relate to a display device.
In a display device, a method of converting a pixel signal into a pulse width modulation (PWM) signal and writing the signal to a latch may be used (refer to Patent Document 1).
However, power consumption may increase due to a load or the like on a wiring for transmitting a signal.
Therefore, the present disclosure provides a display device capable of suppressing the power consumption.
In order to solve the above-described problem, according to an aspect of the present disclosure, there is provided a display device including:
There may be further provided at least one count signal supply unit configured to supply the count signal to the PWM signal generation unit,
The logical operation unit may include:
The count signal supply unit may be electrically connected to the second input unit via a buffer unit.
The count signal supply unit may be a gray code counter.
The count signal supply unit may generate the count signal having a predetermined waveform on the basis of a reference clock, and supply the generated count signal to the PWM signal generation unit.
There may be further provided a pixel electrode that is provided in the pixel and a signal level conversion unit provided in the pixel and configured to convert a signal level of the PWM signal input to the pixel electrode.
There may be further provided a first chip and a second chip stacked with the first chip, and the first holding unit, the PWM signal generation unit, the signal level conversion unit, and the pixel electrode may be separated and disposed in the first chip and the second chip.
The signal level conversion unit may include four transistors connected in series between a first reference voltage node with a voltage level different from a high level or low level of the PWM signal and a second reference voltage node with either the high level or the low level,
There may be further provided a second holding unit provided in the pixel and configured to hold the PWM signal, and the signal level conversion unit may include a fifth transistor connected between the second holding unit and the pixel electrode, and a voltage booster configured to increase a voltage of the pixel electrode with capacitive coupling.
The PWM signal generation unit may be shared by a plurality of the pixels.
The image signal may include a plurality of bits,
The first holding unit may hold the image signal during a blanking period between a plurality of PWM periods corresponding to the PWM signal.
The first holding unit may hold the image signal having a subframe divided for each of a plurality of color components such that unit frames of the image signal are input in a predetermined order.
The image signal may include a plurality of bits,
A plurality of the bits of the image signal may be time-divided a plurality of times in accordance with a weight of the bits.
A plurality of the bits of the image signal may be time-divided such that weights of the bits are substantially equal.
A plurality of the bits of the image signal may be time-divided into a first half bit and a second half bit in one subframe,
There may be further provided a selector configured to select the first holding unit configured to hold the image signal of the first half bit and the first holding unit configured to hold the image signal of the second half bit.
The first holding unit may hold the image signal of the second half bit in a period between the count of the first half bit and the count of the second half bit.
There may be further provided a pixel electrode provided in the pixel,
Two pixel electrodes adjacent in a first direction may be driven on the basis of the same image signal, and the pixel electrodes may be driven such that two pixel electrodes driven on the basis of the same image signal are shifted by one pixel electrode in the first direction for each subframe of the same color component.
The first holding unit and the PWM signal generation unit may be shared by four pixel electrodes arranged in 2×2,
There may be further provided:
The predetermined region may be a pixel line which is one line of a plurality of the pixels arranged in a matrix.
The predetermined region may be a line division region divided in a direction along one line from a pixel line, the line division region being one line of a plurality of the pixels arranged in a matrix.
The drive stop unit may stop an input of the image signal to the first holding unit of the pixel in the predetermined region of the color component for which the flag is generated.
The count signal may be input to the PWM signal generation unit for each pixel line that is one line of a plurality of the pixels arranged in a matrix, and
Hereinafter, embodiments of a display device will be described with reference to the drawings. Although main components of the display device will be mainly described below, the display device may have a component or function that is not illustrated or described. The following description does not exclude components and functions that are not illustrated or described.
The display device 1 is, for example, an augmented reality (AR) display device. The AR display device is required to have low power consumption and a high frame rate. Furthermore, the display device 1 is, for example, a reflective display panel of liquid crystal on silicon (LCOS). However, the present disclosure is not limited thereto, and the display device 1 may be another display device such as a micro electro mechanical system (MEMS), an organic light emitting diode (OLED), a light emitting diode (LED), or the like.
As illustrated in
The display device 1 includes an interface circuit 10, a multiplexer 12, a timing controller 14, a clock generator 16, a set value storage register 18, an I-Squared-C (I2C) 20, a frame memory 22, a line buffer 24, a pixel region 26, a V driver 28, and a global counter 30.
The interface circuit 10 receives an image signal from the application processor 2.
The multiplexer 12 parallelizes the image signal received from the interface circuit 10 in order to decrease the operation frequency of a circuit and stores (writes) the image signal in the frame memory 22.
The timing controller 14 performs timing control on the display operation of the display device 1.
The clock generator 16 generates a reference clock on the basis of the timing controller 14. Furthermore, the clock generator 16 may have a gamma correction function to be described later. Furthermore, the clock generator 16 may be included in the global counter (count signal supply unit) 30.
The set value storage register 18 stores various types of information related to the operation of the display device 1.
The I2C 20 is a communication interface. The I2C 20 exchanges necessary information such as information to be read from and written to the set value storage register 18 with the application processor 2 outside the display device 1.
The frame memory 22 stores the image signal. The frame memory 22 is, for example, a storage unit such as a static random access memory (SRAM).
The line buffer 24 latches image signal data for each signal line. Furthermore, the line buffer 24 may perform processing necessary for the image signal data. The line buffer 24 outputs a signal based on the image signal data to the corresponding signal line.
In the pixel region 26, a plurality of pixels 50 is arranged in a matrix. Note that the details of each of the pixels 50 will be described with reference to
The V driver 28 generates and outputs a drive signal of each of the pixels 50 according to the driving of the signal line by the line buffer 24. Thus, each of the pixels 50 can be sequentially driven.
The global counter 30 is provided so as to be opposed to the V driver 28 across the pixel region 26. The global counter 30 generates a count signal and supplies the count signal to a PWM signal generation circuit 52 in the pixel 50. For example, at least one global counter 30 is provided in the display device 1. The global counter 30 creates an arbitrary count signal on the basis of a reference clock having a high frequency. Note that the details of the global counter 30 will be described with reference to
The pixel 50 includes a first switch SW1, a first holding unit 51, the PWM signal generation circuit (PWM signal generation unit) 52, a signal level conversion unit 53, a second holding unit 54, and a pixel electrode 55. Note that the configurations of the other pixels 50 in the pixel region 26 are also the same.
The first switch SW1 is connected to a front side of the first holding unit 51.
The first holding unit 51 is provided in the pixel 50 and holds an image signal. A plurality of the first holding units 51 is provided according to the bit depth of the image signal. In the example illustrated in
The PWM signal generation circuit 52 converts the digital image signal into one pulse PWM signal. The PWM signal generation circuit 52 is provided in the pixel 50, and generates a PWM signal corresponding to the image signal on the basis of an image signal held in the first holding unit 51 and a count signal Cx (x=0, 1, . . . , 6, 7). Furthermore, the PWM signal generation circuit 52 outputs and writes the PWM signal to the second holding unit 54.
The PWM signal generation circuit 52 includes a logical operation unit. The logical operation unit generates a PWM signal by performing a logical operation of the image signal held in the first holding unit 51 and the count signal.
The logical operation unit includes an exclusive-NOR circuit (EXNOR circuit 521) and an AND circuit (AND circuit 522). In a case where the image signal includes a plurality of bits, a plurality of the EXNOR circuits 521 is provided according to the bit depth. In the example illustrated in
Note that the global counter 30 may be electrically connected to the second input unit via a buffer circuit (not illustrated).
The output unit of each EXNOR circuit 521 is electrically connected to the input unit of the AND circuit 522. The signal output from the AND circuit 522 is a PWM signal output at a time corresponding to the image signal. The PWM width of the PWM signal is based on, for example, the count start timing of the global counter 30 and the rise timing of the output signal of the AND circuit 522 (refer to
The signal level conversion unit 53 is provided in the pixel 50 and converts a signal level (voltage level) of the PWM signal input to the pixel electrode 55. This is because, for example, in order to drive the liquid crystal, a higher voltage is required than in the case of driving a logic circuit.
The signal level conversion unit 53 includes a second switch SW2 and a third switch SW3. The second switch SW2 and the third switch SW3 are connected in series between a reference voltage node VCC and ground. The second switch SW2 is turned on or off upon receiving a reset signal. The third switch SW3 is turned on or off upon receiving the signal from the AND circuit 522.
The second holding unit 54 is provided in the pixel 50 and holds a PWM signal. For example, the second holding unit 54 is electrically connected to a node between the second switch SW2 and the third switch SW3. The width of the PWM signal is based on, for example, a period during which the voltage value of the reference voltage node VCC is held. The second holding unit 54 is, for example, a latch circuit.
The pixel electrode 55 is an electrode of an electro-optical element such as liquid crystal, which is provided in the pixel 50. The pixel electrode 55 receives one pulse PWM signal, that is, one pulse voltage signal. As a result, the pixel emits light.
Here, for example, when digital 8 bits are converted into 256 gradations, 256 signal transitions need to be performed. As the number of signal transitions increases, the number of charge/discharges of the circuit increases. That is, the power consumption is likely to be increased by the generation of the PWM signal. As will be described later, the first holding unit 51 and the PWM signal generation circuit 52 are disposed so as to be close to each other. Therefore, the power consumption can be suppressed, and the frame rate can be improved.
First, at time t1, a light source (Light) is turned off (turned off). The light source is, for example, a light source in a reflective LCOS.
Next, at time t2, the reset signal becomes High, and the second switch SW2 is turned on. Thus, one (voltage VCC) is written to the second holding unit 54, and the second holding unit 54 goes into a high state. Note that in the period during which the light source is turned off, the width of the PWM signal is not effective. The actual PWM width is a period during which the light source is in the ON state and the second holding unit 54 is in the high state.
Furthermore, during the reset, the image signal is written to the first holding unit 51. Thus, the first holding unit 51 holds the image signal.
Next, at time t3, the reset signal becomes Low, and the second switch SW2 is turned off. Furthermore, at time t3, the light source is turned on (emits light).
Furthermore, at time t3, the global counter 30 inputs the count signals C0 to C3 to the PWM signal generation circuit 52. Thus, the PWM signal generation circuit 52 compares the image signal with the count signal.
Next, at time t4, the AND circuit 522 of the PWM signal generation circuit 52 outputs one at a timing when the data of the image signal held in the first holding unit 51 and the value of the count signal all match. In the example illustrated in
Thus, the third switch SW3 is turned on. As a result, zero (ground voltage) is written to the second holding unit 54, and the second holding unit 54 goes into a low state.
In this manner, the PWM signal corresponding to the image signal is generated. In the PWM width period, when the second holding unit 54 is in the high state, the voltage of the pixel electrode 55 is also in the high state, and the pixel 50 is driven.
The display device 1 performs color sequential driving. The color sequential driving is a method of sequentially displaying images of color components of red, green, and blue in a time-division manner. The frame includes a plurality of subframes corresponding to respective colors. The subframes are displayed in a predetermined order. The subframes are displayed, for example, in the order of red, green, blue, red, green, and blue. In a case where the frame rate is equal to or higher than a predetermined frequency, the images are individually recognized by the user as a series of continuous images. That is, the user perceives the images of the respective color components of red, green, and blue, which are sequentially projected in a time-division manner, as a synthesis image obtained by synthesizing the images.
As illustrated in
Furthermore, writing of data of an image signal to the first holding unit (data-latch) 51 is performed during a blanking period. The blanking period is a period between a PWM period of a certain subframe and a PWM period of a next subframe. The blanking period is also a reset period. Since the light source is turned off during the blanking period, double latching is not necessary by writing the data of the image signal during this period.
The clock generator 16 generates a reference clock. The clock generator 16 can generate a reference clock having an arbitrary waveform. Therefore, a gamma adjustment to be described with reference to
The global counter 30 includes a flip-flop. In the configuration example of the global counter 30 illustrated in
The inversion timing of the output signal of the global counter 30 is generated on the basis of a reference clock having a higher frequency. The set value storage register 18 in the display device 1 can arbitrarily control the inversion timing of the global counter 30.
The global counter 30 generates a count signal having a predetermined (arbitrary) waveform on the basis of the reference clock. The global counter 30 performs gamma correction and generates a count signal to change a pulse waveform. In gamma 2.2, the global counter 30 generates the count signal such that the pulse width gradually increases, that is, the cycle gradually increases. In the example illustrated in
Normally, for example, in a case where linear gamma is adjusted to gamma 2.2 by 8 bits, gamma adjustment is performed by increasing the gradation to 10 bits. In this case, the number of necessary first holding units 51 increases.
On the other hand, the global counter 30 can perform gamma correction on the basis of the reference clock without increasing the bit depth, and adjust the gamma value.
In the gray code, a one-bit count signal transitions at one timing. In a case where the global counter 30 is a gray code counter, the occurrence of hazard can be suppressed. Furthermore, since the gray code has the smaller number of transitions than the binary code, the power consumption can be suppressed.
Note that in a case where the count signal of the gray code counter is used, the line buffer 24 illustrated in
The display device 1 further includes a first chip CH1, a second chip CH2 stacked with the first chip CH1, and a via (columnar electrode) V.
The first chip CH1 is a low-voltage circuit board. In the example illustrated in
The second chip CH2 is a high-voltage circuit board. In the example illustrated in
The via V electrically connects the first chip CH1 and the second chip CH2. In the example illustrated in
As illustrated in
In the first chip CH1, in one pixel row, each of N pixels includes the first holding unit (MEM) 51 and the PWM signal generation circuits 52 (PWM). In the example illustrated in
In a case where the area of the via V is large as compared with the area of the pixel 50, it may be difficult to dispose the via V for each pixel 50. In this case, as illustrated in
In the example illustrated in
In the examples illustrated in
The first holding unit (data-latch) 51 is provided for each pixel 50. The first holding unit 51 is collectively disposed, for example, at the central portion of the pixel region 26. Thus, the layout efficiency can be improved. For example, since 8-bit data is held in one pixel 50, the first holding unit 51 of 10×8×8=640 bits is disposed.
For example, the PWM signal generation circuit 52 is disposed adjacent to the first holding unit 51 in the vertical direction of the paper surface of
For example, the second holding unit 54 and the signal level conversion unit 53 are disposed adjacent to the PWM signal generation circuit 52 in the vertical direction of the paper surface of
10×8 pixel electrodes 55 are disposed in a matrix. In
Since the PWM signal generation circuit 52 is shared by four pixels 50, the number of elements can be reduced by, for example, about 45% as compared with a case where the PWM signal generation circuit 52 is provided for each pixel 50. As the bit depth increases, the number of elements can be further reduced.
As described above, according to the first embodiment, the PWM signal generation circuit 52 is disposed in the pixel 50. Therefore, the frame rate can be improved, and the power consumption can be suppressed.
As a comparative example, the PWM signal generation circuit 52 may be disposed outside the pixel region 26. In this case, the PWM signal generation circuit 52 reads the image signal from a memory (first holding unit 51) in the pixel region 26, and returns the PWM signal to the pixel region 26. In this case, in order to generate the PWM signal, it is necessary to read and write eight bits for each gradation. It is necessary to perform read driving for only one gradation expression, and it is difficult to increase the speed. That is, it is difficult to improve the frame rate. Furthermore, the power consumption increases due to charging and discharging of the wiring.
On the other hand, in the first embodiment, the PWM signal generation circuit 52 is disposed in the pixel 50. Moreover, in the first embodiment, the PWM signal generation circuit 52 is disposed close to the first holding unit 51. Thus, the distance of the wiring between the first holding unit 51 and the PWM signal generation circuit 52 can be shortened, and the influence of a load capacitance can be suppressed. That is, since the first holding unit 51 and the PWM signal generation circuit 52 are integrated in the pixel 50, the power consumption can be suppressed. Furthermore, since the PWM signal generation circuit 52 is disposed in the pixel 50, the number of data accesses can be reduced. In the first holding unit 51 in the pixel 50, for example, the PWM signal generation circuit 52 is only required to compare an image signal collectively held for 8 bits with a count signal input from the outside of the pixel 50. Therefore, the PWM signal generation circuit 52 may not perform the read driving for generating the PWM signal. Therefore, the frame rate can be improved.
Furthermore, in the first embodiment, the display device 1 performs color sequential driving. In the color sequential driving, when the frame rate (subframe rate) is low, a color breakup phenomenon is likely to occur. By improving the frame rate, the color breakup can be suppressed, and the visibility can be improved.
Furthermore, in the first embodiment, the gamma correction can be performed digitally without increasing the bit depth. Therefore, the necessary memory can be reduced.
The first holding unit 51 is, for example, a capacitor. The capacitor as the first holding unit 51 has one end electrically connected to the first input unit of the EXNOR circuit 521 and the other end electrically connected to the reference voltage node (ground).
As in the first modification example of the first embodiment, a capacitor may be used as the first holding unit 51. In this case, effects similar to those of the first embodiment can be obtained.
For example, the first holding units 51 corresponding to bits [7:6] that are the most significant 2 bits are grouped (segmented) to correspond to one bit. Bits [7:6] are segmented and 0/1 is updated as needed. When the update bit=N as needed, the bit corresponding to the first holding unit 51 and the bit corresponding to the EXNOR circuit 521 can be reduced to 8-log 2(N)+1 bit.
In
In the first embodiment, writing of data to the first holding unit 51 is collectively performed. On the other hand, in the second embodiment, the data is written to the first holding unit 51 a plurality of times. By writing a bit having a slow count signal transition a plurality of times, for example, the number of elements such as the EXNOR circuits 521 or the like can be reduced. Furthermore, the number of input terminals of the AND circuit 522 can be reduced.
Note that in the example illustrated in
Furthermore, the bit depth to be segmented is not limited to two. Furthermore, the most significant bit is not necessarily segmented.
As in the second embodiment, a plurality of high-order bits may be segmented. Note that in the second embodiment, a in the first embodiment, the frame rate can be improved, and the power consumption can be suppressed.
In the example illustrated in
The first switches SW1 of the first and second stages in
As in the first modification example of the second embodiment, the count signal of the gray code counter may be used. In this case, effects similar to those of the second embodiment can be obtained.
The second holding unit 54 includes a latch circuit including two inverter circuits. The inverter includes two different conductive transistors.
The second holding unit 54 operates at a voltage level between a voltage level (for example, 3 V) of a reference voltage node VDD and a voltage level (for example, 0 V) of a reference voltage node VSS. That is, the PWM signal generated by the PWM signal generation circuit 52 has a high level of 3 V and a low level of 0 V.
The signal level conversion unit 53 includes a first transistor Tr1, a second transistor Tr2, a third transistor Tr3, a fourth transistor Tr4, and a first capacitor Ca1.
The first transistor Tr1, the third transistor Tr3, the fourth transistor Tr4, and the second transistor Tr2 are connected in series in this order between the reference voltage node VCC and the reference voltage node VSS. The voltage level (for example, 6 V) of the reference voltage node VCC is higher than the voltage level of the reference voltage node VDD.
The first transistor Tr1 has one end electrically connected to the reference voltage node VCC and a gate to which a reset signal (first signal) is input. The first transistor Tr1 is, for example, a P-type (first conductive) metal-oxide-semiconductor field effect transistor (MOSFET).
The second transistor Tr2 has one end electrically connected to the reference voltage node VSS and a gate to which the outputs of the PWM signal generation circuit 52 and the second holding unit 54 are electrically connected. The second transistor Tr2 is, for example, an N-type (second conductive) MOSFET.
The third transistor Tr3 is connected between the first transistor Tr1 and the second transistor Tr2, and the reference voltage node VDD is electrically connected to the gate of the third transistor Tr3. The third transistor Tr3 is, for example, a P-type MOSFET.
The fourth transistor Tr4 is connected between the first transistor Tr1 and the second transistor Tr2, and the reference voltage node VDD is electrically connected to the gate of the fourth transistor Tr4. The fourth transistor Tr4 is, for example, an N-type MOSFET.
A node between the third transistor Tr3 and the fourth transistor Tr4 which are connected in series is electrically connected to the pixel electrode 55.
The first capacitor Ca1 is connected between the pixel electrode 55 and the reference voltage node VSS. For example, the first capacitor Ca1 is provided to hold a voltage during a period from time t12 to time t13 in
First, at time t11, the reset signal becomes low. Thus, the first transistor Tr1 is turned on. Furthermore, at time t11, zero is written to the second holding unit 54, and the voltage of the second holding unit 54 is low. Thus, the second transistor Tr2 is turned off. Since the gate of the third transistor Tr3 and the gate of the fourth transistor Tr4 are electrically connected to the reference voltage node VDD, the third transistor Tr3 and the fourth transistor Tr4 are continuously turned on. Therefore, the voltage of pixel electrode 55 becomes high.
Next, at time t12, the reset signal becomes high. Thus, the first transistor Tr1 is turned off.
Next, at time t13, the AND circuit 522 outputs one. Thus, the second transistor Tr2 is turned on. Therefore, the voltage of pixel electrode 55 becomes low.
In the reset signal applied to the gate of the first transistor Tr1, High indicates 6 V and Low indicates 3 V In the voltage of the second holding unit 54, which is applied to the gate of the second transistor Tr2, High indicates 3 V and Low indicates 0 V Furthermore, as described above, the voltage applied to the gate of the third transistor Tr3 and the gate of the fourth transistor Tr4 is 3 V.
In the voltage relationship illustrated in
As in the third embodiment, the configuration of the signal level conversion unit 53 may be changed. Note that in the second embodiment, as in the first embodiment, the power consumption can be suppressed, and the frame rate can be improved.
Furthermore, the signal level conversion unit (level shift circuit) 53 according to the third embodiment may be incorporated in the pixel circuit including the PWM signal generation circuit 52 as described above, or may be an independent pixel circuit.
The output unit of the PWM signal generation circuit 52 is electrically connected to the gate of the second transistor Tr2. Therefore, the PWM signal is input to the gate of the second transistor Tr2.
The operation of the signal level conversion unit 53 according to the first modification example of the third embodiment is substantially the same as that of the signal level conversion unit 53 according to the third embodiment.
As in the first modification example of the third embodiment, the second holding unit 54 may not be provided. In this case, effects similar to those of the third embodiment can be obtained.
The signal level conversion unit 53 includes a fifth transistor Tr5, a sixth transistor Tr6, a seventh transistor Tr7, and a voltage booster 531.
The fifth transistor Tr5 is connected between one end of the second holding unit 54 and the pixel electrode 55. The gate of the fifth transistor Tr5 is electrically connected to the reference voltage node VDD. The fifth transistor Tr5 is, for example, an N-type MOSFET.
The sixth transistor Tr6 is connected between the other end of the second holding unit 54 and the reference voltage node VSS, and the reset signal is input to the gate of the sixth transistor Tr6. The sixth transistor Tr6 is, for example, an N-type MOSFET.
The seventh transistor Tr7 is connected between one end of the second holding unit 54 and the reference voltage node VSS, and the output unit of the AND circuit 522 is electrically connected to the gate of the seventh transistor Tr7. The seventh transistor Tr7 is, for example, an N-type MOSFET.
The voltage booster 531 increases the voltage of the pixel electrode 55 by capacitive coupling. The voltage booster 531 includes a second capacitor Ca2. The second capacitor Ca2 is connected between a signal line Rift and the pixel electrode 55.
First, at time t21, the reset signal becomes high. Thus, the sixth transistor Tr6 is turned on. As a result, the voltage at the other end of the second holding unit 54 becomes low (voltage VSS). Moreover, the voltage at one end of the second holding unit 54 becomes high (voltage VDD). Since the fifth transistor Tr5 has a gate electrically connected to the reference voltage node VDD, the fifth transistor Tr5 are continuously turned on. Furthermore, since the gate of the fifth transistor Tr5 is fixed at the voltage VDD, the source voltage of the fifth transistor Tr5 becomes VDD-Vth. Vth is a threshold voltage of the fifth transistor Tr5. Thus, the voltage of the pixel electrode 55 becomes VDD-Vth.
Next, at time t22, the signal line Rift becomes high. Due to capacitive coupling of the second capacitor Ca2, the voltage of the pixel electrode 55 increases by ΔV Thus, the voltage of pixel electrode 55 becomes VDD-Vth+ΔV. VDD-Vth+ΔV is a voltage higher than the voltage VDD.
Next, at time t23, the reset signal becomes low. Thus, the sixth transistor Tr6 is turned off.
Next, at time t24, the AND circuit 522 outputs one. Thus, the seventh transistor Tr7 is turned on. Therefore, the voltage of pixel electrode 55 becomes low.
In the second embodiment, the gate-source voltages and the drain-source voltages of all the transistors are equal to or less than a voltage VDD. Therefore, the breakdown voltage of the transistor can be lowered. That is, a low breakdown voltage transistor can be used for all the transistors. As a result, the size of the transistor can be further reduced, and the pixel 50 can be more easily miniaturized.
As in the second modification example of the third embodiment, the voltage level may be converted using the capacitive coupling. In this case, effects similar to those of the third embodiment can be obtained.
The gate of the fifth transistor Tr5 is electrically connected to the signal line Trans. A pulse signal is input from the signal line Trans to the gate of the fifth transistor Tr5. The high voltage of the signal line Trans is, for example, the voltage VDD. The low voltage of the signal line Trans is a logic voltage level lower than the voltage VDD. Therefore, the low voltage of the signal line Trans is higher than the voltage VSS, and is, for example, the output level at which the AND circuit 522 outputs one. Furthermore, the fifth transistor Tr5 is continuously turned on.
First, at time t31, the reset signal becomes high. Thus, the sixth transistor Tr6 is turned on. As a result, the voltage at the other end of the second holding unit 54 becomes low (voltage VSS). Moreover, the voltage at one end of the second holding unit 54 becomes high (voltage VDD).
Next, at time t32, the reset signal becomes low. Thus, the sixth transistor Tr6 is turned off.
Next, at time t33, the signal line Trans becomes high. The high voltage of the signal line Trans is, for example, the voltage VDD. Therefore, the source voltage of the fifth transistor Tr5 becomes VDD-Vth. Thus, the voltage of the pixel electrode 55 becomes VDD-Vth.
Next, at time t34, the signal line Rift becomes high. Due to capacitive coupling of the second capacitor Ca2, the voltage of the pixel electrode 55 increases by ΔV. Thus, the voltage of pixel electrode 55 becomes VDD-Vth+ΔV VDD-Vth+ΔV is a voltage higher than the voltage VDD.
Next, at time t35, the signal line Trans becomes low.
Next, at time t36, the AND circuit 522 outputs one. Thus, the seventh transistor Tr7 is turned on. Therefore, the voltage of pixel electrode 55 becomes low.
In the circuit configuration illustrated in
Four first holding units 51 and four EXNOR circuits 521 are provided. The data Dx (x=0, 1, 2, 3) is input to the first holding unit 51, and the count signal Cx (x=0, 1, 2, 3) is input to the second input unit of the EXONOR circuit.
Total 8 bits of bits [7:0] are divided into two, for example, total 4 bits of bits [7] and [2:0] and total 4 bits of bits [6:3]. That is, the number of the first holding units 51 and the number of the EXNOR circuits 521 can be halved to four as compared with
That is, a plurality of bits of the image signal is time-divided a plurality of times in one subframe. The PWM signal generation circuit 52 generates a PWM signal time-divided a plurality of times in one subframe according to an image signal time-divided into a plurality of bits.
First, in a first half reset period, a 4-bit digital image signal of bits [7] and [2:0] is written to the first holding unit 51 of the data from D0 to D3.
Furthermore, one (voltage VCC) is written to the second holding unit 54 (pixel 50) by reset.
Next, the count signals C0 to C3 are input from the global counter 30. Note that the count signal C3 is adjusted to an unbalanced count signal so as to be, for example, 7:128.
Next, the AND circuit 522 outputs one at a timing when the data of the first holding unit 51 of the first half and the count value of the first half all match. Thus, zero (ground voltage) is written to the second holding unit 54.
In this manner, the first half counting ends.
Next, in a second half reset period, a 4-bit digital image signal of bits [6:3] is written into the first holding unit 51 of the data from D0 to D3.
Furthermore, one (voltage VCC) is written to the second holding unit 54 (pixel 50) by reset.
Next, the count signals C0 to C3 are input from the global counter 30.
Next, the AND circuit 522 outputs one at a timing when the data of the first holding unit 51 of the second half and the count value of the second half all match. Thus, zero (ground voltage) is written to the second holding unit 54.
Here, the digital image signal is time-divided according to the weight of the bit. More specifically, the digital image signal is time-divided such that weights of bits are substantially equal.
As a comparative example, in a case where the bit is divided into 4 bits of bits [7:4] and 4 bits of bits [3:0], the weights of the bits are biased in the first half and the second half. The weight of bits [7:4] is 240, and the weight of bits [3:0] is 15. In this case, the width of the PWM signal in the second half becomes short. There is a case where a delay occurs in the rising and falling of the PWM signal that is an electric signal when the liquid crystal is driven. Due to this delay, in a case where the width of the PWM is short, there is a possibility that the PWM period ends without starting driving of the liquid crystal.
On the other hand, in the fourth embodiment, the weights of the bits of the digital image signal are substantially equal. The weights of bits [7] and [2:0] are 135, and the weight of bits [6:3] is 120. Thus, the ratio of the weights of bits [7] and [2:0] is 135/255×100=53%, and the ratio of the weight of the bits [6:3] is 120/255×100=47%. Therefore, the influence of the delay in driving the liquid crystal can be suppressed.
As in the fourth embodiment, it may be driven in a time-division manner in the subframe. Note that in the fourth embodiment, as in the first embodiment, the power consumption can be suppressed, and the frame rate can be improved.
Three first holding units 51 and three EXNOR circuits 521 are provided. The data Dx (x=0, 1, 2) is input to the first holding unit 51, and the count signal Cx (x=0, 1, 2) is input to the second input unit of the EXONOR circuit.
Total 8 bits of bits [7:0] are divided into three, for example, total 2 bits of bits [7] and [0], total 3 bits of bits [6] and [1:0], and total 3 bits of bits [5:3]. That is, the number of the first holding units 51 and the number of the EXNOR circuits 521 can be reduced to three as compared with
Note that the driving method is substantially the same as that for the pixel 50 of the fourth embodiment.
Furthermore, the number of divisions is not limited to three, and may be, for example, four. Total 8 bits of bits [7:0] are divided into four, for example, total 2 bits of bits [7] and [0], total 2 bits of bits [6] and [1], total 2 bits of bits [5] and [2], and total 2 bits of bits [4] and [3]. In this case, the number of the first holding units 51 and the number of the EXNOR circuits 521 can be reduced to two.
As in the first modification example of the fourth embodiment, the number of divisions may be changed. In this case, effects similar to those of the fourth embodiment can be obtained.
Total 8 bits of bits [7:0] are divided into two, for example, total 4 bits of bits [7:4] that are high-order 4 bits, and total 4 bits of bits [3:0] that are low-order 4 bits.
That is, a plurality of bits of the image signal is time-divided into a first half bit and a second half bit in one subframe.
The pixel 50 further includes a selector 56 and a switching unit 57.
The selector 56 selects the first holding unit 51 that holds the image signal of the first half bit and the first holding unit 51 that holds the image signal of the second half bit. In the selector 56, an input unit is electrically connected to two first holding units 51, and an output unit is electrically connected to the first input unit of the EXNOR circuit 521. The selector 56 electrically connects one of the first holding units 51 to the EXNOR circuit 521.
In a case where a signal for selecting a most significant bit (MSB) side is input to the selector 56, the selector 56 selects the first holding unit 51 to which high-order bit data Dx (x=4, 5, 6, 7) is input. In a case where a signal for selecting a least significant bit (LSB) side is input to the selector 56, the selector 56 selects the first holding unit 51 to which low-order bit data Dx (x=0, 1, 2, 3) is input.
Note that the signal for selecting the MSB side and the signal for selecting the LSB side have a complementary relationship.
The switching unit 57 switches the output of the PWM signal generation circuit 52 according to the count of the first half bit or the count of the second half bit. The switching unit 57 includes a first switching transistor 571 and a second switching transistor 572.
The first switching transistor 571 is disposed on one side branched from the node of the output of the AND circuit 522. In a case where the signal for connecting to the MSB side is input to the first switching transistor 571, the first switching transistor 571 sends the output of the AND circuit 522 to the second switch SW2.
The second switching transistor 572 is disposed on the other side branched from the node of the output of the AND circuit 522. In a case where the signal for connecting to the LSB side is input to the second switching transistor 572, the second switching transistor 572 sends the output of the AND circuit 522 to the third switch SW3.
Eight first holding unit 51 are provided. That is, by providing four selectors 56, the number of the EXNOR circuits 521 can be halved to four as compared with
The PWM signal generation circuit 52 generates a PWM signal according to a first timing based on the first half bit and the count signal of a first polarity (count-down) and a second timing based on the second half bit and the count signal of a second polarity (count-up).
In the example illustrated in
First, high-order 4-bit digital image signal is written to the first holding unit 51 of data from D4 to D7.
For example, writing of the low-order 4-bit digital image signal to the first holding unit 51 of the data from D0 to D3 may be performed simultaneously with writing of the high-order 4-bit digital image signal, and is only required to be performed until the completion of the count-down in the first half to be described later.
Next, the selector 56 selects the first holding unit 51 on the MSB side, and the switching unit 57 connects the output of the AND circuit 522 to the MSB side.
Next, the count signals C4 to C7 (low speed) of reverse polarity countdown are input from the global counter 30. Note that in the case of the count-down, the count values are counted in the order of 15, 14, . . . , 1, and 0.
Next, the AND circuit 522 outputs one at a timing when the data of the first holding unit 51 of the first half and the count value of the first half all match. Thus, one (voltage VCC) is written to the second holding unit 54. In the example illustrated in
In this manner, the first half count-down ends.
Next, the selector 56 selects the first holding unit 51 on the LSB side, and the switching unit 57 connects the output of the AND circuit 522 to the LSB side.
Next, the count signals C0 to C3 (low speed) of count-up are input from the global counter 30. Note that in the case of the count-up, the count values are counted in the order of 0, 1, . . . , 14, and 15.
Next, the AND circuit 522 outputs one at a timing when the data of the first holding unit 51 of the second half and the count value of the second half all match. Thus, zero (ground voltage) is written to the second holding unit 54. In the example illustrated in
Furthermore, in the example illustrated in
As in the second modification example of the fourth embodiment, the selector 56 that selects the first holding unit 51 and the switching unit 57 for writing one to the second holding unit 54 may be provided. In this case, effects similar to those of the fourth embodiment can be obtained.
Since the selector 56 is not provided, the number of the first holding units 51 can be reduced to four as compared with
In
The driving illustrated in
In the third modification example of the fourth embodiment, as compared with the second modification example of the fourth embodiment, there is a useless period in the subframe for writing data, but the number of first holding units 51 can be reduced to further miniaturize the pixel 50.
As in the third modification example of the fourth embodiment, the switching unit 57 for writing one to the second holding unit 54 may be provided without providing the selector 56. In this case, effects similar to those of the second modification example of the fourth embodiment can be obtained.
The pixel configuration illustrated in
As in the fourth embodiment, total 8 bits of bits [7:0] are divided into two, for example, total 4 bits of bits [7] and [2:0] and total 4 bits of bits [6:3]. That is, the number of the first holding units 51 and the number of the EXNOR circuits 521 can be halved to four as compared with
In the fourth modification example of the fourth embodiment, as in the fourth embodiment, total 8 bits of bits [7:0] are divided into two, for example, total 4 bits of bits [7] and [2:0] and total 4 bits of bits [6:3]. The weights of the bits of the digital image signal are substantially equal in the first half and the second half. Therefore, the influence of the delay in driving the liquid crystal can be suppressed.
In the example illustrated in
The driving illustrated in
As in the fourth modification example of the fourth embodiment, the switching unit 57 for writing one to the second holding unit 54 may be provided, and time division may be performed such that the weights of bits are substantially equal. In this case, effects similar to those of the fourth embodiment and the third modification example of the fourth embodiment can be obtained.
The first holding unit 51, the PWM signal generation circuit 52, the signal level conversion unit 53, and the second holding unit 54 are shared by two vertically adjacent pixels. Therefore, the number of first holding units 51, the number of PWM signal generation circuits 52, the number of signal level conversion units 53, and the number of second holding units 54 can be reduced to half.
The pixel 50 further includes an eighth transistor Tr8, a relay wiring L, and a ninth transistor Tr9.
The eighth transistor Tr8 is connected between the second holding unit 54 and the pixel electrode 55. The eighth transistor Tr8 is provided in front of each pixel electrode 55.
The relay wiring L is a wiring disposed so as to connect a plurality of the pixel electrodes 55 via the eighth transistor Tr8.
The ninth transistor Tr9 is disposed between the pixel electrodes 55 (eighth transistors Tr8) on the relay wiring L. The ninth transistor Tr9 operates to separate the pixel electrodes 55.
The pixel 50 performs display switching driving for each color component. Among three vertical pixels, two vertical pixels are simultaneously written, and simultaneously displayed on two lines. Among three vertical pixels, two upper pixels are referred to as Odd line, and two lower pixels are referred to as Even line. The display switching driving is performed by switching the Odd line and the Even line and performing display in the first subframe and the second subframe with each color. The eighth transistor Tr8 and the ninth transistor Tr9 operate so as to enable display switching driving.
As illustrated in
In the native subframe, 8×8 pixels 50 are shown. For example, in the red component, pixels of R1, R9, R17, R25, R33, R41, R49, and R57 are present in a first column.
By the pixel shift driving, in the first subframe of the red component, the pixels 50 of R1, R17, R33, and R49 are respectively displayed so as to be based on the same image signal in two vertical pixels. In the second subframe of the red component, the pixels 50 of R1, R9, R25, R41, and R57 are respectively displayed so as to be based on the same image signal in two vertical pixels. As described above, the first subframe and the second subframe are synthesized and perceived by the user.
As described above, in the fifth embodiment, some of a plurality of the pixel electrodes 55 sharing the first holding unit 51 and the PWM signal generation circuit 52 are driven on the basis of the same image signal, and the pixel electrodes 55 are driven such that the arrangement of the pixel electrodes 55 driven on the basis of the same image signal is changed for each subframe of the same color component. More specifically, two pixel electrodes 55 adjacent in a first direction (column direction) are driven on the basis of the same image signal, and the pixel electrodes 55 are driven such that two pixel electrodes 55 driven on the basis of the same image signal are shifted by one pixel electrode 55 in the first direction for each subframe of the same color component.
In a case where the pixel shift driving is not performed, the circuit such as the PWM signal generation circuit 52 is shared by two pixels 50, and thus the resolution in the vertical direction is also halved.
On the other hand, in the fifth embodiment, by shifting the pixel 50 to be displayed for each subframe of each color, it is possible to suppress a reduction in resolution, which is caused by a reduction in the number of elements.
As in the fifth embodiment, the pixel shift driving may be performed. Note that in the fifth embodiment, as in the first embodiment, the power consumption can be suppressed, and the frame rate can be improved.
The first holding unit 51, the PWM signal generation circuit 52, the signal level conversion unit 53, and the second holding unit 54 are shared by 2×2 pixels adjacent to each other. Therefore, the number of first holding units 51, the number of PWM signal generation circuits 52, the number of signal level conversion units 53, and the number of second holding units 54 can be reduced to one fourth.
The pixel 50 includes a tenth transistor Tr10. The tenth transistor Tr10 is connected between the second holding unit 54 and the pixel electrode 55. The tenth transistor Tr10 is provided in front of each pixel electrode 55.
As illustrated in
As illustrated in
In the red component and the blue component, of two horizontal pixels, pixels 50 to be displayed are alternately switched in the horizontal direction. For example, in the red component, there are pixels 50 of R1, R2, R9, and R10 corresponding to 2×2. In the first subframe of the red component, the pixel 50 of R1 is displayed so as to be based on the same image signal in two horizontal pixels. In the third subframe, the pixel 50 of R2 is displayed so as to be based on the same image signal in two horizontal pixels. Similarly, in the second subframe of the red component, the pixel 50 of R10 is displayed so as to be based on the same image signal in two horizontal pixels. In the fourth subframe, the pixel 50 of R9 is displayed so as to be based on the same image signal in two horizontal pixels.
For example, in the green component, there are pixels 50 of G1, G2, G9, and G10 corresponding to 2×2. The pixels 50 are displayed in order of G1, G10, G2, and G9 in the first to fourth subframes of the green component.
As described above, in the first modification example of the fifth embodiment, in the red component and the blue component, two pixel electrodes 55 adjacent in a second direction (row direction) are driven on the basis of the same image signal, and the pixel electrodes 55 are driven such that two pixel electrodes 55 driven on the basis of the same image signal are shifted by one pixel electrode 55 in the first direction (column direction) perpendicular to the second direction for each subframe of the same color component. Furthermore, in the green component, one of four pixel electrodes 55 is driven, and the pixel electrode 55 is driven such that the arrangement of the pixel electrodes 55 to be driven for each subframe changes.
Since the pixel shift driving as illustrated in
As in the first modification example of the fifth embodiment, the pixel shift driving may be performed for 2×2 pixels. In this case, effects similar to those of the fifth embodiment can be obtained.
In AR, for example, images and the like are superimposed and displayed in a certain region of the real world seen through smart glasses. Therefore, the probability that the image is displayed on the entire screen is low, and it is preferable to reduce the power consumption by stopping the circuit as much as possible in a region (black region B) of a black display portion where the image is not displayed.
The display device 1 further includes a flag generation circuit (flag generation unit) 32, a flag determination circuit, and a drive stop unit.
The flag generation circuit 32 calculates the sum of the signal values (gradation values) of the image signals for each subframe (color component) and for each predetermined region of a plurality of arranged pixels 50, and generates a black flag in a case where the sum of the signal values is equal to or less than a predetermined value. A predetermined region in the sixth embodiment is, for example, a pixel line which is one line of a plurality of pixels 50 arranged in a matrix. The flag generation circuit 32 stores the flag together with the image signal in the frame memory 22. Note that for the pixel 50 for which the flag has been generated, the flag generation circuit 32 may not write the image signal to the frame memory 22. That is, the flag generation circuit 32 may write only the data of the image signal having the gradation value in the frame memory 22. The flag generation circuit 32 is provided, for example, between the multiplexer 12 and the frame memory 22.
The flag determination circuit determines the presence or absence of a flag. The flag determination circuit is disposed in the line buffer 24, the global counter 30, and the V driver 28.
The drive stop unit stops driving of the pixel 50 determined to have the black flag. That is, the drive stop unit stops the driving of the pixels 50 in a predetermined region of the subframe for which the black flag is generated. Thus, at the display surface of the pixel 50, some of the pixels 50 can stop driving and perform partial driving. As a result, the power consumption be suppressed. The drive stop unit is disposed in the line buffer 24, the global counter 30, and the V driver 28.
More specifically, the drive stop unit stops the input of the image signal to the first holding unit 51 of the pixel 50 in a predetermined region of the subframe for which the black flag is generated. That is, the drive stop unit stops the scan for writing the data of the image signal to the first holding unit 51 by the line buffer 24. Therefore, the power consumption can be reduced.
Furthermore, more specifically, the drive stop unit stops the input of the count signal to the PWM signal generation circuit 52 of the pixel 50 in a predetermined region of the subframe for which the black flag is generated. That is, the drive stop unit stops the input of the count signal to the PWM signal generation circuit 52 by the global counter 30. Therefore, the power consumption can be reduced.
Since other configurations of the display device 1 according to the sixth embodiment are similar to the corresponding configurations of the display device 1 according to the first embodiment, the detailed description thereof will be omitted.
Next, the operation of the partial driving will be described.
First, before the image signal is written to the frame memory 22, the flag generation circuit 32 calculates the sum of gradation values for each color component (subframe) of RGB and for each line.
Next, the flag generation circuit 32 identifies a line in which the sum of the gradation values is zero as a black line (black region B). That is, the flag generation circuit 32 generates the black flag. The flag generation circuit 32 stores the black flag in the set value storage register 18 for each color component and for each line.
In
Next, the flag determination circuit determines the presence or absence of the black flag in each line of the subframe of each color. The line buffer 24 does not write the data of the image signal to the first holding unit 51 (data scan in
The pixel 50 on a line with the black flag is reset, the gradation value is set to zero, and PWM is immediately lowered. Furthermore, the pixel 50 may be reset for each line in conjunction with the black flag.
In
For example, the global counter 30 performs gating for each line. That is, the global counter 30 inputs the count signal in units of lines. The global counter 30 inputs the count signal to all the pixels 50 on the line in which the black flag is zero.
As in the sixth embodiment, the partial driving may be performed. Note that in the sixth embodiment, as in the first embodiment, the power consumption can be suppressed, and the frame rate can be improved.
Furthermore, in the display device 1 according to the sixth embodiment, the arrangement of the first holding unit 51 and the PWM signal generation circuit 52 may be not necessarily the same as that in the first embodiment. For example, in the sixth embodiment, the PWM signal generation circuit 52 may be disposed outside the pixel 50. Furthermore, the display device 1 according to the sixth embodiment performs color sequential driving, and generates and determines a flag for each subframe. However, the present disclosure is not limited thereto, and the partial driving may be performed for each color component in one frame. That is, the partial driving may be applied to other display driving methods other than the color sequential driving such as LCOS.
A predetermined region in the first modification example of the sixth embodiment is, for example, a line division region divided in a direction along one line (pixel line) from the pixel line. In the example illustrated in
Next, the operation of the partial driving will be described.
First, before the image signal is written to the frame memory 22, the flag generation circuit 32 calculates the sum of gradation values for each color component (subframe) of RGB and for each line division region.
Next, the flag generation circuit 32 identifies a line division region in which the sum of the gradation values is zero as the black region B. That is, the flag generation circuit 32 generates the black flag. The flag generation circuit 32 stores the black flag in the set value storage register for each color component and for each line division region.
Next, the flag determination circuit determines the presence or absence of the black flag in each line division region of the subframe of each color. The line buffer 24 does not write the data of the image signal to the first holding unit 51 for the line division region with the black flag in the subframe of each color.
In
Furthermore, the global counter 30 does not pass the count signal to the PWM signal generation circuit 52 for the line with the black flag in all the horizontal four division regions in the subframe of each color. In a case where at least one black flag is zero in the line division region, the global counter 30 passes the count signal to one line including the line division region in which the black flag is zero. Therefore, the count signal is input not only to the line division region in which the black flag is zero but also to the pixels 50 in the line division regions in the second to fourth columns from the left and in the first, second, fifth, and sixth rows from the top in which the black flag is one.
That is, the PWM signal generation circuit 52 receives the count signal for each pixel line, which is one line of a plurality of the pixels 50 arranged in a matrix. Furthermore, the drive stop unit stops the input of the count signal to the PWM signal generation circuit 52 of the pixel 50 on the pixel line of the subframe for which the black flag is generated for all the pixels in the pixel line.
The pixel 50 in the line division region with the black flag is reset, the gradation value is set to zero, and PWM is immediately lowered. Furthermore, the pixel 50 may be reset for each line division region in conjunction with the black flag.
As illustrated in
As illustrated in
As in the first modification example of the sixth embodiment, the line may be divided in the horizontal direction to perform the partial driving. In this case, effects similar to those of the sixth embodiment can be obtained.
The display device 1 according to the present disclosure can be mounted on various electronic devices.
The vehicle 100 of
The center display 101 is disposed on a dashboard 107 at a location facing a driver seat 108 and a passenger seat 109.
The safety-related information is information of doze sensing, looking-away sensing, sensing of mischief of a child riding together, presence or absence of wearing of a seat belt, sensing of leaving of an occupant, and the like, and is information sensed by the sensor arranged to overlap with a back surface side of the center display 101, for example. The operation-related information senses a gesture related to an operation by the occupant by using the sensor. The sensed gestures may include an operation of various types of equipment in the vehicle 100. For example, operations of air conditioning equipment, a navigation device, an AV device, a lighting device, and the like are detected. The life log includes life logs of all the occupants. For example, the life log includes an action record of each occupant in the vehicle. By acquiring and storing the life log, it is possible to check a state of the occupant at a time of an accident. The health-related information senses the body temperature of the occupant by using the temperature sensor, and estimates a health condition of the occupant on the basis of the sensed body temperature. Alternatively, the face of the occupant may be imaged by using an image sensor, and the health condition of the occupant may be estimated from the imaged facial expression. Moreover, a conversation may be made with the occupant in automatic voice, and the health condition of the occupant may be estimated on the basis of an answer content of the occupant. The authentication/identification-related information includes a keyless entry function of performing face authentication by using the sensor and a function of automatically adjusting a seat height and position in face identification. The entertainment-related information includes a function of detecting operation information of the AV device by the occupant by using the sensor, and a function of recognizing the face of the occupant by the sensor and providing a content suitable for the occupant by the AV device.
The console display 102 can be used, for example, to display the life log information. The console display 102 is disposed near a shift lever 111 of a center console 110 between the driver seat 108 and the passenger seat 109. The console display 102 can also display information sensed by the various sensors. Furthermore, the console display 102 may display an image of the vehicle surroundings captured by the image sensor, or may display an image of a distance to an obstacle in the vehicle surroundings.
The head-up display 103 is virtually displayed behind a windshield 112 in front of the driver seat 108. The head-up display 103 can be used to display, for example, at least one of the safety-related information, the operation-related information, the life log, the health-related information, the authentication/identification-related information, or the entertainment-related information. Since the head-up display 103 is virtually disposed in front of the driver seat 108 in many cases, the head-up display 103 is suitable for displaying information directly related to an operation of the vehicle 100, such as a speed of the vehicle 100 and a remaining amount of fuel (battery).
The digital rear mirror 104 can also display a state of the occupant in the rear seat in addition to the rear side of the vehicle 100, and thus can be used to display the life log information, for example, by disposing the sensor to overlap with a back surface side of the digital rear mirror 104.
The steering wheel display 105 is disposed near the center of a steering wheel 113 of the vehicle 100. The steering wheel display 105 can be used to display, for example, at least one of the safety-related information, the operation-related information, the life log, the health-related information, the authentication/identification-related information, or the entertainment-related information. In particular, since the steering wheel display 105 is close to the driver's hand, the steering wheel display 105 is suitable for displaying the life log information such as the body temperature of the driver, or for displaying information regarding an operation of the AV device, air conditioning equipment, or the like.
The rear entertainment display 106 is attached to the back side of the driver seat 108 and the passenger seat 109, and is for the occupant in the rear seat to view. The rear entertainment display 106 can be used to display, for example, at least one of the safety-related information, the operation-related information, the life log, the health-related information, the authentication/identification-related information, or the entertainment-related information. In particular, since the rear entertainment display 106 is in front of the occupant in the rear seat, information related to the occupant in the rear seat is displayed. For example, information regarding an operation of the AV device or the air conditioning equipment may be displayed, or a result of measuring the body temperature or the like of the occupant in the rear seat by the temperature sensor may be displayed.
The display device 1 according to the present disclosure can be applied to the center display 101, the console display 102, the head-up display 103, the digital rear mirror 104, the steering wheel display 105, and the rear entertainment display 106.
The display device 1 according to the present disclosure is applicable not only to various displays used in the vehicle but also to displays mounted on various electronic devices.
In the camera of
By applying the display device 1 according to the present disclosure to the monitor screen 126, the electronic viewfinder 124, the sub screen, and the like used for the camera, it is possible to reduce the cost and improve the display quality.
The display device 1 according to the present disclosure is also applicable to a head-mounted display (hereinafter, referred to as an HMD). The HMD can be used for virtual reality (VR), augmented reality (AR), mixed reality (MR), substitutional reality (SR), or the like.
Furthermore, a camera may be provided in the HMD 130 to capture an image around the wearer, and an image obtained by combining the image captured by the camera and an image generated by a computer may be displayed on the display device 132. For example, by disposing the camera to overlap with the back surface side of the display device 132 visually recognized by the wearer of the HMD 130, capturing an image of the surroundings of the eyes of the wearer with the camera, and displaying the captured image on another display provided on the outer surface of the HMD 130, a person around the wearer can obtain expression of the face and a movement of the eyes of the wearer in real time.
Note that various types of the HMD 130 are conceivable. For example, as illustrated in
The display device 1 according to the present disclosure is also applicable to a television device (hereinafter, a TV).
As described above, according to the display device 1 of the present disclosure, the TV 330 with low cost and excellent display quality can be realized.
The display device 1 according to the present disclosure is also applicable to a smartphone and a mobile phone.
Note that the present technology can have the following configurations.
(1)
A display device including:
The display device according to (1),
The display device according to (2),
The display device according to (2) or (3), in which the count signal supply unit is electrically connected to the second input unit via a buffer unit.
(5)
The display device according to any one of (2) to (4), in which the count signal supply unit is a gray code counter.
(6)
The display device according to any one of (2) to (5), in which the count signal supply unit generates the count signal having a predetermined waveform on the basis of a reference clock, and supplies the generated count signal to the PWM signal generation unit.
(7)
The display device according to any one of (1) to (6), further including:
The display device according to (7), further including:
The display device according to (7) or (8),
The display device according to (7) or (8),
The display device according to any one of (1) to (10), in which the PWM signal generation unit is shared by a plurality of the pixels.
(12)
The display device according to any one of (1) to (11),
The display device according to any one of (1) to (12), in which the first holding unit holds the image signal during a blanking period between a plurality of PWM periods corresponding to the PWM signal.
(14)
The display device according to any one of (1) to (13), in which the first holding unit holds the image signal having a subframe divided for each of a plurality of color components such that unit frames of the image signal are input in a predetermined order.
(15)
The display device according to (14),
The display device according to (15), in which a plurality of the bits of the image signal is time-divided a plurality of times in accordance with a weight of the bits.
(17)
The display device according to (16), in which a plurality of the bits of the image signal is time-divided such that weights of the bits are substantially equal.
(18)
The display device according to any one of (15) to (17),
The display device according to (18), further including a selector configured to select the first holding unit configured to hold the image signal of the first half bit and the first holding unit configured to hold the image signal of the second half bit.
(20)
The display device according to (18), in which the first holding unit holds the image signal of the second half bit in a period between the count of the first half bit and the count of the second half bit.
(21)
The display device according to any one of (15) to (20), further including a pixel electrode provided in the pixel,
The display device according to (21), in which two pixel electrodes adjacent in a first direction are driven on the basis of the same image signal, and the pixel electrodes are driven such that two pixel electrodes driven on the basis of the same image signal are shifted by one pixel electrode in the first direction for each subframe of the same color component.
(23)
The display device according to (21),
The display device according to any one of (1) to (23), further including:
The display device according to (24), in which the predetermined region is a pixel line which is one line of a plurality of the pixels arranged in a matrix.
(26)
The display device according to (24), in which the predetermined region is a line division region divided in a direction along one line from a pixel line, the line division region being one line of a plurality of the pixels arranged in a matrix.
(27)
The display device according to any one of (24) to (26), in which the drive stop unit stops an input of the image signal to the first holding unit of the pixel in the predetermined region of the color component for which the flag is generated.
(28)
The display device according to any one of (24) to (27),
Aspects of the present disclosure are not limited to the above-described individual embodiments, but include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. That is, various additions, modifications, and partial deletions are possible without departing from the conceptual idea and spirit of the present disclosure derived from the matters defined in the claims and equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-122829 | Jul 2021 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/011468 | 3/15/2022 | WO |
