Patent Application
20170309220
This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2016-0051094, filed on Apr. 26, 2016, the entire contents of which are hereby incorporated by reference.
The present disclosure herein relates to a display device, and more particularly, to a display device conforming to an interface specification between a signal control unit and a data driving unit.
A display device includes a display panel for displaying an image, a gate driving unit and a data driving unit for driving the display panel. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels respectively connected to the gate lines and the data lines. The plurality of pixels display gradations corresponding to data voltages supplied from the data driving unit. Accordingly, an image is displayed in the display panel.
Additionally, the display device includes a signal control unit for controlling the gate driving unit and the data driving unit. The signal control unit generates a plurality of driving signals for controlling the gate driving unit and the data driving unit in response to an external control signal. The signal control unit transmits a data driving signal and a plurality of image data to the data driving unit through an interface between the signal control unit and the data driving unit.
Meanwhile, there is a case that there occurs an error in driving of the data driving unit by noise or the like when the data driving signal and the plurality of image data are transmitted from the signal control unit to the data driving unit.
The present disclosure provides a display device having improved driving reliability of a data driving unit.
An embodiment of the inventive concept provides a display device including a signal control unit configured to output a gate driving signal, a clock signal having frequency information, a plurality of image data corresponding to a plurality of frame images, and a first frequency control signal for defining a plurality of frame periods in which the plurality of frame images are respectively displayed. A data driving unit has a signal processing unit configured to train the clock signal received from the signal control unit to generate an internal clock signal, and a data converting unit configured to convert the plurality of image data to a plurality of data voltages in response to the internal clock signal, and to output the data voltages. A gate driving unit is configured to output a gate signal in response to the gate driving signal received from the signal control unit. Aa display panel is configured to display the plurality of frame images corresponding respectively to the plurality of data voltages in response to the gate signal. The signal processing unit includes: a filtering unit configured to receive the first frequency control signal, and generate a second frequency control signal having a first level when a level of the first frequency control signal is maintained at the first level for a preset determination period, and having a second level when a level of the first frequency control signal is maintained at the second level for the determination period; and a clock training unit configured to perform clock training for generating the internal clock signal in response to the second frequency control signal.
In an embodiment, the data driving unit may further include a reference clock signal generating unit configured to generate a reference clock signal for determining the determination period, and the filtering unit may compare a level of the first frequency control signal for each cycle of the reference clock signal. When the first frequency control signal has been maintained at one level of the first and second levels for at least n cycles of the reference clock signal, where n is a natural number greater than or equal to two, the filtering unit may convert a level of the second frequency control signal to the one level of the first frequency control signal from an (n+1)-th cycle of the reference clock signal.
In an embodiment, when a level of the first frequency control signal is not maintained to be constant at one level of the first and second levels for the n cycles, the filtering unit may be configured to maintain a level of the second frequency control signal to be unconverted in the (n+1)-th cycle.
In an embodiment, the filtering unit may include: a signal generating unit configured to output n input signals respectively including level information of the first frequency control signal in the n cycles; a comparing unit configured to compare the n input signals to determine whether a level of the first frequency control signal remains constant for the n cycles; and an output unit configured to output, when the comparing unit determines that the level of the first frequency control signal has remained constant for the n cycles, the second frequency control signal having, in the (n+1)-th cycle, the same level as the level of the first frequency control signal.
In an embodiment, the signal generating unit may include n flip-flops configured to generate the n input signals, and n inverted signals respectively having level values inverted from level values of the n input signals.
In an embodiment, the comparing unit may include: a first NAND circuit configured to combine the n input signals to output a first comparison signal; a second NAND circuit configured to combine the n inverted signals to output a second comparison signal; and a latch unit connected to each of the first NAND circuit and the second NAND circuit, and configured to output a result signal having one of the first level and the second level on the basis of the first comparison signal and the second comparison signal.
In an embodiment, the output unit may include: a first inverter configured to output an inverted result signal having a level inverted from a level of the result signal; a second inverter configured to invert the inverted result signal to the result signal again; and an output flip-flop configured to convert, in the (n+1)-th cycle, a level of the second frequency control signal to the level of the result signal.
In an embodiment, the signal control unit may be configured to further output a plurality of blank data, the plurality of image data may be outputted in the plurality of frame periods, and the plurality of blank data may be outputted in a plurality of blank periods alternately repeated with the plurality of frame periods respectively.
In an embodiment, each of the plurality of blank data may include pattern data for the clock training, and the clock training unit may be configured to perform the clock training using the pattern data.
In an embodiment, each of the plurality of image data may include dummy data and active data, one frame period of the plurality of frame periods may be disposed between a first blank period and a second blank period, and a dummy data period included in the one frame period may be disposed to be adjacent to at least one of the first blank period or the second blank period.
An embodiment of the inventive concept provides a data driving unit including: a filtering unit configured to receive a first frequency control signal from a signal control unit, and to generate, on the basis that a level of the first frequency control signal is maintained to be constant at one level of a first level and a second level for a preset determination period, a second frequency control signal converted to have the same level as the one level. A clock training unit is configured to receive a clock signal including frequency information from the signal control unit, and to generate an internal clock signal corresponding to the clock signal while performing training of the clock signal in response to the second frequency control signal. A data converting unit is configured to convert a plurality of image data corresponding to a plurality of frame images to a plurality of data voltages in response to the internal clock signal, and to output the data voltages.
An embodiment of the inventive concept provides a method of driving a display device including outputting a clock signal having frequency information, a gate driving signal, a plurality of image data corresponding to a plurality of frame images, and a first frequency control signal for defining a plurality of frame periods in which the plurality of frame images are respectively displayed. The method further includes generating a second frequency control signal having a first level when a level of the first frequency control signal is maintained at the first level for a preset determination period, and having a second level when a level of the first frequency control signal is maintained at the second level for the determination period. The method further includes generating an internal clock signal while performing training of the clock signal in response to the second frequency control signal; converting the plurality of image data to a plurality of data voltages in response to the internal clock signal, and outputting the data voltages; outputting a gate signal in response to the gate driving signal; and displaying the plurality of frame images corresponding respectively to the plurality of data voltages in response to the gate signal.
In an embodiment, the generating of the second frequency control signal may include: generating a reference clock signal for determining the determination period; and comparing a level of the first frequency control signal for each cycle of the reference clock signal, and, when the first frequency control signal has been maintained at one level of the first and second levels for at least n cycles of the reference clock signal, where n is a natural number greater than or equal to two, converting a level of the second frequency control signal to the one level of the first frequency control signal from an (n+1)-th cycle of the reference clock signal.
In an embodiment, when a level of the first frequency control signal is not maintained to be constant at one level of the first and second levels for the n cycles, a level of the second frequency control signal is maintained to be unconverted in the (n+1)-th cycle.
The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to describe principles of the inventive concept. In the drawings:
As the inventive concept can have various changes and modifications made thereto and take many forms, specific embodiments of the inventive concept are illustrated in the accompanying drawings and are hereinafter described in detail. However, it should be understood that this is not intended to limit the inventive concept to specific disclosures, but is intended to include all changes and modifications, equivalents, and substitutes within the spirit and scope of the inventive concept.
Similar reference numerals are used for similar elements in the accompanying drawings through the specification. It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept. As used herein, the singular forms, “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It will be further understood that the term “include” or “have”, when used in this specification, specifies the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Hereinafter, exemplary embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings.
Referring to
The display panel 400 may include a plurality of gate lines GL1 to GLn, and a plurality of data lines DL1 to DLm. More specifically, the plurality of gate lines GL1 to GLn may be arranged to extend in a lateral direction and to cross each of the plurality of data lines DL1 to DLm extending in a longitudinal direction.
Additionally, the display panel 400 may include a plurality of pixels PX11 to PXnm each connected to a corresponding gate line and a corresponding data line respectively among the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm.
The signal control unit 100 may receive a plurality of input image data DATA corresponding to a plurality of frame images, and a plurality of control signals CS from the outside. The plurality of control signals CS may include, as an example, a vertical synchronization signal, a horizontal synchronization signal, a main clock signal, a data enable signal, and the like which control the plurality of input image data DATA.
The signal control unit 100 may convert a data format of the plurality of input image data DATA so as to conform to an interface specification between the signal control unit 100 and the data driving unit 300. A plurality of image data DAT with the converted data format may be supplied to the data driving unit 300.
The signal control unit 100 may output a plurality of driving signals in response to the plurality of control signals CS. The signal control unit 100 may generate a first frequency control signal SFC, a data driving signal D-CS, and a gate driving signal G-CS as the plurality of driving signals.
The data driving signal D-CS may include, as an example, an output start signal, a horizontal start signal, and the like. The data driving signal D-CS according to an embodiment of the inventive concept may include the plurality of image data DAT with the converted data format, and a clock signal CLK having frequency information.
The gate driving signal G-CS may include, as an example, a vertical start signal, a vertical clock signal, and the like. The signal output unit 100 transmits the data driving signal D-CS to the data driving unit 300, and transmits the gate driving signal G-CS to the gate driving unit 200.
The gate driving unit 200 may be connected to each of the plurality of gate lines GL1 to GLn. The gate driving unit 200 may sequentially output a plurality of gate signals respectively to the plurality of gate lines GL1 to GLn in response to the gate driving signal G-CS supplied from the signal control unit 100.
The data driving unit 300 may be connected to each of the plurality of data lines DL1 to DLm. The data driving unit 300 may convert the plurality of image data DAT to a plurality of data voltages in response to the data driving signal D-CS supplied from the signal control unit 100. Additionally, the data driving unit 300 may generate an internal clock signal from a clock signal CLK included in the plurality of image data DAT, and may output the plurality of data voltages respectively to the plurality of data lines DL1 to DLm in response to the internal clock signal.
Accordingly, the display panel 400 may output the plurality of frame images using the plurality of gate signals received from the gate driving unit 200, and the plurality of data voltages received from the data driving unit 300.
The data driving unit 300 may include a receiving unit 310, a reference clock signal generating unit 320, a signal processing unit 330, and a data converting unit 340. The signal processing unit 330 according to an embodiment of the inventive concept may include a filtering unit 331, and a clock training unit 332.
The receiving unit 310 may separate signals received from the signal control unit 100, and output the separated signals to the filtering unit 331, the clock training unit 332, and the data converting unit 340 respectively. More specifically, the receiving unit 310 may separate out the first frequency control signal SFC, and output the same to the filtering unit 331, and may extract the clock signal CLK from the plurality of image data DAT included in the data driving signal D-CS, and output the clock signal CLK to the clock training unit 332. Additionally, the receiving unit 310 may output the plurality of image data DAT to the data converting unit 340.
Although only the plurality of image data DAT and the clock signal CLK are illustrated as the data driving signal D-CS in
The reference clock signal generating unit 320 may generate a reference clock signal RCLK which becomes a reference for driving the data driving unit 300. As an example, the reference clock signal generating unit 320 may generate the reference clock signal RCLK having a preset frequency, and supply the reference clock signal RCLK to the signal processing unit 330.
The signal processing unit 330 may include the filtering unit 331 for filtering the first frequency control signal SFC, and the clock training unit 332 for generating an internal clock signal CLK′ from the clock signal CLK.
The filtering unit 331 may generate the second frequency control signal SFC′ converted from the first frequency control signal SFC on the basis of a level analysis of the first frequency control signal SFC. The first frequency control signal SFC according to an embodiment of the inventive concept may be a control signal of clock training for determining a time period for training the internal clock signal.
The filtering unit 331 may analyze a level of the first frequency control signal SFC using the reference clock signal RCLK supplied from the reference clock signal generating unit 320. As an example, the filtering unit 331 may analyze the level of the first frequency control signal SFC for a preset determination period of the reference clock signal RCLK.
More specifically, the filtering unit 331 may determine the level of the first frequency control signal SFC for each cycle 1T of the reference clock signal RCLK. In this case, the level of the first frequency control signal SFC may be a voltage level of the first frequency control signal SFC. As an example, as illustrated in
As a more specific example, when a level of the first frequency control signal SFC has been maintained at one level of the first level H and the second level L for at least n cycles of the reference clock signal RCLK, the filtering unit 331 may convert a level of the second frequency control signal SFC′ to the one level of the first frequency control signal SFC from an (n+1)-th cycle. Additionally, when a level of the first frequency control signal SFC is not maintained to be constant at one level of the first level H or the second level L for the n cycles, the filtering unit 331 may maintain a level of the second frequency control signal SFC′ to be unconverted in the (n+1)-th cycle. That is, the second frequency control signal SFC′ having a level in the (n+1)-th cycle the same as that in the n-th cycle may be generated.
Referring to
A glitch may occur in the first frequency control signal SFC due to noise (for example, electrostatic discharge (ESD)), fluctuation of input power, or the like. Particularly, a glitch phenomenon may occur in the vicinity of a falling edge at which the first frequency control signal SFC is converted from the first level H to the second level L, or in the vicinity of a rising edge at which the first frequency control signal SFC is converted from the second level L to the first level H. For ease of description, a period in which a glitch occurs in the vicinity of the falling edge is defined as a first glitch period GT-1, and a period in which a glitch occurs in the vicinity of the rising edge is defined as a second glitch period GT-2. For the first and second glitch periods GT-1 and GT-2, a level of the first frequency control signal SFC may be unstable.
First, when a level of the first frequency control signal SFC is not maintained to be constant for the preset determination period 4T in the first glitch period GT-1, this is determined as a glitch occurrence period, so that the second frequency control signal SFC′ maintained at the first level H without level conversion may be generated. Then, when the first frequency control signal SFC is maintained at the second level L at least for the preset determination period 4T after the first glitch period GT-1, the filtering unit 331 may convert the second frequency control signal SFC′ to the second level L from the next cycle.
Similarly, when a level of the first frequency control signal SFC is not maintained to be constant for the preset determination period 4T in the second glitch period GT-2, this is determined as a glitch occurrence period, so that the second frequency control signal SFC′ maintained at the second level L without level conversion may be generated. Then, when the first frequency control signal SFC is maintained at the first level H at least for the preset determination period 4T after the second glitch period GT-2, the second frequency control signal SFC′ may be converted to the first level H from the next cycle.
Accordingly, the filtering unit 331 according to an embodiment of the inventive concept may generate a glitch-free second frequency control signal SFC′ even when the glitch phenomenon occurs to the first frequency control signal SFC.
When the second frequency control signal SFC′ is generated as described, the filtering unit 331 may transmit the second frequency control signal SFC′ to the clock training unit 332.
The clock training unit 332 may perform training of the clock signal CLK supplied from the receiving unit 310 to generate the internal clock signal CLK′ by using the reference clock signal RCLK supplied from the reference clock signal generating unit 320.
The clock training unit 332 may perform clock training for generating the internal clock signal CLK′ in a preset period of the second frequency control signal SFC′ in response to the second frequency control signal SFC′. As described in detail, because the glitch-free second frequency control signal SFC′ is supplied to the clock training unit 332 through the filtering unit 331, the clock training unit 332 may perform clock training without error.
The clock training unit 332 according to an embodiment of the inventive concept may include a phase locked loop (PLL) circuit 332A as illustrated in
The clock training unit 332 may supply the internal clock signal CLK′ to the data converting unit 340.
The data converting unit 340 may sample the plurality of image data DAT provided from the receiving unit 310 in response to the internal clock signal CLK′, and may convert a plurality of sampled image data DAT′ to the plurality of data voltages. Additionally, the data converting unit 340 may output the plurality of data voltages to the plurality of data lines DL1 to DLm (see
Referring to
The signal generating unit 331A may receive the first frequency control signal SFC from the receiving unit 310 (see
The signal generating unit 331A may generate n input signals including level information of the first frequency control signal SFC for respective cycles of the n cycles of the reference clock signal RCLK. Hereinafter, description will be given of the case that n is four according to an embodiment of the inventive concept, in
Referring to
As illustrated in
The second flip-flop 12 among the first to fourth flip-flops 11, 12, 13, and 14 may receive the first input signal Q1 through a first input terminal D, and the reference clock signal RCLK through a second input terminal CK. The second flip-flop 12 may output the second input signal Q2 through a first output terminal Q, and a second inverted signal QB2 through a second output terminal QB, in response to the reference clock signal RCLK. The second inverted signal QB2 may have a level inverted from that of the second input signal Q2.
The third flip-flop 13 among the first to fourth flip-flops 11, 12, 13, and 14 may receive the second input signal Q2 through a first input terminal D, and the reference clock signal RCLK through a second input terminal CK. The third flip-flop 13 may output the third input signal Q3 through a first output terminal Q, and a third inverted signal QB3 through a second output terminal QB, in response to the reference clock signal RCLK. The third inverted signal QB3 may have a level inverted from that of the third input signal Q3.
The fourth flip-flop 14 among the first to fourth flip-flops 11, 12, 13, and 14 may receive the third input signal Q3 through a first input terminal D, and the reference clock signal RCLK through a second input terminal CK. The fourth flip-flop 14 may output the fourth input signal Q4 through a first output terminal Q, and a fourth inverted signal QB4 through a second output terminal QB, in response to the reference clock signal RCLK. The fourth inverted signal QB4 may have a level inverted from that of the fourth input signal Q4.
Accordingly, the fourth input signal Q4 may have the level information of the first frequency control signal SFC at a first cycle of the determination period 4T, the third input signal Q3 may have the level information of the first frequency control signal SFC at a second cycle of the determination period 4T, the second input signal Q2 may have the level information of the first frequency control signal SFC at a third cycle of the determination period 4T, and the first input signal Q1 may have the level information of the first frequency control signal SFC at a fourth cycle of the determination period 4T.
Referring to
More specifically, the comparing unit 331B according to an embodiment of the inventive concept may include a first NAND circuit 21, a second NAND circuit 22, and a latch unit 23 as illustrated in
The first NAND circuit 21 may combine the first to fourth input signals Q1 to Q4 to output a first comparison signal CP-1. For example, when all of the first to fourth input signals Q1 to Q4 include first level information, the first NAND circuit 21 may output the first comparison signal CP-1 having second level information.
The second NAND circuit 22 may combine the first to fourth inverted signals QB1 to QB4 to output a second comparison signal CP-2. For example, when all of the first to fourth inverted signals QB1 to QB4 include the second level information, the second NAND circuit 22 may output the second comparison signal CP-2 having the first level information.
The latch unit 23 may be connected to each of an output terminal of the first NAND circuit 21 and an output terminal of the second NAND circuit 22, and may output a result signal RS having one of a first level and a second level on the basis of the first comparison signal CP-1 and the second comparison signal CP-2. As illustrated in
More specifically, the third NAND circuit 23a may receive the first comparison signal CP-1 from the first NAND circuit 21 through a first input terminal, and receive an output signal of the fourth NAND circuit 23b through a second input terminal. The fourth NAND circuit 23b may receive the second comparison signal CP-2 from the second NAND circuit 22 through a first input terminal, and receive an output signal of the third NAND circuit 23a through a second input terminal. Additionally, the output signal of the third NAND circuit 23a may be supplied to the output unit 331C as the result signal RS.
As an example, when the first comparison signal CP-1 has the second level information, and the second comparison signal CP-2 has the first level information, the latch unit 23 may output a result signal RS having the first level.
Referring to
More specifically, the first inverter 31 may output an inverted result signal RS' having a level inverted from that of the result signal RS, and the second inverter 32 may be connected to an output terminal of the first inverter 31 to invert the inverted result signal RS' to the result signal again. The first inverter 31 and the second 32 may be configured to amplify the result signal. The first inverter 31 and the second 32 may be configured to delay the result signal so as to synchronize the result signal with the clock signal. The output flip-flop 33 may output the second frequency control signal SFC′ such that the second frequency control signal SFC′ has a level of the result signal RS from the next cycle of the preset determination period 4T.
As a more specific example, when the result signal RS has the first level, the first inverter 31 may output an inverted result signal RS' having the second level, and the second inverter 32 may output a result signal RS having the first level. The output flip-flop 33 may output the second frequency control signal SFC′ having the first level at a fifth cycle in response to modified clock signal RCLK<5>.
As described above, by determining whether a level of the first frequency control signal SFC remains constant for the n cycles of the preset determination period, and then generating the second frequency control signal SFC′, the filtering unit 331 may remove a glitch period included in the first frequency control signal SFC. To this end, by comparing the n input signals with each other, and comparing the n inverted signals having levels respectively inverted from those of the n input signals with each other, for the n cycles, the filtering unit 331 according to an embodiment of the inventive concept may effectively generate a glitch-free second frequency control signal SFC′ from the first frequency control signal SFC.
Referring to
Additionally, the signal control unit 100 according to an embodiment of the inventive concept may output a plurality of blank data BD in the plurality of blank periods BLS-1 and BLS-2. Each of the plurality of blank data BD may include pattern data CTP for clock training. Referring to
As illustrated in
The second frequency control signal SFC′ may be the first frequency control signal SFC from which the glitch phenomenon that has occurred thereto is removed. As an example, when the first frequency control signal SFC is a signal in which the glitch phenomenon has occurred at each of the falling edge and the rising edge as illustrated in
According to an embodiment of the inventive concept, even when the transition sections TRS included in the first frequency control signal SFC are delayed by the preset time IS, there may be no significant influence on an operation of the next frame.
Referring to
The active area 401 may include a plurality of pixels PX11 to PXnm defined by a plurality of gate lines GL1 to GLn, and a plurality of data lines DL1 to DLm.
The first dummy area 402a may include a plurality of dummy pixels PXD11 to PXD1m defined by a first dummy gate line GLD1, and the plurality of data lines DL1 to DLm, and the second dummy area 402b may include a plurality of dummy pixels PXD21 to PXD2m defined by a second dummy gate line GLD2, and the plurality of data lines DL1 to DLm.
The signal control unit 100 according to an embodiment of the inventive concept may include, in the plurality of image data DAT, dummy data to be respectively outputted to the first dummy area 402a and the second dummy area 402b, and output the plurality of image data DAT. For example, the signal control unit 100 may output the plurality of image data DAT including a plurality of active data to be respectively outputted to the plurality of pixels PX11 to PXnm, and the plurality of dummy data to be respectively outputted to the plurality of dummy pixels PXD11 to PXD1m, and PXD21 to PXD2m.
As a more specific example, the plurality of image data DAT according to an embodiment of the inventive concept may respectively include the at least one of dummy data or the active data. Referring to
The first and second blank periods BLS-1 and BLS-2 may be positioned respectively before and after the frame period FS-2. As a more specific example, the first dummy data period DUS-1 may be positioned between the first blank period BLS-1 and the active data period ACS, and the second dummy data period DUS-2 may be positioned between the active data period ACS and the second blank period BLS-2.
Even when the first frequency control signal SFC having the transition period TRS corresponding to the first blank period BLS-1 is delayed by the preset time IS, a delayed time period corresponding to the preset time IS may be positioned in the first dummy data period DUS-1. Accordingly, there may be no influence on an operation of the data driving unit 300 in the active period ACS.
In the description above, an embodiment is described of the second frequency control signal SFC′ which is the first frequency control signal SFC of which each of the falling and rising edges is delayed by the preset time IS. According to another embodiment of the inventive concept, however, the second frequency control signal SFC′ may be the first frequency control signal SFC of which only one of the falling and rising edges is delayed by the preset time IS.
A filtering unit according to another embodiment of the inventive concept may determine a level of the first frequency control signal SFC for a preset period of time, and then generate the second frequency control signal SFC-1 which is the first frequency control signal SFC the falling edge of which is delayed by the preset time IS. The rising edge of the second frequency control signal SFC-1 may be synchronized with the rising edge of the first frequency control signal SFC. In this case, a transition period TRS-1 of the second frequency control signal SFC-1 may be shorter than the transition period TRS of the first frequency control signal SFC.
A clock training unit may perform clock training for the transition period TRS-1 of the second frequency control signal SFC-1.
According to an embodiment of the inventive concept, even when a glitch occurs in a control signal due to noise or the like in the process of transmission from a signal control unit to a data driving unit, the data driving unit may remove the glitch included in the control signal, thereby improving driving reliability of a display device.
Although the exemplary embodiments of the inventive concept have been described herein, it is understood that various changes and modifications can be made by those skilled in the art within the spirit and scope of the inventive concept defined by the following claims or the equivalents.
Therefore, the scope of the inventive concept is defined by the following claims or the equivalents other than the foregoing detailed description.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2016-0051094 | Apr 2016 | KR | national |
