Patent Application
20250054449
Embodiments according to the present disclosure relate to a display device.
In recent years, in a field of a display device that performs image display, a planar display device in which pixels (pixel circuits) including light emitting elements are arranged in a matrix form has been rapidly spread. For the planar display device, as the light emitting element of a pixel, an organic EL display device using a so-called current drive type electro-optical element in which light emission luminance changes according to a current value flowing through the device, for example, an organic electro luminescence (EL) element utilizing a phenomenon in which light is emitted when an electric field is applied to an organic thin film has been developed and commercialized.
A power supply voltage is supplied from a power supply for driving pixels, circuits, and the like in the display device (see, for example, Patent Document 1).
However, for example, IR drop (voltage drop) may occur due to wiring resistance of the power supply wiring, and the luminance may be reduced.
Therefore, the present disclosure provides a display device capable of suppressing a decrease in luminance.
In order to solve the above problem, according to the present disclosure,
The plurality of pixels may be arranged in the pixel region,
The lead-out wiring may be provided for each of a plurality of the voltage lead-out positions on the reference voltage supply wiring, and
The display device may further include a drive unit that supplies a signal voltage corresponding to the gradation voltage to the plurality of pixels, in which
One of two of the gradation voltage generation units may supply a first gradation voltage to the gradation voltage supply wiring from a first supply position on the gradation voltage supply wiring,
The plurality of pixels may be arranged in the pixel region,
The display device may further include a drive unit that supplies a signal voltage corresponding to the gradation voltage to the plurality of pixels, in which
The lead-out wiring may further include a third lead-out wiring that supplies a voltage at the voltage lead-out position on the reference voltage supply wiring according to a position of a third pixel disposed between the first pixel and the second pixel to a third gradation voltage generation unit included in the gradation voltage generation unit.
The third gradation voltage generation unit may be disposed between the first gradation voltage generation unit and the second gradation voltage generation unit.
The lead-out wiring may supply a voltage at one of the voltage lead-out positions on the reference voltage supply wiring to the gradation voltage generation unit.
The plurality of pixels may be arranged in the pixel region,
The plurality of pixels may be arranged in the pixel region,
The plurality of pixels may be arranged in the pixel region,
The plurality of pixels may be arranged in the pixel region,
The reference voltage supply wiring may include:
The reference voltage may be a power supply voltage on a high potential side supplied to the pixel.
The reference voltage may be a power supply voltage on a low potential side supplied to the pixel.
The gradation voltage generation unit may include a plurality of resistance elements connected in series, and includes a ladder resistance circuit that outputs the gradation voltage from an end portion of each of the resistance elements on the basis of the reference voltage supplied from the lead-out wiring.
The gradation voltage generation unit may include:
Hereinafter, embodiments of a display device will be described with reference to the drawings. Although main components of the display device will be mainly described below, the display device may have a component or function that is not illustrated or described. The following description does not exclude components and functions that are not depicted or described.
Here, as a display device to which the technology of the present disclosure is applied, an active matrix type organic EL display device in which an organic EL element, which is an example of a current drive type light emitting element, is a light emitting unit (light emitting element) of a pixel (pixel circuit) will be described as an example. However, the technology of the present disclosure is not limited to application to an organic EL display device. That is, the technology of the present disclosure can be applied to all display devices in which one gradation voltage corresponding to an input digital video signal is selected from a plurality of gradation voltages generated by a gradation voltage occurrence circuit to be converted into an analog video signal, and the light emitting element is driven by the analog video signal.
As illustrated in
Furthermore, the pixel unit 20 is also a pixel region in which the plurality of pixels 10 is arranged.
The row scanning unit 30 is provided on the left side of the pixel unit 20, for example. The row scanning unit 30 includes a shift register, an address decoder, and the like, and sequentially outputs a scanning signal for selecting each pixel 10 of the pixel unit 20 in units of rows from the left side of the pixel unit 20 with respect to the scanning line 21. Note that, although the row scanning unit 30 is arranged on the left side of the pixel unit 20 here, it is also possible to arrange the row scanning unit 30 on the right side of the pixel unit 20, and it is also possible to adopt a configuration in which two row scanning units 30 are arranged on both left and right sides.
The gradation voltage generation circuit 40 generates a number of gradation voltages corresponding to the bit depth of the digital video signal input to the drive unit 50. In the example illustrated in
Further, the gradation voltage generation circuit (gradation voltage generation unit) 40 generates the gradation voltage on the basis of the first reference voltage. The first reference voltage is a voltage serving as a reference of the gradation voltage, and is a voltage supplied from the lead-out wiring 70.
Furthermore, in the example illustrated in
The drive unit 50 incorporates a digital/analog conversion circuit (hereinafter, sometimes referred to as a digital to analog converter (DAC)), and selects one gradation voltage corresponding to an input digital video signal from a plurality of gradation voltages generated by the gradation voltage generation circuit 40 to convert the gradation voltage into an analog video signal. The analog video signal output from the drive unit 50 is supplied to the pixel row selectively scanned by the row scanning unit 30 through the signal line 22, and the light emitting element of each pixel 10 of the pixel row is driven to emit light.
Furthermore, the drive unit 50 supplies a signal voltage Vsig corresponding to the gradation voltage to the plurality of pixels 10.
The IO pad 60 is arranged at a position different from the pixel unit 20, that is, the pixel region. In the example illustrated in
The power supply wiring 61 is a wiring connected between the pixel unit 20 and the IO pad 60. The power supply wiring 61 is a wiring to which the second reference voltage (reference voltage) is supplied from the IO pad (reference voltage supply unit) 60.
The lead-out wiring 70 is connected between the pixel unit 20 (pixel 10) and the gradation voltage generation circuit 40. The lead-out wiring 70 supplies the voltage of the power supply wiring (reference voltage supply wiring) 61 that supplies the second reference voltage to the pixel 10 to the gradation voltage generation circuit 40 as the first reference voltage so as to be used for generation of the gradation voltage. That is, the lead-out wiring 70 draws the power supply voltage of the pixel 10 back to the gradation voltage generation circuit 40.
In addition, in the example illustrated in
In
The pixel unit 20 (pixel region) and the IO pad 60 are arranged in a direction different from the supply direction of the signal voltage Vsig to the pixel 10. The supply direction of the signal voltage Vsig is, for example, the direction in which the signal line 22 extends, and is the up-down direction in
The IO pad 60 is disposed to the right of the pixel unit 20 and the first gradation voltage generation circuit 40A. The power supply wiring 61 electrically connected to the IO pad 60 is electrically connected to the right end of the pixel unit 20. The pixel 10 arranged on the right side of the pixel unit 20 is a pixel arranged at a position Pn relatively close to the IO pad 60 (see “Near” in
The first lead-out wiring 70A extracts the power supply voltage of the pixel 10 at the position Pn close to the IO pad 60, and supplies the power supply voltage to the first gradation voltage generation circuit 40A. The second lead-out wiring 70B extracts the power supply voltage of the pixel 10 at the position Pf far from the IO pad 60, and supplies the power supply voltage to the second gradation voltage generation circuit 40B.
The first gradation voltage generation circuit 40A and the second gradation voltage generation circuit 40B are disposed on the left and right sides of the drive unit 50. That is, the first gradation voltage generation circuit 40A and the second gradation voltage generation circuit 40B are disposed so as to sandwich the drive unit 50 therebetween.
In addition, the first gradation voltage generation circuit 40A and the second gradation voltage generation circuit 40B are electrically connected via a gradation voltage supply wiring 411. The drive unit 50 is disposed on the gradation voltage supply wiring 411. The first gradation voltage generation circuit 40A and the second gradation voltage generation circuit 40B output a gradation voltage VGx (in a case where the digital video signal is 8 bits, x=0 to 255) to the gradation voltage supply wiring 411.
The difference between the voltage extracted from the pixel 10 at the position Pn by the first lead-out wiring 70A and the voltage extracted from the pixel 10 at the position Pf by the second lead-out wiring 70B is caused by, for example, the power supply wiring 61.
The power supply wiring 61 is connected between the IO pad 60 and the pixel 10. At least a part of the power supply wiring 61 extends along a predetermined direction in the pixel region. The power supply wiring 61 supplies a power supply voltage (for example, the voltage ELVDD) from the IO pad 60 to a power supply voltage node (see
The power supply wiring 61 includes an outer peripheral power supply wiring 611 and an in-pixel power supply wiring 612.
The outer peripheral power supply wiring (first reference voltage supply wiring) 611 is disposed so as to surround the plurality of pixels 10, that is, the outer periphery of the pixel unit 20 (pixel region). The outer peripheral power supply wiring 611 is disposed in, for example, an annular shape. In the example illustrated in
The in-pixel power supply wiring (second reference voltage supply wiring) 612 is connected between the outer peripheral power supply wiring 611 and the pixel 10. The in-pixel power supply wiring 612 is arranged to extend into the pixel 10, and supplies a power supply voltage to the pixel 10. The in-pixel power supply wiring 612 is arranged, for example, in a mesh shape (lattice shape). The pixels 10 are arranged at intersections of meshes of the in-pixel power supply wiring 612. The power supply voltage nodes of the adjacent pixels 10 are connected to each other by the in-pixel power supply wiring 612.
The resistance value of the wiring resistance of the in-pixel power supply wiring 612 is higher than the resistance value of the wiring resistance of the outer peripheral power supply wiring 611. That is, the resistance value of the wiring resistance of the outer peripheral power supply wiring 611 is lower than the resistance value of the wiring resistance of the in-pixel power supply wiring 612. The outer peripheral power supply wiring 611 is thicker than the in-pixel power supply wiring 612, for example. As described above, the IO pad 60 supplies the voltage ELVDD to the power supply wiring 61 as the second reference voltage. The current flowing from the IO pad 60 to the power supply wiring 61 passes through a current path having the lowest resistance and flows into the pixel 10. Depending on the magnitude of the resistance value, the current normally passes through a current path in which the distance of the outer peripheral power supply wiring 611 is as long as possible and the distance of the in-pixel power supply wiring 612 is as short as possible. For example, the current passes through the outer peripheral power supply wiring 611 up to the pixel column of the target pixel 10, and then passes through the in-pixel power supply wiring 612 to flow to the target pixel 10. Note that the current flowing through the pixel 10 may pass through a plurality of current paths.
Here, in a case where the current passes through the outer peripheral power supply wiring 611, IR drop (voltage drop) may occur due to the wiring resistance of the outer peripheral power supply wiring 611 extending in the left-right direction in
Note that, due to the magnitude of the resistance, the current flowing in the left-right direction in
The size of the IR drop at the position on the outer peripheral power supply wiring 611 far from the IO pad 60 is represented by, for example, ΔV. As illustrated in
The fluctuation of the power supply voltage of the pixel 10 due to the IR drop may affect the driving of the pixel 10.
As illustrated in
The drive circuit that drives the organic EL element 11 includes a drive transistor 12, a sampling transistor 13, a light emission control transistor 14, a holding capacitance 15, an auxiliary capacitance 16, and an auto-zero transistor 17. Note that a P-channel transistor is used as the drive transistor 12 on the assumption that the drive transistor is formed not on an insulator such as a glass substrate but on a semiconductor such as silicon. Furthermore, in the present circuit example, P-channel transistors are also used for the sampling transistor 13, the light emission control transistor 14, and the auto-zero transistor 17, similarly to the drive transistor 12.
In the present circuit example, the pixel transistor includes a light emission control transistor 14 in addition to the drive transistor 12 and the sampling transistor 13. Therefore, in addition to the row scanning unit 30 illustrated in
In addition, the pixel transistor includes the auto-zero transistor 17. The auto-zero transistor 17 controls the organic EL element 11 not to emit light during a non-light emission period of the organic EL element 11 under driving by a drive signal from an auto-zero scanner (not illustrated).
In the pixel 10 having the above configuration, the sampling transistor 13 samples the signal voltage Vsig of the video signal supplied from the drive unit 50 through the signal line 22 under the driving by the scanning signal supplied from the row scanning unit 30, and writes the signal voltage Vsig into the pixel 10. The light emission control transistor 14 is connected in series to the drive transistor 12. More specifically, the light emission control transistor 14 is connected between a power supply voltage node (in-pixel power supply wiring 612) on the high potential side and a source electrode of the drive transistor 12, and controls light emission/non-light emission of the organic EL element 11 under driving by a light emission control signal given from the drive scanning unit. For example, the voltage ELVDD is supplied from the in-pixel power supply wiring 612 which is a power supply voltage node on the high potential side.
The holding capacitance 15 is connected between a gate electrode and a source electrode of the drive transistor 12, and holds a signal voltage Vsig written by sampling by the sampling transistor 13. The drive transistor 12 drives the organic EL element 11 to emit light by causing a drive current corresponding to the signal voltage Vsig held by the holding capacitance 15 to flow through the organic EL element 11. The auxiliary capacitance 16 is connected between the source electrode of the drive transistor 12 and a node (for example, the in-pixel power supply wiring 612) of a fixed potential. The auxiliary capacitance 16 suppresses fluctuation of the source potential of the drive transistor 12 when the signal voltage Vsig is written, and acts to set the gate-source voltage Vgs of the drive transistor 12 to the threshold voltage Vth of the drive transistor 12.
Here, since the organic EL element 11 is a current drive type light emitting element, a gradation of light emission is obtained by controlling a current value flowing through the device. In controlling the current value flowing through the organic EL element 11, the signal voltage Vsig of the video signal is written in the gate electrode of the drive transistor 12, and the overdrive voltage when the drive transistor 12 is used as a current source is controlled. The overdrive voltage is a voltage higher than a voltage for obtaining a desired gradation.
Note that, in the present circuit example, the pixel circuit including the light emission control transistor 14 in addition to the drive transistor 12 and the sampling transistor 13 has been described as an example, but the pixel circuit may have a circuit configuration not including the light emission control transistor 14.
In the example illustrated in
Therefore, as illustrated in
The lead-out wiring 70 is provided for each of the plurality of voltage lead-out positions Pv on the power supply wiring 61. The voltage lead-out position Pv is, for example, a connection position between the outer peripheral power supply wiring 611 and the lead-out wiring 70. That is, the lead-out wiring 70 is electrically connected to the power supply wiring 61 at the voltage lead-out position Pv on the power supply wiring 61. In the example illustrated in
In addition, no element such as a capacitor is provided between the power supply wiring 61 and the gradation voltage generation circuit 40. Therefore, the lead-out wiring 70 directly supplies the voltage at the voltage lead-out position Pv to the gradation voltage generation circuit 40 without an element such as a capacitor. The gradation voltage generation circuit 40 generates a gradation voltage on the basis of the reference voltage supplied from the lead-out wiring. This makes it possible to cope with direct current (DC) fluctuations in the power supply voltage of the pixel 10.
The first lead-out wiring 70A supplies the voltage at the voltage lead-out position Pv on the power supply wiring 61 corresponding to the position (position Pn) of the first pixel 10n closest to the IO pad 60 to the first gradation voltage generation circuit 40A. The first pixel 10n includes, for example, a plurality of pixels 10 in the pixel column closest to the IO pad 60.
The second lead-out wiring 70B supplies the voltage at the voltage lead-out position Pv on the power supply wiring 61 corresponding to the position (position Pf) of the second pixel 10f farthest from the IO pad 60 to the second gradation voltage generation circuit 40B. The second pixel 10f includes, for example, a plurality of pixels 10 in a pixel column farthest from the IO pad 60.
The gradation voltage generation circuit 40 is provided for each of the plurality of lead-out wirings 70. In the example illustrated in
The plurality of gradation voltage generation circuits 40 is arranged at a plurality of positions with respect to the drive unit 50 according to the plurality of voltage lead-out positions Pv with respect to the power supply wiring 61. The voltage drawn from the first pixel 10n arranged on the right side of the pixel unit 20 is supplied to the first gradation voltage generation circuit 40A arranged on the right side of the drive unit 50. The voltage drawn from the second pixel 10f arranged on the left side of the pixel unit 20 is supplied to the second gradation voltage generation circuit 40B arranged on the left side of the drive unit 50.
As illustrated in
m (for example, two to 12) signal lines 22 are connected to one selector 54. The selector 54 selects the signal line 22 as the output destination of the amplifier 53 in a time division manner (in a time division manner) to sequentially supply the signal voltage Vsig to the plurality of signal lines 22. Thus, the light emitting element of the pixel 10 is driven to emit light.
As illustrated in
The ladder resistance circuit 41 has a configuration in which resistors of a number corresponding to the bit depth of a digital video signal are connected in series between a first power supply (high potential side power supply, in the first embodiment, power supply voltage node ELVDD) and a second power supply (low potential side power supply, in the first embodiment, ground GND). In the example illustrated in
The constant current source 42 is connected between the ladder resistance circuit 41 and the ground. The constant current source 42 is connected in series with the ladder resistance circuit 41. The constant current source 42 includes a current source transistor. A reference voltage Vref is input to a gate of the current source transistor.
As illustrated in
Note that, since the second lead-out wiring 70B functions substantially similarly to the first lead-out wiring 70A, the description thereof will be omitted. The second gradation voltage generation circuit 40B functions substantially similarly to the first gradation voltage generation circuit 40A, and thus description thereof is omitted.
As illustrated in
Each of the first lead-out wiring 70A and the second lead-out wiring 70B is electrically connected to, for example, a part of the annular portion of the outer peripheral power supply wiring 611.
The first lead-out wiring 70A is electrically connected to the voltage lead-out position Pv on the outer peripheral power supply wiring 611 corresponding to the position of the first pixel 10n closest to the IO pad 60. The first lead-out wiring 70A supplies a voltage (for example, the voltage ELVDD) at the voltage lead-out position Pv on the outer peripheral power supply wiring 611 corresponding to the position of the first pixel 10n as a first reference voltage (voltage VG0A) to the first gradation voltage generation circuit 40A.
The second lead-out wiring 70B is electrically connected to the voltage lead-out position Pv on the outer peripheral power supply wiring 611 corresponding to the position of the second pixel 10f farthest from the IO pad 60. The second lead-out wiring 70B supplies a voltage (for example, the voltage ELVDD-ΔV) at the voltage lead-out position Pv on the outer peripheral power supply wiring 611 corresponding to the position of the second pixel 10f to the second gradation voltage generation circuit 40B as a first reference voltage (voltage VG0B).
The first gradation voltage generation circuit 40A generates 256 first gradation voltages VG0A to VG255A using a voltage (for example, the voltage ELVDD) supplied from the first lead-out wiring 70A as a first reference voltage (voltage VG0A).
The second gradation voltage generation circuit 40B generates 256 second gradation voltages VG0B to VG255B using a voltage (for example, the voltage ELVDD−ΔV) supplied from the second lead-out wiring 70B as a first reference voltage (voltage VG0B). That is, the second gradation voltage generation circuit 40B generates second gradation voltages VG0B to VG255B lower than first gradation voltages VG0A to VG255A according to ΔV that is the IR drop.
As described above, the drive unit 50 generates and outputs the signal voltage Vsig by selecting one gradation voltage from the plurality of gradation voltages VG0 to VG255. Therefore, the magnitude of the signal voltage Vsig also fluctuates according to the fluctuation of the gradation voltage supplied to the drive unit 50.
As illustrated in
As described with reference to
As illustrated in the upper part of
The signal voltage Vsig decreases linearly from the position Pn to the position Pf so as to follow the power supply voltage.
As illustrated in
The voltage of the gradation voltage supply wiring 411 located between the first supply position and the second supply position has a voltage level between the first gradation voltages VG0A to VG255A and the second gradation voltages VG0B to VG255B. That is, the gradation voltage applied to the gradation voltage supply wiring 411 is divided to a voltage level between the first gradation voltages VG0A to VG255A and the second gradation voltages VG0B to VG255B by the wiring resistance (resistor 412) of the gradation voltage supply wiring 411. As a result, the gradation voltage to be linearly interpolated is applied to the gradation voltage supply wiring 411 at the position between the position Pn and the position Pf. In addition, a signal voltage Vsig linearly interpolated between the position Pn and the position Pf is generated by linear interpolation of the gradation voltage. Note that, since the resistance value of the resistor 412 is usually substantially uniform, the signal voltage Vsig changes linearly.
As illustrated in the upper part of
As described above, according to the first embodiment, the lead-out wiring 70 supplies the voltage of the power supply wiring 61 that supplies the second reference voltage to the pixel 10 to the gradation voltage generation circuit 40 as the first reference voltage (voltage VG0) so as to be used for generating the gradation voltages VG0 to VG255. This makes it possible to suppress a decrease in luminance and shading due to IR drop.
Furthermore, the size of the IR drop may change depending on the amount of light emission of the pixel 10. For example, in a high luminance mode, that is, a high display rate mode, IR drop tends to be large. By suppressing a decrease in luminance due to IR drop, the maximum luminance can be improved.
Furthermore, the organic EL element 11 may be a light emitting diode (LED) element. In this case, the display device 1 is an LED display.
In addition, the magnitude of the IR drop is proportional to the magnitude of the current passing through the outer peripheral power supply wiring 611. For example, in a case where a large current flows through the outer peripheral power supply wiring 611 as in an LED display, a decrease in luminance due to IR drop tends to be large. Therefore, it is more preferable to provide the lead-out wiring 70 to suppress a decrease in luminance.
Note that, in the first embodiment, two voltage extraction positions on the outer peripheral power supply wiring 611 are positions corresponding to the first pixel 10n and the second pixel 10f, respectively. However, the present invention is not limited thereto, and the voltage extraction position may be a position of a pixel column shifted from the pixel columns of the first pixel 10n and the second pixel 10f. That is, the two voltage extraction positions may be, for example, positions corresponding to the pixel 10 on the side closer to the IO pad 60 and the pixel 10 on the side farther from the IO pad 60 in the pixel unit 20.
In addition, in the first embodiment, a case where the digital video signal has 8 bits and 256 gradation voltages VG0 to VG255 are generated is illustrated. However, the bit depth and the number of gradations are not limited to the above example.
In the example illustrated in
The power supply wiring 62 is connected between the gradation voltage generation circuit 40 and the IO pad 60. The power supply wiring 62 supplies a second reference voltage (voltage ELVDD), which is a power supply voltage supplied from the IO pad 60 to the pixel 10, to the gradation voltage generation circuit 40 as a first reference voltage so as to be used for generating the gradation voltages VG0 to VG255.
The voltage ELVDD is directly supplied from the IO pad 60 to the gradation voltage generation circuit 40 via the power supply wiring 62. Therefore, the gradation voltage generation circuit 40 generates the gradation voltage VGx on the basis of the voltage ELVDD directly supplied from the IO pad 60.
Similarly to
As illustrated in the upper part of
On the other hand, in the first embodiment, the signal voltage Vsig can be lowered to follow the power supply voltage from the position Pn to the position Pf. As a result, the gate-source voltage Vgs can be made substantially constant regardless of the in-plane position of the pixel unit 20. As a result, it is possible to suppress a decrease in luminance and shading due to IR drop.
As a second comparative example, for example, it is also conceivable to provide a dedicated arithmetic circuit that corrects the gradation voltages VG0 to VG255 on the basis of the detected power supply voltage of the pixel 10. However, in this case, an installation area for disposing a complicated arithmetic circuit is required, and thus, for example, a scale of a peripheral circuit other than the pixel region becomes large. In addition, power consumption increases.
On the other hand, in the first embodiment, the gradation voltages VG0 to VG255 can be corrected so as to follow the change in the power supply voltage of the pixel 10 by changing the arrangement of the circuits and changing the connection (routing) of the wiring. Therefore, the gradation voltages VG0 to VG255 can be automatically corrected without requiring processing such as calculation and without improving a device, a process, and the like. As a result, it is possible to suppress a decrease in luminance due to IR drop while suppressing an increase in circuit scale (chip area) and an increase in power consumption.
The pixel 10 illustrated in
In the first modification of the first embodiment, similarly to the first embodiment, the holding capacitance 15 is connected between the gate electrode and the source electrode of the drive transistor 12. In addition, a power supply voltage (for example, the voltage ELVDD) is supplied to the source electrode of the drive transistor 12 from the in-pixel power supply wiring 612 which is a power supply voltage node on the high potential side.
As in the first modification of the first embodiment, the configuration of the pixel circuit may be changed. In this case, effects similar to those of the first embodiment can be obtained.
In the second modification of the first embodiment, similarly to the first embodiment, the holding capacitance 15 is connected between the gate electrode and the source electrode of the drive transistor 12. In addition, a power supply voltage (for example, the voltage ELVDD) is supplied to the source electrode of the drive transistor 12 from the in-pixel power supply wiring 612 which is a power supply voltage node on the high potential side.
As in the second modification of the first embodiment, the configuration of the pixel circuit may be changed. In this case, effects similar to those of the first embodiment can be obtained.
In the third modification of the first embodiment, similarly to the first embodiment, the holding capacitance 15 is connected between the gate electrode and the source electrode of the drive transistor 12. In addition, a power supply voltage (for example, the voltage ELVDD) is supplied to the source electrode of the drive transistor 12 from the in-pixel power supply wiring 612 which is a power supply voltage node on the high potential side.
As in the third modification of the first embodiment, the configuration of the pixel circuit may be changed. In this case, effects similar to those of the first embodiment can be obtained.
In the fourth modification of the first embodiment, similarly to the first embodiment, the holding capacitance 15 is connected between the gate electrode and the source electrode of the drive transistor 12. In addition, a power supply voltage (for example, the voltage ELVDD) is supplied to the source electrode of the drive transistor 12 from the in-pixel power supply wiring 612 which is a power supply voltage node on the high potential side.
As in the fourth modification of the first embodiment, the configuration of the pixel circuit may be changed. In this case, effects similar to those of the first embodiment can be obtained.
In the fifth modification of the first embodiment, similarly to the first embodiment, the holding capacitance 15 is connected between the gate electrode and the source electrode of the drive transistor 12. In addition, a power supply voltage (for example, the voltage ELVDD) is supplied to the source electrode of the drive transistor 12 from the in-pixel power supply wiring 612 which is a power supply voltage node on the high potential side.
As in the fifth modification of the first embodiment, the configuration of the pixel circuit may be changed. In this case, effects similar to those of the first embodiment can be obtained.
The lead-out wiring 70 is electrically connected to the voltage lead-out position Pv on the outer peripheral power supply wiring 611 corresponding to the position of the second pixel 10f farthest from the IO pad 60.
The lead-out wiring 70 supplies a voltage at one voltage lead-out position Pv on the power supply wiring 61 to the gradation voltage generation circuit 40. The lead-out wiring 70 supplies a voltage (for example, the voltage ELVDD−ΔV) at the voltage lead-out position Pv on the power supply wiring 61 corresponding to the position of the second pixel 10f farthest from the IO pad 60 to the gradation voltage generation circuit 40.
The gradation voltage generation circuit 40 is disposed on the left side of the drive unit 50. The gradation voltage generation circuit 40 uses the voltage (for example, the voltage ELVDD−ΔV) supplied from the lead-out wiring 70 as the first reference voltage (voltage VG0) to generate 256 gradation voltages VG0 to VG255.
Here, since there is one gradation voltage generation circuit 40, the drive unit 50 supplies the signal voltage Vsig based on the gradation voltages VG0 to VG255 to all the signal lines 22 regardless of the position from the IO pad 60. Therefore, the drive unit 50 also supplies the signal voltage Vsig based on the gradation voltages VG0 to VG255 to the signal line 22 arranged at the position Pn close to the IO pad 60.
As illustrated in the upper part of
In this case, similarly to the comparative example, the gate-source voltage Vgs narrows from the position Pn to the position Pf, and the luminance decreases. However, the gate-source voltage Vgs of the entire display surface is larger than that of the comparative example. Therefore, the decrease in luminance is suppressed, and the luminance can be improved in the entire display surface.
As in the second embodiment, one lead-out wiring 70 and one gradation voltage generation circuit 40 may be provided. In this case, effects similar to those of the first embodiment can be obtained. Note that the second embodiment may be combined with the first to fifth modifications of the first embodiment.
The drive unit 50 is divided into two drive units 50A and 50B at substantially the center.
The lead-out wiring 70 is electrically connected to the voltage lead-out position Pv on the outer peripheral power supply wiring 611 corresponding to the position (position Pc) of the pixel 10 disposed between the first pixel 10n and the second pixel 10f. The position Pc indicates, for example, a substantially central portion (position near the center) of the pixel unit 20 (pixel region).
The lead-out wiring 70 supplies the voltage (for example, the voltage ELVDD−ΔV/2) at the voltage lead-out position Pv on the power supply wiring 61 corresponding to the position of the pixel 10 arranged between the first pixel 10n closest to the IO pad 60 and the second pixel 10f farthest from the IO pad 60 to the gradation voltage generation circuit 40.
The gradation voltage generation circuit 40 is disposed between the drive unit 50A and the drive unit 50B. The gradation voltage generation circuit 40 uses the voltage (for example, the voltage ELVDD−ΔV/2) supplied from the lead-out wiring 70 as the first reference voltage (voltage VG0) to generate 256 gradation voltages VG0 to VG255.
As illustrated in the upper part of
In the third embodiment, similarly to the second embodiment, luminance can be improved over the entire display surface. Note that, in the third embodiment, improvement in luminance is small as compared with the second embodiment.
As in the third embodiment, the voltage extraction position of the lead-out wiring 70 and the arrangement of the gradation voltage generation circuit 40 may be changed. In this case, effects similar to those of the second embodiment can be obtained. Note that the third embodiment may be combined with the first to fifth modifications of the first embodiment.
The variation in the wiring resistance of the outer peripheral power supply wiring 611 illustrated in
In the example illustrated in
Therefore, as illustrated in
The drive unit 50 is divided into two drive units 50A and 50B at substantially the center.
The lead-out wiring 70 further includes a third lead-out wiring 70C. The third lead-out wiring 70C is electrically connected to the voltage lead-out position Pv on the outer peripheral power supply wiring 611 according to the position (position Pc) of the pixel 10 arranged between the first pixel 10n and the second pixel 10f.
The third lead-out wiring 70C supplies the voltage at the voltage lead-out position Pv on the power supply wiring 61 corresponding to the position (position Pc) of the pixel 10 arranged between the first pixel 10n and the second pixel 10f to the third gradation voltage generation circuit 40C as a first reference voltage (voltage VG0C).
The gradation voltage generation circuit 40 further includes a third gradation voltage generation circuit 40C. The third gradation voltage generation circuit 40C is disposed between the first gradation voltage generation circuit 40A and the second gradation voltage generation circuit 40B.
The third gradation voltage generation circuit 40C is disposed between the drive unit 50A and the drive unit 50B. The third gradation voltage generation circuit 40C generates 256 third gradation voltages VG0C to VG255C with the voltage supplied from the third lead-out wiring 70C as a first reference voltage (voltage VG0C).
As illustrated in the upper part of
The third lead-out wiring 70C extracts the power supply voltage at the position Pc greatly decreased from the voltage ELVDD by the IR drop, and supplies the power supply voltage to the third gradation voltage generation circuit 40C. As described in the first embodiment, the signal voltage Vsig is linearly interpolated. For example, the signal voltage Vsig is linearly interpolated between the position Pn and the position Pc. The signal voltage Vsig is linearly interpolated between the position Pc and the position Pf.
The signal voltage Vsig greatly decreases linearly from the position Pn to the position Pc so as to follow the power supply voltage. The signal voltage Vsig linearly slightly decreases from the position Pc to the position Pf so as to follow the power supply voltage. That is, the signal voltage Vsig follows the power supply voltage over the entire display surface.
As illustrated in the upper part of
In the fourth embodiment, the signal voltage Vsig can be changed so as to follow a local change in the power supply voltage. This makes it possible to suppress a local fluctuation in luminance. As a result, for example, it is possible to further suppress a decrease in the uniformity of the image quality with respect to the display pattern in which the display rate is biased in the display surface.
In addition, four or more lead-out wirings 70 and four or more gradation voltage generation circuits 40 may be provided. As the number of lead-out wirings 70 and the number of gradation voltage generation circuits 40 increase, a local fluctuation in luminance can be further suppressed.
As in the fourth embodiment, three lead-out wirings 70 and three gradation voltage generation circuits 40 may be provided. In this case, effects similar to those of the first embodiment can be obtained. Note that the fourth embodiment may be combined with the first to fifth modifications of the first embodiment.
The pixel unit 20 (pixel region) and the IO pad 60 are arranged side by side in the supply direction of the signal voltage Vsig to the pixel 10. The supply direction of the signal voltage Vsig is the up-down direction in
In the example illustrated in
Similarly to the second embodiment, the lead-out wiring 70 is electrically connected to the voltage lead-out position Pv on the outer peripheral power supply wiring 611 corresponding to the position of the second pixel 10f farthest from the IO pad 60.
The lead-out wiring 70 supplies a voltage (for example, the voltage ELVDD−ΔV) at the voltage lead-out position Pv on the power supply wiring 61 corresponding to the position of the second pixel 10f to the gradation voltage generation circuit 40 as a first reference voltage (voltage VG0).
The gradation voltage generation circuit 40 is disposed on the right side of the drive unit 50. The gradation voltage generation circuit 40 uses the voltage (for example, the voltage ELVDD−ΔV) supplied from the lead-out wiring 70 as the first reference voltage (voltage VG0) to generate 256 gradation voltages VG0 to VG255.
As described with reference to
As in the fifth embodiment, the position of the IO pad 60 may be changed. In this case, effects similar to those of the second embodiment can be obtained. Note that the fifth embodiment may be combined with the first to fifth modifications of the first embodiment. Further, the lead-out wiring 70 may lead out the power supply voltage of the pixel 10 at the position Pc instead of the position Pf. That is, the third embodiment may be combined with the fifth embodiment.
In the organic EL element 11, an anode electrode is connected to a common power supply wiring 24 wired in common for all the pixels 10.
The drive circuit that drives the organic EL element 11 includes a drive transistor 12, a sampling transistor 13, and a holding capacitance 15. An N-channel transistor is used as the drive transistor 12. Therefore, to the source electrode of the drive transistor 12, a power supply voltage (for example, the voltage ELVSS) is supplied from the in-pixel power supply wiring 612 which is a power supply voltage node on the low potential side. Furthermore, in the present circuit example, an N-channel transistor is also used for the sampling transistor 13, similarly to the drive transistor 12.
In the example illustrated in
In a case where the drive transistor 12 is an N-channel transistor, the power supply voltage on the low potential side increases from the position Pn to the position Pf by IR drop.
The first lead-out wiring 70A supplies a voltage (for example, the voltage ELVSS) at the voltage lead-out position Pv on the outer peripheral power supply wiring 611 corresponding to the position of the first pixel 10n as a first reference voltage (voltage VG0A) to the first gradation voltage generation circuit 40A.
The first gradation voltage generation circuit 40A generates 256 first gradation voltages VG0A to VG255A using a voltage (for example, the voltage ELVSS) supplied from the first lead-out wiring 70A as a first reference voltage (voltage VG0A). Note that the voltage VG0A is the lowest voltage among the first gradation voltages VG0A to VG255A.
The ladder resistance circuit 41 is configured to be connected in series between a first power supply (low potential side power supply, in the sixth embodiment, power supply voltage node ELVSS) and a second power supply (high potential side power supply, in the sixth embodiment, the power supply voltage node ELVDD). In the example illustrated in
Note that, since the second lead-out wiring 70B functions substantially similarly to the first lead-out wiring 70A, the description thereof will be omitted. The second gradation voltage generation circuit 40B functions substantially similarly to the first gradation voltage generation circuit 40A, and thus description thereof is omitted.
As in the sixth embodiment, the conductivity type of the drive transistor 12 may be changed, and the power supply voltage of the pixel 10 drawn back to the first gradation voltage generation circuit 40A and the second gradation voltage generation circuit 40B may be changed. In this case, effects similar to those of the first embodiment can be obtained. Note that the sixth embodiment may be combined with the second to fifth embodiments, or may be combined with the first to fifth modifications of the first embodiment.
The first gradation voltage generation circuit 40A generates a gradation voltage by a ramp waveform method. The first gradation voltage generation circuit 40A includes a ramp wave voltage generation unit 43, a voltage follower 44, a timing control unit 45, and a timing switch 46.
The ramp wave voltage generation unit 43 generates a ramp wave voltage whose voltage level changes with time on the basis of the first reference voltage. The ramp wave voltage generation unit 43 includes a capacitance 431, a voltage supply switch 432, and a constant current source 433.
The capacitance 431 is connected between the node N and the high-potential-side power supply node. The capacitance 431 holds the voltage (for example, the voltage ELVDD) drawn back from the first lead-out wiring 70A.
The voltage supply switch 432 is connected between the node N and the lead-out wiring 70. When the voltage supply switch 432 is turned on, the voltage (for example, the voltage ELVDD) drawn back from the first lead-out wiring 70A is written into the capacitance 431.
The constant current source 433 is connected between the node N and the ground. When the constant current source 433 is driven, the capacitance 431 is discharged at a constant current. As a result, a ramp wave voltage having a substantially constant slope with the lapse of time is generated.
The voltage follower 44 is connected between the node N and the ramp wiring (RAMP_OUT) 47. The voltage follower 44 outputs the ramp wave voltage to the ramp wiring 47.
The timing control unit 45 generates the gradation voltage by controlling the timing of supplying the ramp wave voltage on the basis of the luminance of the plurality of pixels 10. More specifically, the timing control unit 45 controls the timing switch at a timing corresponding to the luminance of the plurality of pixels 10. That is, the timing control unit 45 receives the digital video signal, and controls the plurality of timing switches 46 at a timing corresponding to the digital video signal. The timing control unit 45 selects the signal voltage Vsig corresponding to the gradation at the timing of turning off the timing switch 46.
The plurality of timing switches 46 is connected between the ramp wiring 47 and each of the plurality of signal lines 22. The timing switch 46 is controlled by the timing control unit 45, and outputs the signal voltage Vsig to the signal line 22.
Note that, since the second lead-out wiring 70B functions substantially similarly to the first lead-out wiring 70A, the description thereof will be omitted. The second gradation voltage generation circuit 40B functions substantially similarly to the first gradation voltage generation circuit 40A, and thus description thereof is omitted.
In the initial state, the voltage of the ramp wiring 47 is the first reference voltage (for example, the voltage ELVDD) supplied by the first lead-out wiring 70A. In addition, the timing switch 46 is in an on state.
Next, at time t1, the constant current source 433 operates. As a result, as illustrated in
Next, at time t2, the timing control unit 45 turns off the timing switch 46. A predetermined gradation voltage VG [xx] is selected at a predetermined timing T_VG [xx] at which the timing switch 46 is turned off. As a result, the signal voltage Vsig corresponding to the digital video signal is supplied to the signal line 22.
As in the seventh embodiment, the configurations of the first gradation voltage generation circuit 40A and the second gradation voltage generation circuit 40B may be changed. In this case, effects similar to those of the first embodiment can be obtained. Note that the seventh embodiment may be combined with the second to sixth embodiments, or may be combined with the first to fifth modifications of the first embodiment.
The display device 1 according to the present disclosure can be mounted on various electronic apparatuses.
The vehicle 100 in
The center display 101 is arranged on a dashboard 107 at a location facing a driver seat 108 and a passenger seat 109.
The safety-related information is information of doze sensing, looking-away sensing, sensing of mischief of a child riding together, presence or absence of wearing of a seat belt, sensing of leaving of an occupant, and the like, and is information sensed by the sensor arranged to overlap with a back surface side of the center display 101, for example. The operation-related information senses a gesture related to an operation by the occupant by using the sensor. The sensed gestures may include an operation of various types of equipment in the vehicle 100. For example, operations of air conditioning equipment, a navigation device, an audiovisual (AV) device, a lighting device, and the like are detected. The life log includes life logs of all the occupants. For example, the life log includes an action record of each occupant in the vehicle. By acquiring and storing the life log, it is possible to check a state of the occupant at a time of an accident. In the health-related information, the health condition of the occupant is estimated on the basis of the body temperature of the occupant detected by using a temperature sensor. Alternatively, the face of the occupant may be imaged by using an image sensor, and the health condition of the occupant may be estimated from the imaged facial expression. Further, a conversation may be made with an occupant in automatic voice, and the health condition of the occupant may be estimated on the basis of the contents of a response from the occupant. The authentication/identification-related information includes a keyless entry function of performing face authentication using a sensor, a function of automatically adjusting a seat height and position through face identification, and the like. The entertainment-related information includes a function of detecting, with a sensor, operation information about an AV device being used by an occupant, a function of recognizing the face of the occupant with sensor and providing content suitable for the occupant through the AV device, and the like.
The console display 102 can be used, for example, to display the life log information. The console display 102 is disposed near a shift lever 111 of a center console 110 between the driver seat 108 and the passenger seat 109. The console display 102 can also display information sensed by the various sensors. Furthermore, the console display 102 may display an image of the surroundings of the vehicle captured by an image sensor, or may display an image of a distance to an obstacle present in the surroundings of the vehicle.
The head-up display 103 is virtually displayed behind a windshield 112 in front of the driver seat 108. The head-up display 103 can be used to display, for example, at least one of the safety-related information, the operation-related information, the life log, the health-related information, the authentication/identification-related information, or the entertainment-related information. Since the head-up display 103 is virtually arranged in front of the driver seat 108 in many cases, the head-up display 103 is suitable for displaying information directly related to an operation of the vehicle 100, such as a speed of the vehicle 100 and a remaining amount of fuel (battery).
The digital rear mirror 104 can also display a state of the occupant in the rear seat in addition to the rear side of the vehicle 100, and thus can be used to display the life log information, for example, by disposing the sensor to overlap with a back surface side of the digital rear mirror 104.
The steering wheel display 105 is arranged near the center of a steering wheel 113 of the vehicle 100. The steering wheel display 105 can be used to display, for example, at least one of the safety-related information, the operation-related information, the life log, the health-related information, the authentication/identification-related information, or the entertainment-related information. In particular, since the steering wheel display 105 is close to the driver's hand, the steering wheel display 105 is suitable for displaying the life log information such as the body temperature of the driver, or for displaying information regarding an operation of the AV device, air conditioning equipment, or the like.
The rear entertainment display 106 is attached to the back side of the driver seat 108 and the passenger seat 109, and is for the occupant in the rear seat to view. The rear entertainment display 106 can be used to display, for example, at least one of the safety-related information, the operation-related information, the life log, the health-related information, the authentication/identification-related information, or the entertainment-related information. In particular, since the rear entertainment display 106 is in front of the occupant in the rear seat, information related to the occupant in the rear seat is displayed. For example, information regarding an operation of the AV device or the air conditioning equipment may be displayed, or a result of measurement of the body temperature or the like of an occupant in the rear seat with a temperature sensor may be displayed.
The display device 1 according to the present disclosure can be applied to the center display 101, the console display 102, the head-up display 103, the digital rear mirror 104, the steering wheel display 105, and the rear entertainment display 106.
The display device 1 according to the present disclosure can be applied not only to various displays used in vehicles but also to displays mounted on various electronic apparatuses.
In the camera in
By applying the display device 1 according to the present disclosure to the monitor screen 126, the electronic viewfinder 124, the sub screen, and the like used for the camera, it is possible to reduce the cost and improve the display quality.
The display device 1 according to the present disclosure is also applicable to a head-mounted display (hereinafter, referred to as an HMD). The HMD can be used for virtual reality (VR), augmented reality (AR), mixed reality (MR), substitutional reality (SR), or the like.
Furthermore, a camera may be provided in the HMD 130 to capture an image around the wearer, and an image obtained by combining the image captured by the camera and an image generated by a computer may be displayed on the display device 132. For example, by arranging the camera to overlap with the back surface side of the display device 132 visually recognized by the wearer of the HMD 130, capturing an image of the surroundings of the eyes of the wearer with the camera, and displaying the captured image on another display provided on the outer surface of the HMD 130, a person around the wearer can obtain expression of the face and a movement of the eyes of the wearer in real time.
Note that various types of the HMD 130 are conceivable. For example, as illustrated in
The display device 1 according to the present disclosure can also be applied to a television device (hereinafter referred to as a TV).
As described above, according to the display device 1 of the present disclosure, the TV 330 with low cost and excellent display quality can be realized.
The display device 1 according to the present disclosure can also be applied to a smartphone and a mobile phone.
Note that the present technology may have the following configurations.
(1)
A display device including:
The display device according to (1), in which
The display device according to (1) or (2), in which
The display device according to (3), further including a drive unit that supplies a signal voltage corresponding to the gradation voltage to the plurality of pixels, in which
The display device according to (3) or (4), in which
The display device according to any one of (3) to (5), in which
The display device according to (6), further including a drive unit that supplies a signal voltage corresponding to the gradation voltage to the plurality of pixels, in which
The display device according to (6) or (7), in which the lead-out wiring further includes a third lead-out wiring that supplies a voltage at the voltage lead-out position on the reference voltage supply wiring according to a position of a third pixel disposed between the first pixel and the second pixel to a third gradation voltage generation unit included in the gradation voltage generation unit.
(9)
The display device according to (8), in which the third gradation voltage generation unit is disposed between the first gradation voltage generation unit and the second gradation voltage generation unit.
(10)
The display device according to (1) or (2), in which the lead-out wiring supplies a voltage at one of the voltage lead-out positions on the reference voltage supply wiring to the gradation voltage generation unit.
(11)
The display device according to (10), in which
The display device according to (10), in which
The display device according to any one of (1) to (12), in which
The display device according to any one of (1) to (12), in which
The display device according to any one of (1) to (14), in which
The display device according to any one of (1) to (15), in which the reference voltage is a power supply voltage on a high potential side supplied to the pixel.
(17)
The display device according to any one of (1) to (15), in which the reference voltage is a power supply voltage on a low potential side supplied to the pixel.
(18)
The display device according to any one of (1) to (17), in which the gradation voltage generation unit includes a plurality of resistance elements connected in series, and includes a ladder resistance circuit that outputs the gradation voltage from an end portion of each of the resistance elements on the basis of the reference voltage supplied from the lead-out wiring.
(19)
The display device according to any one of (1) to (17), in which
Aspects of the present disclosure are not limited to the above-described individual embodiments, but include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. That is, various additions, modifications, and partial deletions are possible without departing from the conceptual idea and spirit of the present disclosure derived from the matters defined in the claims and equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-206117 | Dec 2021 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/040060 | 10/27/2022 | WO |
