Patent Application
20190331974
The present invention relates to a display device, and more particularly to a display device having a display region with a shape other than rectangular (typically, a right-angled U-shaped display region).
In general, a plurality of source bus lines (video signal lines) and a plurality of gate bus lines (scanning signal lines) are disposed in a display region (display unit) of a liquid crystal display device, and pixel formation portions which form pixels are provided near intersections of the source bus lines and the gate bus lines. Each pixel formation portion includes a thin film transistor (TFT) which is a switching element connected at its gate terminal to a gate bus line passing through a corresponding intersection and connected at its source terminal to a source bus line passing through the intersection; a pixel capacitance for holding a pixel voltage value; and the like. The liquid crystal display device is also provided with a gate driver (scanning signal line drive circuit) for driving the gate bus lines; and a source driver (video signal line drive circuit) for driving the source bus lines.
A conventional general liquid crystal display device has a rectangular display region. However, in recent years, the development of liquid crystal display devices having a display region with a shape other than rectangular, such as liquid crystal display devices for watch applications and liquid crystal display devices for in-vehicle applications, has progressed. Such display devices are called “variant-form displays”.
Regarding display devices for watch applications, there is one having a non-display region inside a display region. An invention related to such a display device is disclosed in, for example, Japanese Laid-Open Patent Publication No. 2008-257191. A display device disclosed in Japanese Laid-Open Patent Publication No. 2008-257191 is provided with bypass wiring lines in a part of a non-display region so that gate bus lines disposed in a display region on the left side of the non-display region and gate bus lines disposed in a display region on the right side of the non-display region can be driven by one gate driver.
In addition, in relation to the present invention, the following prior art documents are also known. Japanese Laid-Open Patent Publication No. 2008-292995 discloses a configuration in which circuit units (at least either one of gate drivers and source drivers) are arranged along the periphery of a non-rectangular display region. FIGS. 16 to 18 of Japanese Laid-Open Patent Publication No. 2002-014366 disclose examples of the arrangement of a gate driver regarding a variant-form display. Note that a configuration using bypass wiring lines is also disclosed in Japanese Laid-Open Patent Publication No. 2010-054980.
[Patent Document 1] Japanese Laid-Open Patent
Publication No. 2008-257191
[Patent Document 2] Japanese Laid-Open Patent Publication No. 2008-292995 [Patent Document 3] Japanese Laid-Open Patent
Publication No. 2002-014366
[Patent Document 4] Japanese Laid-Open Patent Publication No. 2010-054980
Meanwhile, regarding display devices other than display devices for watch applications, too, a shape is considered in which a non-display region is provided between display regions for when attention is focused on a direction in which gate bus lines extend. For example, a display device having a right-angled U-shaped display region as viewed from the top as shown in
Now, regarding a display device having a right-angled U-shaped display region, a configuration for driving gate bus lines is considered. Note that it is assumed that a plurality of gate bus lines are alternately driven one by one from both left and right sides of the display region. In this case, for example, as shown in
When bypass wiring lines such as those described above are used, a picture-frame for disposing the bypass wiring lines is provided in a recessed portion 940. In
An object of the present invention is therefore to achieve a narrower picture-frame than those of conventional displays, regarding a variant-form display (typically, a display device having a shape in which a non-display region is provided between display regions).
A first aspect of the present invention is directed to a display device having a non-rectangular display region in which scanning signal lines are disposed, the display device including:
at least one pair of scanning signal line driving units including a first-type scanning signal line drive circuit configured to drive a relatively large number of scanning signal lines; and a second-type scanning signal line drive circuit configured to drive a relatively small number of scanning signal lines, wherein
regarding the first-type scanning signal line drive circuit and the second-type scanning signal line drive circuit in a pair,
According to a second aspect of the present invention, in the first aspect of the present invention,
the display region includes:
regarding the first-type scanning signal line drive circuit and the second-type scanning signal line drive circuit in a pair,
According to a third aspect of the present invention, in the second aspect of the present invention,
the second-type scanning signal line drive circuit is provided in a non-display region between the two narrow-width regions, and
a width of the second-type scanning signal line drive circuit in a direction in which the scanning signal lines extend is smaller than a width of a bypass wiring line region required when it is assumed that bypass wiring lines are disposed in the non-display region, the bypass wiring lines connecting the scanning signal lines disposed in the two narrow-width regions.
According to a fourth aspect of the present invention, in the third aspect of the present invention,
the width of the bypass wiring line region is found by a following equation:
Wr=Wg×2×Nr
where Wr represents the width of the bypass wiring line region, Wg represents a width of one bypass wiring line, and Nr represents a number of the bypass wiring lines for when it is assumed that the bypass wiring lines are disposed.
According to a fifth aspect of the present invention, in the second aspect of the present invention,
bypass wiring lines connecting some of the scanning signal lines disposed in the two narrow-width regions are disposed in a non-display region between the two narrow-width regions, and
the scanning signal lines connected to the bypass wiring lines are driven by the first-type scanning signal line drive circuit.
According to a sixth aspect of the present invention, in the fifth aspect of the present invention,
a width of a bypass wiring line region in which the bypass wiring lines are disposed is smaller than a width of the second-type scanning signal line drive circuit in a direction in which the scanning signal lines extend.
According to a seventh aspect of the present invention, in the sixth aspect of the present invention,
the width of the bypass wiring line region is found by a following equation:
Wr=Wg×2×Nr
where Wr represents the width of the bypass wiring line region, Wg represents a width of one bypass wiring line, and Nr represents a number of the bypass wiring lines disposed in the bypass wiring line region.
According to an eighth aspect of the present invention, in the second aspect of the present invention,
the timing control signals are provided to the first-type scanning signal line drive circuit and the second-type scanning signal line drive circuit in a pair, using a same signal wiring line.
According to a ninth aspect of the present invention, in the second aspect of the present invention,
the timing control signals are provided to the first-type scanning signal line drive circuit and the second-type scanning signal line drive circuit in a pair, using different signal wiring lines not passing through a non-display region between the two narrow-width regions.
According to a tenth aspect of the present invention, in the second aspect of the present invention,
scanning signal lines earlier in scanning order than the scanning signal lines disposed in the two narrow-width regions are disposed in the wide-width region, and
a scanning signal is provided as a scanning start signal to the second-type scanning signal line drive circuit, the scanning signal being outputted by the first-type scanning signal line drive circuit to a scanning signal line disposed in the wide-width region.
According to an eleventh aspect of the present invention, in the second aspect of the present invention,
the display device includes two pairs of scanning signal line driving units,
the scanning signal lines disposed in the wide-width region are alternately driven one by one by a first-type scanning signal line drive circuit included in one of the two pairs of scanning signal line driving units and a first-type scanning signal line drive circuit included in the other one of the two pairs of scanning signal line driving units,
the scanning signal lines disposed in one of the two narrow-width regions are alternately driven one by one by a first-type scanning signal line drive circuit included in one of the two pairs of scanning signal line driving units and a second-type scanning signal line drive circuit included in the other one of the two pairs of scanning signal line driving units, and
the scanning signal lines disposed in the other one of the two narrow-width regions are alternately driven one by one by a second-type scanning signal line drive circuit included in the one of the two pairs of scanning signal line driving units and a first-type scanning signal line drive circuit included in the other one of the two pairs of scanning signal line driving units.
According to a twelfth aspect of the present invention, in the second aspect of the present invention,
the display device includes a pair of scanning signal line driving units,
the scanning signal lines disposed in the wide-width region and the scanning signal lines disposed in one of the two narrow-width regions are sequentially driven one by one by the first-type scanning signal line drive circuit, and
the scanning signal lines disposed in the other one of the two narrow-width regions are sequentially driven one by one by the second-type scanning signal line drive circuit.
According to a thirteenth aspect of the present invention, in the second aspect of the present invention,
the display device includes two pairs of scanning signal line driving units,
the scanning signal lines disposed in the wide-width region are sequentially driven one by one by both of a first-type scanning signal line drive circuit included in one of the two pairs of scanning signal line driving units and a first-type scanning signal line drive circuit included in the other one of the two pairs of scanning signal line driving units,
the scanning signal lines disposed in one of the two narrow-width regions are sequentially driven one by one by both of a first-type scanning signal line drive circuit included in one of the two pairs of scanning signal line driving units and a second-type scanning signal line drive circuit included in the other one of the two pairs of scanning signal line driving units, and
the scanning signal lines disposed in the other one of the two narrow-width regions are sequentially driven one by one by both of a second-type scanning signal line drive circuit included in the one of the two pairs of scanning signal line driving units and a first-type scanning signal line drive circuit included in the other one of the two pairs of scanning signal line driving units.
According to a fourteenth aspect of the present invention, in the first aspect of the present invention,
the first-type scanning signal line drive circuit and the second-type scanning signal line drive circuit include transistors used to drive the scanning signal lines, and
in each of the scanning signal line drive circuits, the transistors have different sizes depending on wiring line loads of scanning signal lines to be driven.
According to the first aspect of the present invention, a display device having a non-rectangular display region can adopt a configuration in which scanning signal lines which are conventionally driven by providing bypass wiring lines are driven by the second-type scanning signal line drive circuit. Here, by providing the second-type scanning signal line drive circuit while considering the number of scanning signal lines in each region, a picture-frame region can be reduced over conventional displays.
According to the second aspect of the present invention, even if there are a large number of scanning signal lines disposed in the two narrow-width regions, the area of a picture-frame region required for a non-display region (a region where bypass wiring lines are conventionally disposed) between the two narrow-width regions can be reduced over conventional displays. As such, a display device having a display region including a wide-width region and two narrow-width regions achieves a narrower picture-frame than conventional displays.
According to the third aspect of the present invention, the area of a picture-frame region can be securely reduced compared with a configuration in which bypass wiring lines are provided.
According to the fourth aspect of the present invention, the same effect as that of the third aspect of the present invention can be obtained.
According to the fifth aspect of the present invention, by suitably combining the second-type scanning signal line drive circuit and bypass wiring lines, a narrow picture-frame can be more effectively achieved.
According to the sixth aspect of the present invention, the area of a picture-frame region can be securely reduced compared with a configuration in which only the second-type scanning signal line drive circuit is provided in a non-display region between the two narrow-width regions.
According to the seventh aspect of the present invention, the same effect as that of the sixth aspect of the present invention can be obtained.
According to the eighth aspect of the present invention, in a region around the display region, the area for the scanning signal line drive circuits can be reduced. By this, a narrow picture-frame in the region around the display region can be achieved.
According to the ninth aspect of the present invention, wiring lines for the timing control signals are not provided in the non-display region between the two narrow-width regions. Hence, a narrow picture-frame is effectively achieved in a conventional bypass wiring line region.
According to the tenth aspect of the present invention, since a wiring line for a scanning start signal to be provided to the second-type scanning signal line drive circuit is not required, a narrow picture-frame is more effectively achieved.
According to the eleventh aspect of the present invention, since scanning signals are alternately provided to a plurality of scanning signal lines one by one from one end and the other end of each scanning signal line, bias in the waveform rounding of scanning signals is suppressed.
According to the twelfth aspect of the present invention, the number of scanning signal line drive circuits can be reduced compared with a configuration in which staggered driving is adopted or a configuration in which both-side driving is adopted. Hence, a narrow picture-frame is more effectively achieved.
According to the thirteenth aspect of the present invention, a scanning signal is provided to each scanning signal line from both of one end and the other end of the scanning signal line. Hence, the waveform rounding of a scanning signal at a middle portion of each scanning signal line is suppressed.
According to the fourteenth aspect of the present invention, each scanning signal line drive circuit is provided with transistors of sizes determined depending on the wiring line loads of scanning signal lines to be driven. Hence, consistency between a wiring line load and a driving capability can be achieved. As a result, an effect of power consumption optimization and an effect of a reduction in non-uniformity of display which occurs due to a difference in scanning signal waveform caused by a difference in wiring line load can be obtained.
Embodiments of the present invention will be described below with reference to the accompanying drawings.
<1.1 Overall Configuration and Overview of Operation>
A plurality of source bus lines (video signal lines) SL and a plurality of gate bus lines (scanning signal lines) GL are disposed in the display region 400. In the display region 400, pixel formation portions which form pixels are provided at intersections of the source bus lines SL and the gate bus lines GL.
The operation of the components shown in
The gate driver 200 repeats application of an active scanning signal to each gate bus line GL, based on the gate control signals GCTL outputted from the display control circuit 100, with one vertical scanning period as a cycle. Note that a detailed description of the gate driver 200 will be made later.
The source driver 300 receives the digital video signals DV and source control signals SCTL outputted from the display control circuit 100, and applies a driving video signal to each source bus line SL. At this time, the source driver 300 sequentially holds the digital video signals DV indicating voltages to be applied to the respective source bus lines SL, at timing of occurrence of pulses of the source clock signal. Then, the held digital video signals DV are converted to analog voltages at timing of occurrence of a pulse of the latch strobe signal. The converted analog voltages are simultaneously applied, as driving video signals, to all source bus lines SL.
By applying the scanning signals to the gate bus lines GL and applying the driving video signals to the source bus lines SL in the above-described manner, an image based on the image signal DAT transmitted from the external source is displayed in the display region 400.
Meanwhile, as the TFTs 40 in the display region 400, for example, an oxide TFT (a thin film transistor that uses an oxide semiconductor as a channel layer) can be adopted. More specifically, a TFT having a channel layer formed of In—Ga—Zn—O (indium gallium zinc oxide) which is an oxide semiconductor having indium (In), gallium (Ga), zinc (Zn), and oxygen (O) as the main components (hereinafter, referred to as “In—Ga—Zn—O-TFT”) can be adopted as the TFTs 40. By adopting such an In—Ga—Zn—O-TFT, effects such as an improvement in definition and a reduction in power consumption can be obtained. In addition, transistors using oxide semiconductors other than In—Ga—Zn—O (indium gallium zinc oxide) as a channel layer can also be adopted. For example, when a transistor using, as a channel layer, an oxide semiconductor containing at least one of indium, gallium, zinc, copper (Cu), silicon (Si), tin (Sn), aluminum (Al), calcium (Ca), germanium (Ge), and lead (Pb) is adopted, too, the same effects can be obtained. Note that the use of other TFTs than oxide TFTs is not excluded.
<1.2 Gate Driver>
Next, the gate driver 200 will be described in detail.
<1.2.1 Configuration and Operation of the Gate Driver>
In each embodiment, a plurality of gate drivers 200 are provided in a liquid crystal display device. Hence, first, a configuration and operation which are common to all gate drivers of all embodiments will be described. Note, however, that the configuration and operation described below are an example and the present invention is not limited thereto.
<1.2.1.1 Configuration of a Shift Register Circuit>
As shown in
Signals to be provided to the input terminals of each stage (each unit circuit SR) of the shift register circuit 210 are as follows (see
An output signal OUT is outputted from the output terminal of each stage (each unit circuit SR) of the shift register circuit 210. An output signal OUT outputted from any stage (here, a zth stage) is provided as a scanning signal G(z) to a zth gate bus line among the k gate bus lines connected to the shift register circuit 210, and is also provided as a set signal S to a unit circuit SRz+1 of a (z+1)th stage.
In the above-described configuration, when a pulse of the gate start pulse signal ST serving as a set signal S is provided to the unit circuit SR1 of the first stage of the shift register circuit 210, shift pulses included in output signals OUT outputted from the respective unit circuits SR are sequentially transferred from the unit circuit SR1 of the first stage to the unit circuit SRk of a kth stage, based on the clock operation of the two-phase gate clock signals. Then, according to the transfer of the shift pulses, the output signals OUT outputted from the respective unit circuits SR sequentially go to a high level. By this, scanning signals G(1) to G(k) which sequentially go to a high level (active) for a predetermined period are provided to the k gate bus lines connected to the shift register circuit 210.
<1.2.1.2 Configuration of the Unit Circuit>
Next, a connection relationship between the components in the unit circuit SR will be described. The gate terminal of the thin film transistor T1, the source terminal of the thin film transistor T10, and one end of the capacitor C1 are connected to each other. Note that a region (wiring line) where they are connected to each other is referred to as “first node” for convenience sake. The first node is given reference character n1. The gate terminal of the thin film transistor T2, the gate terminal of the thin film transistor T4, the drain terminal of the thin film transistor T5, the source terminal of the thin film transistor T7, the drain terminal of the thin film transistor T8, and one end of the resistor R1 are connected to each other. Note that a region (wiring line) where they are connected to each other is referred to as “second node” for convenience sake. The second node is given reference character n2.
The thin film transistor T1 is connected at its gate terminal to the first node n1, connected at its drain terminal to the input terminal 22, and connected at its source terminal to the output terminal 29. The thin film transistor T2 is connected at its gate terminal to the second node n2, connected at its drain terminal to the output terminal 29, and connected at its source terminal to the input terminal for a low-level power supply voltage VSS. The thin film transistor T3 is connected at its gate terminal to the input terminal 21, connected at its drain terminal to the input terminal for a high-level power supply voltage VDD, and connected at its source terminal to the drain terminal of the thin film transistor 14 and the drain terminal of the thin film transistor T10. The thin film transistor T4 is connected at its gate terminal to the second node n2, connected at its drain terminal to the source terminal of the thin film transistor T3 and the drain terminal of the thin film transistor T10, and connected at its source terminal to the input terminal for a low-level power supply voltage VSS. The thin film transistor T5 is connected at its gate terminal to the input terminal 21, connected at its drain terminal to the second node n2, and connected at its source terminal to the input terminal for a low-level power supply voltage VSS.
The thin film transistor T6 is connected at its gate terminal to the input terminal 23, connected at its drain terminal to the input terminal for a high-level power supply voltage VDD, and connected at its source terminal to the other end of the resistor R1. The thin film transistor T7 is connected at its gate and drain terminals to the input terminal 24 and connected at its source terminal to the second node n2. The thin film transistor T8 is connected at its gate terminal to the output terminal 29, connected at its drain terminal to the second node n2, and connected at its source terminal to the input terminal for a low-level power supply voltage VSS. The thin film transistor T9 is connected at its gate terminal to the input terminal 24, connected at its drain terminal to the output terminal 29, and connected at its source terminal to the input terminal for a low-level power supply voltage VSS. The thin film transistor T10 is connected at its gate terminal to the input terminal for a high-level power supply voltage VDD, connected at its drain terminal to the source terminal of the thin film transistor T3 and the drain terminal of the thin film transistor 14, and connected at its source terminal to the first node n1.
The capacitor C1 is connected at its one end to the gate terminal of the thin film transistor T1 and connected at its other end to the source terminal of the thin film transistor T1. The resistor R1 is connected at its one end to the second node n2 and connected at its other end to the source terminal of the thin film transistor T6.
<1.2.1.3 Operation of the Shift Register Circuit>
Next, with reference to
In
During a period before period t01, in all unit circuits SR, the potential of the first node n1 is at a low level, the potential of the second node n2 is at a high level, and the output signal OUT is at a low level.
First, attention is focused on the unit circuit SR1 of the first stage. During period t01, a pulse of the gate start pulse signal ST is outputted. Since the gate start pulse signal ST is provided as a set signal S to the unit circuit SR1 of the first stage, the thin film transistor T3 and the thin film transistor T5 go into an on state during period t01. By the thin film transistor T5 going into an on state, the potential of the second node n2 goes to a low level. By this, the thin film transistor T2 and the thin film transistor T4 go into an off state. In addition, at this time, the thin film transistor T10 is in an on state, and due to the thin film transistor T3 going into an on state, the first node n1 is precharged. By the precharging, the potential of the first node n1 becomes almost “VDD−Vth”. Note that Vth is a threshold voltage of the thin film transistor T3. In addition, since, as described above, the thin film transistor T4 is in the off state, the potential of the first node n1 does not decrease.
During period t11, the set signal S (gate start pulse signal ST) is at a low level. Hence, the thin film transistor T3 is in an off state. In addition, during period t11, the second gate clock signal CK2 is at a low level. Since the second gate clock signal CK2 is provided as a second clock CKB to the unit circuit SR1 of the first stage, the thin film transistor T6 is in an off state. Therefore, the second node n2 is maintained at the low level and the thin film transistor T4 is in an off state. By this, during period t11, the first node n1 is in a floating state.
In addition, during period t11, the first gate clock signal CK1 changes from a low level to a high level. Since the first gate clock signal CK1 is provided as a first clock CKA to the unit circuit SR1 of the first stage, the potential at the input terminal 22 increases during period t11. Since the first node n1 is in the floating state as described above, the first node n1 is bootstrapped (the first node n1 goes into a boosted state) by the increase in the potential at the input terminal 22. Specifically, the potential of the first node n1 becomes almost “VDD×2−Vth”. By this, a large voltage is applied to the gate terminal of the thin film transistor T1, and the potential of the output signal OUT (the potential at the output terminal 29) increases to a high-level potential of the first gate clock signal CK1 without causing a so-called threshold voltage drop (the threshold voltage drop is a phenomenon in which the source potential increases only to a potential lower by the threshold voltage than the drain potential). In this manner, the gate bus line connected to the output terminal 29 of the unit circuit SR1 of the first stage is placed in a selected state.
Furthermore, during period t11, by the output signal OUT going to a high level in the above-described manner, the thin film transistor T8 goes into an on state. By this, the potential of the second node n2 is securely drawn to the VSS potential. Therefore, during period t11, the thin film transistor T2 and the thin film transistor T4 are securely maintained in the off state. Hence, the potential of the output signal OUT and the potential of the first node n1 do not decrease during period t11.
Meanwhile, if the thin film transistor T10 is not provided in the unit circuit SR, then the source potential of the thin film transistor T3 and the drain potential of the thin film transistor T4 become an extremely high potential (almost “VDD×2−Vth”) by the bootstrapping based on the increase in the potential at the input terminal 22 during period t11. Due to this, there is a possibility that a voltage exceeding a breakdown voltage may be applied to the thin film transistor T3 and the thin film transistor T4. That is, there is a possibility that the thin film transistor T3 and the thin film transistor T4 may be destroyed.
Regarding this, according to the configuration shown in
During period t12, the first gate clock signal CK1 changes from the high level to a low level. By this, with a decrease in the potential at the input terminal 22, the potential of the output signal OUT goes to a low level. In addition, the potential of the first node n1 decreases.
During period 21, the second gate clock signal CK2 changes from the low level to a high level. By this, the thin film transistor T6 goes into an on state. As a result, the potential of the second node n2 increases to a high level from the low level through the resistor R1, and thus, the thin film transistor T2 and the thin film transistor 14 go into an on state. By this, the potential of the output signal OUT and the potential of the first node n1 are drawn to the VSS potential.
During and after period t22, in the unit circuit SR1 of the first stage, every time the second gate clock signal CK2 changes from a low level to a high level, the thin film transistor T6 goes into an on state. Therefore, during and after period t22, the potential of the second node n2 is maintained at a high level, and the potential of the output signal OUT and the potential of the first node n1 are drawn to the VSS potential whenever necessary.
Next, attention is focused on the unit circuit SR2 of the second stage. The output signal OUT outputted from the unit circuit SR1 of the first stage is provided as a set signal S to the unit circuit SR2 of the second stage. Therefore, to the unit circuit SR2 of the second stage, a high-level set signal S is provided during period t11. By this, as with the unit circuit SR1 of the first stage for period t01, the first node n1 is precharged during period t11. Then, during period t21, as with the unit circuit SR1 of the first stage for period t11, the first node n1 is bootstrapped and the potential of the output signal OUT increases to a high-level potential of the second gate clock signal CK2. In addition, during period t22, as with the unit circuit SR1 of the first stage for period t12, the potential of the output signal OUT goes to a low level and the potential of the first node n1 decreases. Furthermore, during period t31, as with the unit circuit SR1 of the first stage for period t21, the potential of the output signal OUT and the potential of the first node n1 are drawn to the VSS potential. Furthermore, during and after period t32, as with the unit circuit SR1 of the first stage for period t22 and thereafter, the potential of the output signal OUT and the potential of the first node n1 are drawn to the VSS potential whenever necessary.
The same operation is also performed for the third to kth unit circuits SR3 to SRk. Note that the initialization signal INIT is brought to a high level, for example, during a vertical flyback period. When the initialization signal INIT goes to a high level, the thin film transistor T7 and the thin film transistor T9 go into an on state. By the thin film transistor T7 going into an on state, the potential of the second node n2 goes to a high level and the thin film transistor T2 and the thin film transistor T4 go into an on state. From the above, the potential of the output signal OUT and the potential of the first node n1 are drawn to the VSS potential. Since the initialization signal INIT is provided to all unit circuits SR1 to SRk in a shared manner, by bringing the initialization signal INIT to a high level, the potential of the output signal OUT and the potential of the first node n1 can be brought to the VSS potential in all unit circuits SR1 to SRk.
In the above-described manner, output signals OUT1 to OUTk which sequentially go to a high level for a predetermined period are outputted from the k unit circuits SR1 to SRk included in the shift register circuit 210. By this, as shown in
<1.2.2 Arrangement of the Gate Drivers>
The gate drivers 200 of the present embodiment will be described below.
In each of the left projecting portion 410L and the right projecting portion 410R, there are disposed 2n gate bus lines (n is a natural number) (gate bus lines with a length corresponding to the length of a part of a distance from one edge to the other edge of the display region 400). In
In the present embodiment, as shown in
Note that, in the present embodiment, a first-type scanning signal line drive circuit is implemented by a main gate driver and a second-type scanning signal line drive circuit is implemented by a sub gate driver. Note also that one pair of scanning signal line driving units is implemented by the main gate driver 200(m1) and the sub gate driver 200(s1), and the other pair of scanning signal line driving units is implemented by the main gate driver 200(m2) and the sub gate driver 200(s2). That is, in the present embodiment, two pairs of scanning signal line driving units are provided.
The main gate driver 200(m1) drives the gate bus lines GL(1L), GL(3L), . . . , GL(2n−1L), GL(2n+1), GL(2n+3), . . . , GL(2m−1). The main gate driver 200(m2) drives the gate bus lines GL(2R), GL(4R), . . . , GL(2nR), GL(2n+2), GL(2n+4), . . . , GL(2m). The sub gate driver 200(s1) drives the gate bus lines GL(1R), GL(3R), . . . , GL(2n−1R). The sub gate driver 200(s2) drives the gate bus lines GL(2L), GL(4L), . . . , GL(2nL).
As described above, each of odd-numbered gate bus lines GL in the projecting portions and the rectangular portion is driven by a gate driver 200 arranged on the left side of the relevant gate bus line GL, and each of even-numbered gate bus lines GL in the projecting portions and the rectangular portion is driven by gate drivers 200 arranged on the right side of the relevant gate bus line GL. Specifically, in the left projecting portion 410L, the gate bus lines GL(1L) to GL(2nL) are alternately driven one by one by the main gate driver 200(m1) and the sub gate driver 200(s2). In addition, in the right projecting portion 410R, the gate bus lines GL(1R) to GL(2nR) are alternately driven one by one by the sub gate driver 200(s1) and the main gate driver 200(m2). Furthermore, in the rectangular portion, the gate bus lines GL(2n+1) to GL(2m) are alternately driven one by one by the main gate driver 200(m1) and the main gate driver 200(m2). Such alternate one-by-one driving of the gate bus lines GL by the gate drivers 200 arranged on the left side and the gate drivers 200 arranged on the right side is hereinafter referred to as “staggered driving”.
Now, attention is focused on, for example, the main gate driver 200(m1). Regarding the gate bus lines driven by the main gate driver 200(m1), as is clear from
Meanwhile, in the above description, the shift register circuit 210 in each gate driver 200 includes k unit circuits SR1 to SRk (k is a natural number). Regarding this, in the present embodiment, “k=m” for the main gate drivers 200(m1) and 200(m2) and “k=n” for the sub gate drivers 200 (s1) and 200(s2).
<1.2.3 Relationship Between a Gate Driver Region and a Conventional Bypass Wiring Line Region>
Now, with reference to
<1.2.4 Driving Method>
With reference to
Under the above-described presumption, as shown in
By providing the gate start pulse signals and the gate clock signals to the shift register circuits 210 in the gate drivers 200 in the above-described manner, scanning signals are outputted from each gate driver 200 as shown in
From
As described above, when attention is focused on a main gate driver and a sub gate driver in a pair, the sub gate driver drives gate bus lines that correspond to some of the gate bus lines driven by the main gate driver and that are not connected to the gate bus lines driven by the main gate driver. In addition, the main gate driver and the sub gate driver drive the corresponding gate bus lines at the same timing, based on the same gate control signals (timing control signals) GCTL.
<1.3 Regarding Wiring Lines for the Gate Control Signals>
Now, wiring lines for the gate control signals GCTL to be provided to the gate drivers 200 from the display control circuit 100 will be described. For the wiring lines for the gate control signals GCTL, for example, a configuration shown in
In the first configuration, the gate start pulse signal GSP1 and the gate clock signals GCK1 and GCK3 are supplied using the same signal wiring line 61 to the main gate driver 200(m1) and the sub gate driver 200(s1), and the gate start pulse signal GSP2 and the gate clock signals GCK2 and GCK4 are supplied using the same signal wiring line 62 to the main gate driver 200(m2) and the sub gate driver 200(s2). As such, the gate control signals (timing control signals) GCTL are supplied using the same signal wiring line to a main gate driver and a sub gate driver in a pair.
According to the first configuration, a signal wiring line for the gate control signals GCTL is shared by the main gate driver 200(m1) and the sub gate driver 200(s1), and a signal wiring line for the gate control signals GCTL is shared by the main gate driver 200(m2) and the sub gate driver 200(s2). Hence, in a region around the display region 400, the circuit area for the gate drivers can be reduced. By this, a narrow picture-frame in the region around the display region 400 can be achieved.
In the second configuration, the gate start pulse signal GSP1 and the gate clock signals GCK1 and GCK3 are supplied to the main gate driver 200(m1) using a signal wiring line 63, and the gate start pulse signal GSP1 and the gate clock signals GCK1 and GCK3 are supplied to the sub gate driver 200(s1) using a signal wiring line 64. That is, the same three signals are supplied to the main gate driver 200(m1) and the sub gate driver 200(s1) using different signal wiring lines. In addition, in the second configuration, the gate start pulse signal GSP2 and the gate clock signals GCK2 and GCK4 are supplied to the main gate driver 200(m2) using a signal wiring line 66, and the gate start pulse signal GSP2 and the gate clock signals GCK2 and GCK4 are supplied to the sub gate driver 200(s2) using a signal wiring line 65. That is, the same three signals are supplied to the main gate driver 200(m2) and the sub gate driver 200(s1) using different signal wiring lines. As such, the gate control signals (timing control signals) GCTL are supplied to a main gate driver and a sub gate driver in a pair, using different signal wiring lines that do not pass through a non-display region (recessed portion 500) between the left projecting portion 410L and the right projecting portion 410R.
According to the second configuration, wiring lines for the gate control signals GCTL are not provided in the recessed portion 500. Hence, a narrow picture-frame is effectively achieved in the conventional bypass wiring line region.
<1.4 Effect>
According to the present embodiment, in a liquid crystal display device having the right-angled U-shaped display region 400 and adopting staggered driving as a driving method, the sub gate driver 200(s2) for driving some of gate bus lines GL disposed in the left projecting portion 410L is provided, in a region in the recessed portion 500, in a vicinity of the left projecting portion 410L, and the sub gate driver 200(s1) for driving some of gate bus lines GL disposed in the right projecting portion 410R is provided, in a region in the recessed portion 500, in a vicinity of the right projecting portion 410R. By thus providing the sub gate drivers in a region where bypass wiring lines for connecting the gate bus lines GL disposed in the left projecting portion 410L to the gate bus lines GL disposed in the right projecting portion 410R are conventionally disposed, even if there are a large number of gate bus lines GL disposed in the left projecting portion 410L and the right projecting portion 410R, the area of a picture-frame region required for the recessed portion 500 can be reduced over conventional displays. As such, according to the present embodiment, a variant-form display (a display device having a right-angled U-shaped display region) achieves a narrower picture-frame than conventional displays.
<1.5 Variants>
Variants of the above-described first embodiment will be described below.
<1.5.1 First Variant>
As in the first embodiment, a main gate driver 200 (m1) is arranged on the left side of the display region 400, a main gate driver 200(m2) is arranged on the right side of the display region 400, a sub gate driver 200(s1) is arranged on the left side of a right projecting portion 410R, and a sub gate driver 200(s2) is arranged on the right side of a left projecting portion 410L. How to provide gate control signals GCTL to each gate driver 200 is also the same as in the first embodiment.
In the present variant, some gate bus lines disposed in the left projecting portion 410L and some gate bus lines disposed in the right projecting portion 410R are connected to each other by bypass wiring lines GLr. In the present variant, in a region where the area of a picture-frame is reduced by the provision of the bypass wiring lines GLr, the bypass wiring lines GLr are thus provided. Gate bus lines GL(1L) to GL(2iL) that are not connected to the bypass wiring lines GLr among gate bus lines disposed in the left projecting portion 410L are alternately driven one by one by the main gate driver 200(m1) and the sub gate driver 200(s2). In addition, gate bus lines GL(1R) to GL(2iR) that are not connected to the bypass wiring lines GLr among gate bus lines disposed in the right projecting portion 410R are alternately driven one by one by the sub gate driver 200(s1) and the main gate driver 200(m2). Furthermore, gate bus lines GL(2i+1L) to GL(2i+jL) that are connected to the bypass wiring lines GLr among gate bus lines disposed in the left projecting portion 410L and the right projecting portion 410R are alternately driven one by one by the main gate driver 200 (m1) and the main gate driver 200(m2). As such, the gate bus lines connected to the bypass wiring lines GLr are driven by the main gate drivers
Now, with reference to
<1.5.2 Second Variant>
In the present variant, too, a main gate driver 200(m1) is arranged on the left side of the display region 400, a main gate driver 200(m2) is arranged on the right side of the display region 400, a sub gate driver 200(s1) is arranged on the left side of the right projecting portion 410R, and a sub gate driver 200(s2) is arranged on the right side of the left projecting portion 410L.
A gate start pulse signal GSP1, a gate clock signal GCK1, and a gate clock signal GCK3 are provided to the main gate driver 200(m1). A gate start pulse signal GSP2, a gate clock signal GCK2, and a gate clock signal GCK4 are provided to the main gate driver 200(m2). The gate clock signal GCK1 and the gate clock signal GCK3 are provided to the sub gate driver 200(s1). The gate clock signal GCK2 and the gate clock signal GCK4 are provided to the sub gate driver 200(s2).
Here, 2j gate bus lines GL(1) to GL(2j) (j is a natural number) are disposed in the rectangular portion. A scanning signal provided to the gate bus line GL(2j−1) is provided as a gate start pulse signal ST (see
By the above-described configuration, in the rectangular portion, the 2j gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the main gate driver 200(m2). In addition, in the left projecting portion 410L, a plurality of gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the sub gate driver 200(s2). Furthermore, in the right projecting portion 410R, a plurality of gate bus lines are alternately driven one by one by the sub gate driver 200(s1) and the main gate driver 200(m2).
<1.5.3 Third Variant>
In the present variant, as shown in
A gate start pulse signal GSP1, a gate clock signal GCK1, and a gate clock signal GCK3 are provided to the main gate driver 200(m1), the sub gate driver 200(s1), and the sub gate driver 200(s3), and a gate start pulse signal GSP2, a gate clock signal GCK2, and a gate clock signal GCK4 are provided to the main gate driver 200(m2), the sub gate driver 200(s2), and the sub gate driver 200(s4).
The number of gate bus lines GL disposed in the left projecting portion 410L, the number of gate bus lines GL disposed in the middle projecting portion 410M, and the number of gate bus lines GL disposed in the right projecting portion 410R are equal.
By the above-described configuration, in the left projecting portion 410L, a plurality of gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the sub gate driver 200(s2). In addition, in the middle projecting portion 410M, a plurality of gate bus lines are alternately driven one by one by the sub gate driver 200(s3) and the sub gate driver 200(s4). In the right projecting portion 410R, a plurality of gate bus lines are alternately driven one by one by the sub gate driver 200(s1) and the main gate driver 200(m2). In the rectangular portion, a plurality of gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the main gate driver 200(m2).
<1.5.4 Fourth Variant>
In the present variant, a main gate driver 200(m1) is arranged on the left side of the display region 400, a main gate driver 200(m2) is arranged on the right side of the display region 400, a sub gate driver 200(s1) is arranged on the left side of the right rectangular portion (i.e., a right-side region of the hole portion 510), and a sub gate driver 200(s2) is arranged on the right side of the left rectangular portion (i.e., a left-side region of the hole portion 510).
A gate start pulse signal GSP1, a gate clock signal GCK1, and a gate clock signal GCK3 are provided to the main gate driver 200(m1). A gate start pulse signal GSP2, a gate clock signal GCK2, and a gate clock signal GCK4 are provided to the main gate driver 200(m2). The gate clock signal GCK1 and the gate clock signal GCK3 are provided to the sub gate driver 200(s1). The gate clock signal GCK2 and the gate clock signal GCK4 are provided to the sub gate driver 200(s2).
Here, 2q gate bus lines GL(1) to GL(2q) (q is a natural number) are disposed in the upper rectangular portion. A scanning signal provided to the gate bus line GL(2q−1) is provided as a gate start pulse signal ST (see
By the above-described configuration, in the upper rectangular portion, the 2q gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the main gate driver 200(m2). In addition, in the left rectangular portion, a plurality of gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the sub gate driver 200(s2). Furthermore, in the right rectangular portion, a plurality of gate bus lines are alternately driven one by one by the sub gate driver 200(s1) and the main gate driver 200(m2). Moreover, in the lower rectangular portion, a plurality of gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the main gate driver 200(m2).
<1.5.5 Fifth Variant>
In the present variant, as shown in
A gate start pulse signal GSP1, a gate clock signal GCK1, and a gate clock signal GCK3 are provided to the sub gate driver 200 (s1) and the sub gate driver 200(s3). The gate clock signal GCK1 and the gate clock signal GCK3 are provided to the main gate driver 200(m1), in addition to a signal that synchronizes with a scanning signal to be provided to a gate bus line GL, as a gate start pulse signal ST (see
Now, attention is focused on the left projecting portion 410L. In an upper-side region of the left projecting portion 410L, gate bus lines connected to the sub gate driver 200(s3) and gate bus lines connected to the sub gate driver 200(s2) are disposed. In addition, in a lower-side region of the left projecting portion 410L, gate bus lines connected to the main gate driver 200(m1) and gate bus lines connected to the sub gate driver 200(s2) are disposed. Next, attention is focused on the right projecting portion 410R. In an upper-side region of the right projecting portion 410R, gate bus lines connected to the sub gate driver 200(s1) and gate bus lines connected to the sub gate driver 200(s4) are disposed. In addition, in a lower-side region of the right projecting portion 410R, gate bus lines connected to the sub gate driver 200(s1) and gate bus lines connected to the main gate driver 200(m2) are disposed.
By the above-described configuration, in the upper-side region of the left projecting portion 410L, a plurality of gate bus lines are alternately driven one by one by the sub gate driver 200(s3) and the sub gate driver 200(s2). In the lower-side region of the left projecting portion 410L, a plurality of gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the sub gate driver 200(s2). In the upper-side region of the right projecting portion 410R, a plurality of gate bus lines are alternately driven one by one by the sub gate driver 200(s1) and the sub gate driver 200(s4). In the lower-side region of the right projecting portion 410R, a plurality of gate bus lines are alternately driven one by one by the sub gate driver 200(s1) and the main gate driver 200(m2). In the rectangular portion, a plurality of gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the main gate driver 200(m2).
<1.5.6 Sixth Variant>
In the present variant, a main gate driver 200(m1) is arranged on the left side of the display region 400, a main gate driver 200(m2) is arranged on the right side of the display region 400, a sub gate driver 200(s1) is arranged on the left side of a right projecting portion 410R, and a sub gate driver 200(s2) is arranged on the right side of a left projecting portion 410L.
A gate start pulse signal GSP1, a gate clock signal GCK1, and a gate clock signal GCK3 are provided to the main gate driver 200(m1) and the sub gate driver 200(s1), and a gate start pulse signal GSP2, a gate clock signal GCK2, and a gate clock signal GCK4 are provided to the main gate driver 200(m2) and the sub gate driver 200(s2).
By the above-described configuration, in the left projecting portion 410L, a plurality of gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the sub gate driver 200(s2). In addition, in the right projecting portion 410R, a plurality of gate bus lines are alternately driven one by one by the sub gate driver 200(s1) and the main gate driver 200(m2). Furthermore, in the semicircular portion, a plurality of gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the main gate driver 200(m2).
<1.5.7 Seventh Variant>
In the present variant, as shown in
A gate start pulse signal GSP1, a gate clock signal GCK1, and a gate clock signal GCK3 are provided to the sub gate driver 200 (s1) and the sub gate driver 200(s3). The gate clock signal GCK1 and the gate clock signal GCK3 are provided to the main gate driver 200(m1), in addition to a signal that synchronizes with a scanning signal to be provided to a gate bus line GL, as a gate start pulse signal ST (see
As in the fifth variant, in an upper-side region of the left projecting portion 410L, gate bus lines connected to the sub gate driver 200(s3) and gate bus lines connected to the sub gate driver 200(s2) are disposed, and in a lower-side region of the left projecting portion 410L, gate bus lines connected to the main gate driver 200(m1) and gate bus lines connected to the sub gate driver 200(s2) are disposed. In addition, in an upper-side region of the right projecting portion 410R, gate bus lines connected to the sub gate driver 200(s1) and gate bus lines connected to the sub gate driver 200(s4) are disposed, and in a lower-side region of the right projecting portion 410R, gate bus lines connected to the sub gate driver 200(s1) and gate bus lines connected to the main gate driver 200(m2) are disposed.
By the above-described configuration, in the upper-side region of the left projecting portion 410L, a plurality of gate bus lines are alternately driven one by one by the sub gate driver 200(s3) and the sub gate driver 200(s2). In the lower-side region of the left projecting portion 410L, a plurality of gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the sub gate driver 200(s2). In the upper-side region of the right projecting portion 410R, a plurality of gate bus lines are alternately driven one by one by the sub gate driver 200(s1) and the sub gate driver 200(s4). In the lower-side region of the right projecting portion 410R, a plurality of gate bus lines are alternately driven one by one by the sub gate driver 200(s1) and the main gate driver 200(m2). In the rectangular portion, a plurality of gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the main gate driver 200(m2).
<1.5.8 Eighth Variant>
In the present variant, a main gate driver 200(m1) is arranged on the left side of the display region 400, a main gate driver 200(m2) is arranged on the right side of the display region 400, a sub gate driver 200(s1) is arranged in a portion of the cut portion 520 near a right projecting portion 410R, and a sub gate driver 200(s1) is arranged in a portion of the cut portion 520 near a left projecting portion 410L.
A gate start pulse signal GSP1, a gate clock signal GCK1, and a gate clock signal GCK3 are provided to the main gate driver 200(m1) and the sub gate driver 200(s1), and a gate start pulse signal GSP2, a gate clock signal GCK2, and a gate clock signal GCK4 are provided to the main gate driver 200(m2) and the sub gate driver 200(s2).
By the above-described configuration, in the left projecting portion 410L, a plurality of gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the sub gate driver 200(s2). In addition, in the right projecting portion 410R, a plurality of gate bus lines are alternately driven one by one by the sub gate driver 200(s1) and the main gate driver 200(m2). Furthermore, in the semicircular portion, a plurality of gate bus lines are alternately driven one by one by the main gate driver 200(m1) and the main gate driver 200(m2).
A second embodiment of the present invention will be described. Note that the following mainly describes differences from the above-described first embodiment and description of the same respects as those in the first embodiment is omitted.
In the first embodiment, staggered driving is adopted as a method for driving the gate bus lines GL. In contrast, in the present embodiment, “one-side driving” is adopted in which all of a plurality of gate bus lines GL arranged in each region are driven by a single gate driver 200. A detailed description will be made below.
<2.1 Configuration>
The main gate driver 200(m) drives gate bus lines GL(1L) to GL(2nL) and GL(2n+1) to GL(2m). The sub gate driver 200(s) drives gate bus lines GL(1R) to GL(2nR). As such, each of gate bus lines disposed in a left projecting portion 410L and a rectangular portion is driven by the main gate driver 200(m) arranged on the left side of the relevant gate bus line, and each of gate bus lines disposed in the right projecting portion 410R is driven by the sub gate driver 200(s) arranged on the left side of the relevant gate bus line.
<2.2 Driving Method>
With reference to
Under the above-described presumption, as shown in
By providing the gate start pulse signal and the gate clock signals to the shift register circuits 210 in the gate drivers 200 in the above-described manner, scanning signals are outputted from each gate driver 200 as shown in
From
<2.3 Effect>
According to the present embodiment, in a liquid crystal display device having the right-angled U-shaped display region 400 and adopting one-side driving as a driving method, the sub gate driver 200(s) for driving the gate bus lines GL disposed in the right projecting portion 410R is provided, in a region in a recessed portion 500, in a vicinity of the right projecting portion 410R. By thus providing the sub gate driver in a region where bypass wiring lines for connecting the gate bus lines GL disposed in the left projecting portion 410L to the gate bus lines GL disposed in the right projecting portion 410R are conventionally disposed, even if there are a large number of gate bus lines GL disposed in the left projecting portion 410L and the right projecting portion 410R, the area of a picture-frame region required for the recessed portion 500 can be reduced over conventional displays. As such, as in the first embodiment, a variant-form display (a display device having a right-angled U-shaped display region) achieves a narrower picture-frame than conventional displays.
In addition, since one-side driving is adopted, the number of gate drivers 200 can be reduced compared with a configuration in which staggered driving is adopted or a configuration both-side driving which will be described later is adopted. Hence, a narrow picture-frame is more effectively achieved.
<2.4 Variants>
Variants of the above-described second embodiment will be described below.
<2.4.1 First Variant>
By the above-described configuration, in the left projecting portion 410L, a plurality of gate bus lines are sequentially driven one by one by the sub gate driver 200(s). In addition, in a right projecting portion 410R and a rectangular portion, a plurality of gate bus lines are sequentially driven one by one by the main gate driver 200(m).
<2.4.2 Second Variant>
By the above-described configuration, in a left projecting portion 410L and a rectangular portion, a plurality of gate bus lines are sequentially driven one by one by the main gate driver 200(m). In addition, in the right projecting portion 410R, a plurality of gate bus lines are sequentially driven one by one by the sub gate driver 200(s).
<2.4.3 Third Variant>
By the above-described configuration, in the left projecting portion 410L, a plurality of gate bus lines are sequentially driven one by one by the sub gate driver 200(s). In addition, in a right projecting portion 410R and a rectangular portion, a plurality of gate bus lines are sequentially driven one by one by the main gate driver 200(m).
A third embodiment of the present invention will be described. Note that the following mainly describes differences from the above-described first embodiment and description of the same respects as those in the first embodiment is omitted.
As a method for driving gate bus lines, staggered driving is adopted in the first embodiment and one-side driving is adopted in the second embodiment. In contrast, in the present embodiment, “both-side driving” is adopted in which each gate bus line GL is driven by both of a gate driver 200 arranged on the left side thereof and a gate driver 200 arranged on the right side thereof. Note that, by adopting such both-side driving, for example, the waveform rounding and delay of a scanning signal at a middle portion can be reduced. A detailed description will be made below.
<3.1 Configuration>
Note that, as in the first embodiment, a first-type scanning signal line drive circuit is implemented by a main gate driver and a second-type scanning signal line drive circuit is implemented by a sub gate driver. Note also that one pair of scanning signal line driving units is implemented by the main gate driver 200(m1) and the sub gate driver 200(s1), and the other pair of scanning signal line driving units is implemented by the main gate driver 200(m2) and the sub gate driver 200(s2). That is, in the present embodiment, two pairs of scanning signal line driving units are provided.
The main gate driver 200(m1) drives the gate bus lines GL(1L) to GL(2nL) and GL(2n+1) to GL(2m). The main gate driver 200(m2) drives the gate bus lines GL(1R) to GL(2nR) and GL(2n+1) to GL(2m). The sub gate driver 200(s1) drives the gate bus lines GL(1R) to GL(2nR). The sub gate driver 200(s2) drives the gate bus lines GL(1L) to GL(2nL).
From the above, each of gate bus lines disposed in the left projecting portion 410L is driven by both the main gate driver 200(m1) arranged on the left side of the relevant gate bus line and the sub gate driver 200(s2) arranged on the right side of the relevant gate bus line. In addition, each of gate bus lines disposed in the right projecting portion 410R is driven by both the sub gate driver 200(s1) arranged on the left side of the relevant gate bus line and the main gate driver 200(m2) arranged on the right side of the relevant gate bus line. Furthermore, each of gate bus lines disposed in a rectangular portion is driven by both the main gate driver 200(m1) arranged on the left side of the relevant gate bus line and the main gate driver 200(m2) arranged on the right side of the relevant gate bus line.
<3.2 Driving Method>
With reference to
Under the above-described presumption, as shown in
By providing the gate start pulse signal and the gate clock signals to the shift register circuits 210 in the gate drivers 200 in the above-described manner, scanning signals are outputted from each gate driver 200 as shown in
From
In addition, in the right projecting portion 410R, by sequentially outputting active scanning signals from both the main gate driver 200(m2) and the sub gate driver 200(s1), the gate bus lines GL(1R) to GL(2nR) are sequentially placed in a selected state. Here, a scanning signal G(zL) and a scanning signal G(zR) become active at the same timing (z is an integer between 1 and 2n, inclusive). That is, the scanning start timing of the gate bus lines GL disposed in the left projecting portion 410L is the same as the scanning start timing of the gate bus lines GL disposed in the right projecting portion 410L, and the scanning end timing of the gate bus lines GL disposed in the left projecting portion 410L is the same as the scanning end timing of the gate bus lines GL disposed in the right projecting portion 410L. After the end of scanning of the gate bus lines GL disposed in the left projecting portion 410L and the gate bus lines GL disposed in the right projecting portion 410R, in the rectangular portion, active scanning signals are sequentially outputted from both the main gate driver 200 (m1) and the main gate driver 200(m2). By this, the gate bus lines GL(2n+1) to GL(2m) are sequentially placed in a selected state.
<3.3 Effect>
According to the present embodiment, in a liquid crystal display device having the right-angled U-shaped display region 400 and adopting both-side driving as a driving method, as in the first embodiment, the sub gate drivers are provided in a region where bypass wiring lines for connecting the gate bus lines GL disposed in the left projecting portion 410L to the gate bus lines GL disposed in the right projecting portion 410R are conventionally disposed. By this, even if there are a large number of gate bus lines GL disposed in the left projecting portion 410L and the right projecting portion 410R, the area of a picture-frame region required for the recessed portion 500 can be reduced over conventional displays. As such, as in the first embodiment, a variant-form display (a display device having a right-angled U-shaped display region) achieves a narrower picture-frame than conventional displays.
In addition, since both-side driving is adopted, effects such as those shown below can be obtained. First, the waveform rounding and delay of a scanning signal at a middle portion of each gate bus line GLn can be reduced. In addition, by the reduction in delay, setup time required for timing can be reduced, and thus, the occurrence of erroneous operation of the gate drivers 200 is suppressed.
Although a liquid crystal display device is described as an example in the above-described embodiments (including the variants), the present invention is not limited thereto. The present invention can also be applied to display devices other than liquid crystal display devices, such as an organic electro luminescence (EL) display device.
In addition, the shape of the display region 400 is not limited to those described in the above-described embodiments (including the variants), and various shapes can be adopted.
This application claims priority to Japanese Patent Application No. 2016-155679, entitled “Display Device”, filed Aug. 8, 2016, the content of which is incorporated herein by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016-155679 | Aug 2016 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2017/027837 | 8/1/2017 | WO | 00 |
