Patent Application
20190213971
This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0002399, filed on Jan. 8, 2018 in the Korean Intellectual Property Office, the entire content of which is hereby incorporated by reference.
Aspects of embodiments of the present disclosure relate to a display device for displaying an image in which a frame rate is changed.
A display device receives an image data signal from an external device, such as a graphic card, and displays an image corresponding to the received image data signal.
The frame rate of an image data signal received by the display device may not be constant, but may vary. In order to display an image corresponding to the variable frame rate, the display device may further include additional hardware.
When the frame rate is changed, the voltage applied to the elements inside the display device may fluctuate irregularly, or crosstalk may occur such that the quality of the image displayed on the display device may be deteriorated.
According to an aspect of embodiments of the present disclosure, a display device is capable of providing a high-quality image even when the frame rate of an image data signal changes.
According to one or more embodiments of the inventive concept, a display device includes: a memory configured to store a plurality of data; a signal controller including a receiver to receive image data from the outside, a first register to read the plurality of data stored in the memory, and a power controller, wherein the power controller includes a frequency detector to detect a frequency of the received image data and an operation controller to output a control signal based on data corresponding to the detected frequency among the plurality of data read by the first register; and a voltage generator including a plurality of output circuits to output a plurality of voltages in correspondence to the control signal. At least one of the plurality of output circuits includes: a DC-DC converter; and a feedback circuit configured to control an output of the DC-DC converter and including a first comparator, a second comparator, and a PWM controller. At least one of an output voltage of the DC-DC converter, a current between the first comparator and the second comparator, and a frequency of a signal outputted from the PWM controller is changed in correspondence to the control signal.
In an embodiment, as the detected frequency is higher, the output voltage of the DC-DC converter may become greater.
In an embodiment, as the detected frequency is higher, the current between the first comparator and the second comparator may become greater.
In an embodiment, as the detected frequency is higher, the frequency of the signal outputted from the PWM controller may become higher.
In an embodiment, the feedback circuit may further include a current controller having one end connected to a node between the first comparator and the second comparator and another end connected to a ground voltage, and the current controller includes a variable resistor and a capacitor.
In an embodiment, a resistance value of the variable resistor may be changed in correspondence to the detected frequency.
In an embodiment, when the resistance value of the variable resistor is smaller, a magnitude of the current outputted from the current controller may become greater.
In an embodiment, the signals outputted by the PWM controller may include a plurality of pulse waves, and a part of the plurality of pulse waves may be skipped in correspondence to the detected frequency.
In an embodiment, as the detected frequency is smaller, a number of pulse waves skipped for a certain time in the plurality of pulse waves may increase.
In an embodiment, when the detected frequency changes, a pulse width of each of the plurality of pulse waves may be constant.
In an embodiment, the display device may further include a display panel, a gate driver, a data driver, and a gamma voltage generator. The plurality of output circuits may include: a first output circuit configured to boost an inputted reference voltage to provide a gamma voltage source to the gamma voltage generator; a second output circuit configured to boost the gamma voltage source to provide a gate-on voltage to the gate driver; a third output circuit configured to reduce an inputted reference voltage to provide a core voltage to the signal controller; a fourth output circuit configured to reduce an inputted reference voltage to provide a driving voltage to the data driver; and a fifth output circuit configured to reduce an inputted reference voltage to provide a gate-off voltage to the gate driver.
In an embodiment, the first output circuit and the second output circuit may be respectively a boost converter, the third output circuit and the fourth output circuit may be respectively a buck converter, and the fifth output circuit may be a negative charge pump.
In an embodiment, a voltage of the gamma voltage source may be 16 V or more and 18 V or less, the gate-on voltage may be 28 V or more and 38 V or less, the core voltage may be 1 V or more and 2 V or less, the driving voltage may be 1 V or more and 2 V or less, and the gate-off voltage may be −7 V or more and −5 V or less.
According to one or more embodiments of the inventive concept, a display device includes: a memory configured to store a plurality of data; a signal controller configured to detect a frame rate of an externally applied image data signal, select data corresponding to the detected frame rate among the plurality of data, and output a control signal corresponding to the selected data; and a voltage generator including a DC-DC converter to determine an output voltage in correspondence to the control signal, and a feedback circuit to determine a current flowing inside and a frequency of an outputted signal in correspondence to the control signal.
The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate some exemplary embodiments of the inventive concept and, together with the description, serve to explain principles of the inventive concept. In the drawings:
Herein, some embodiments of the inventive concept will be described with reference to the drawings.
In the drawings, thicknesses, proportions, and dimensions of components may be exaggerated for purposes of description.
In various embodiments of the inventive concept, the terms “include,” “comprise,” “including,” or “comprising,” may specify a property, a region, a fixed number, a step, a process, an element, and/or a component, but do not exclude other properties, regions, fixed numbers, steps, processes, elements, and/or components.
Referring to
The display panel 100 includes a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm intersecting the gate lines GL1 to GLn, and a plurality of pixels PX. The plurality of gate lines GL1 to GLn are connected to the gate driver 300. The plurality of data lines DL1 to DLm are connected to the data driver 400. Only some of the plurality of gate lines GL1 to GLn and only some of the plurality of data lines DL1 to DLm are illustrated in
The pixels PX are respectively connected to corresponding gate lines among the plurality of gate lines GL1 to GLn and corresponding data lines among the plurality of data lines DL1 to DLm.
The plurality of pixels PX may be divided into a plurality of groups according to a color displayed. The plurality of pixels PX may display one of primary colors. The primary colors may include red, green, blue, and white. However, the inventive concept is not limited thereto, and the primary color may further include any of various colors, such as yellow, cyan, and magenta.
In an embodiment, the signal controller 200 receives an image data signal RGB, a horizontal synchronization signal H_SYNC, a vertical synchronization signal V_SYNC, a clock signal MCLK, and a data enable signal DE from an external device. The signal controller 200 converts the data format of the image data signal RGB according to the interface specification with the data driver 400 and outputs a converted image data signal R′G′B′ to the data driver 400. In an embodiment, the signal controller 200 outputs a data control signal (e.g., an output start signal TP, a horizontal start signal STH, and a clock signal HCLK) to the data driver 400, and outputs a gate control signal (e.g., a vertical start signal STV, a gate clock signal CPV, and an output enable signal OE) to the gate driver 300.
Also, the signal controller 200 may receive the core voltages TVDD1 and TVDD2 from the voltage generator 700. The signal controller 200 may receive any one of the core voltages TVDD1 and TVDD2 generated by the voltage generator 700 and may use it as a power for driving it.
The gate driver 300 may receive a gate-on voltage VON and a gate-off voltage VOFF from the voltage generator 700 and may sequentially output the gate signals G1 to Gn in response to the gate control signals STV, CPV, and OE provided from the signal controller 200. The gate signals G1 to Gn are sequentially supplied to the gate lines GL1 to GLn of the display panel 100 to sequentially scan the gate lines GL1 to GLn. Although not shown in the drawings, the display device DD may further include a regulator for converting an input voltage into a gate-on voltage and a gate-off voltage and outputting them.
The data driver 400 generates a plurality of data voltages (or gradation voltages) using the gamma voltages provided from the gamma voltage generator 500. Upon receiving the data control signals TP, STH, and HCLK from the signal controller 200, the data driver 400 selects the data voltages corresponding to the converted image data signal R′G′B′ among the generated data voltages and provides the selected data voltages as the data signals D1 to Dm to the data lines DL1 to DLm of the display panel 100.
When the gate signals G1 to Gn are sequentially supplied to the gate lines GL1 to GLn, the data signals D1 to Dm are provided to the data lines DL1 to DLm in synchronization therewith.
Referring to
The gamma voltage Gamma 1 outputted from the output terminal between the first gamma voltage dividing resistance R1 and the second gamma voltage dividing resistance R2 has the highest voltage value, and the gamma voltage Gamma j outputted from the output terminal between the (j−1)-th gamma voltage dividing resistance Rj−1 and the j-th gamma voltage dividing resistance Rj may have the lowest voltage value.
In an embodiment of the inventive concept, the gamma voltage generator 500 may be integrated with the data driver 400, or the gamma voltage generator 500 may be included in the data driver 400.
Referring to
In an embodiment of the inventive concept, the common voltage generator 600 may be integrated with the voltage generator 700, or the common voltage generator 600 may be included in the voltage generator 700.
The memory 800 may store information on voltage values of signals exchanged between the respective components 100, 200, 300, 400, 500, 600, and 700 in the display device DD. The memory 800 may be a separate component or may be included in at least one of the components 100, 200, 300, 400, 500, 600, and 700.
In correspondence to a change in frequency (or frame rate) of the image data signal RGB, the memory 800 may store data on the levels of the core voltages TVDD1 and TVDD2 that the voltage generator 700 provides to the signal controller 200 or the data driver 400, the levels of the gate-on voltage VON and the gate-off voltage VOFF provided to the gate driver 300, and the level of the gamma voltage source AVDD provided to the gamma voltage generator 500.
In an embodiment, for example, the voltage of the gamma voltage source AVDD is 16 V or more and 18 V or less, the gate-on voltage VON is 28 V or more and 38 V or less, the core voltages TVDD1 and TVDD2 are 1 V or more and 2 V or less, and the gate-off voltage is −7 V or more and −5 V or less. However, the inventive concept is not limited thereto.
In an embodiment, as shown in
Herein, in this specification, a transistor refers to a thin film transistor. In an embodiment of the inventive concept, the storage capacitor Cst may be omitted.
In
The pixel transistor TRP outputs a pixel voltage corresponding to the data signal received from the first data line DL1 in response to the gate signal received from the first gate line GL1.
The liquid crystal capacitor Clc charges a pixel voltage outputted from the pixel transistor TRP. An arrangement of liquid crystal directors included in a liquid crystal layer LCL (see
The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc. The storage capacitor Cst maintains an arrangement of liquid crystal directors during a predetermined section.
In an embodiment, as shown in
The liquid crystal capacitor Clc includes a pixel electrode PE and a common electrode CE. The storage capacitor Cst includes the pixel electrode PE and a portion of a storage line STL overlapping the pixel electrode PE. The common voltage Vcom (see
The first gate line GL1 and the storage line STL are disposed on one surface of a first substrate DS1. The control electrode CTE is branched from the first gate line GL1. The first gate line GL1 and the storage line STL may include a metal (such as Al, Ag, Cu, Mo, Cr, Ta, Ti, and so on) or an alloy thereof. In an embodiment, the first gate line GL1 and the storage line STL may have a multi-layer structure and, for example, may include a Ti layer and a Cu layer.
A first insulating layer 10 covering the control electrode CTE and the storage line STL is disposed on one surface of the first substrate DS1. The first insulating layer 10 may include at least one of an inorganic material and an organic material. The first insulating layer 10 may be an organic film or an inorganic film. In an embodiment, the first insulating layer 10 may have a multi-layer structure and, for example, may include a silicon nitride layer and a silicon oxide layer.
The activation layer AL overlapping the control electrode CTE is disposed on the first insulating layer 10. In an embodiment, the activation layer AL may include a semiconductor layer (not shown) and an ohmic contact layer (not shown).
In an embodiment, the activation layer AL may include amorphous silicon or poly silicon. Additionally, the activation layer AL may include a metal oxide semiconductor.
The output electrode OTE and the input electrode IE are disposed on the activation layer AL. The output electrode OTE and the input electrode IE are disposed spaced apart from each other. Each of the output electrode OTE and the input electrode IE may partially overlap the control electrode CTE.
Although the pixel transistor TRP having a staggered structure is shown in
A second insulating layer 20 covering the activation layer AL, the output electrode OTE, and the input electrode IE is disposed on the first insulating layer 10. The second insulating layer 20 provides a flat surface. The second insulating layer 20 may include an organic material.
A pixel electrode PE is disposed on the second insulating layer 20. The pixel electrode PE is connected to the output electrode OTE through a contact hole CH that penetrates the second insulating layer 20. An alignment film 30 covering the pixel electrode PE may be disposed on the second insulating layer 20.
A color filter layer CF is disposed on a surface of a second substrate DS2. A common electrode CE is disposed on a surface of the color filter layer CF. A common voltage is applied to the common electrode CE. A common voltage and a pixel voltage have different values. An alignment layer (not shown) covering the common electrode CE may be disposed on the common electrode CE. In an embodiment, another insulating layer may be disposed between the color filter layer CF and the common electrode CE.
The pixel electrode PE and the common electrode CE with a liquid crystal layer LCL therebetween form the liquid crystal capacitor Clc. Additionally, portions of the pixel electrode PE and the storage line STL, which are disposed with the first insulating layer 10 and the second insulating layer 20 therebetween, form the storage capacitor Cst. The storage line STL receives a storage voltage having a different value than a pixel voltage. A storage voltage may have the same value as a common voltage.
However, the cross-section of the pixel PX shown in
In an embodiment, the signal controller 200 may include a receiver 210, an image signal converter 220, a power controller 230, a first interface 240, and a first register 250.
In an embodiment, the voltage generator 700 may include a second interface 710, a second register 720, a compensator 730, and output circuits 740. In an embodiment, the output circuits 740 include a first output circuit 741 for outputting the gamma voltage source AVDD, a second output circuit 742 for outputting the gate-on voltage VON, a third output circuit 742 for outputting the first core voltage TVDD1, a fourth output circuit 744 for outputting the second core voltage TVDD2, and a fifth output circuit 745 for outputting the gate-off voltage VOFF. Some of the output circuits 740 may be a boost converter and some of the output circuits 740 may be a buck converter. In an embodiment, for example, the first output circuit 741 and the second output circuit 742 may be boost converters, and the third output circuit 743 and the fourth output circuit 744 may be buck converters. The fifth output circuit 745 may be a buck converter or a negative charge pump.
The gate-on voltage VON outputted from the second output circuit 742 may be generated by boosting the gamma voltage source AVDD outputted from the first output circuit 741.
In an embodiment of the inventive concept, the second core voltage TVDD2 outputted by the fourth output circuit 744 may be used as a driving voltage for driving the data driver 400.
In an embodiment of the inventive concept, the first interface 240 and the second interface 710 may be an I2C interface or a TTL interface, but are not limited thereto.
Referring to
The DC-DC converter 7410 may boost or reduce the input voltage VIN to generate the output voltage VOUT. For example, the DC-DC converter 7410 of the first output circuit 741 and the second output circuit 742 boosts the input voltage VIN to generate the output voltage VOUT, and the DC-DC converter 7410 of the third output circuit 743 and the fourth output circuit 744 reduces the input voltage VIN to generate the output voltage VOUT.
The feedback circuit 7420 may monitor the output voltage VOUT of the DC-DC converter 7410 and maintain it constant.
In an embodiment, the feedback circuit 7420 may include a first resistor 7421, a second resistor 7422, a first comparator 7423, a second comparator 7424, a current controller 7425, and a PWM controller 7426.
The output voltage VOUT is distributed according to a ratio of a resistance value of the first resistor 7421 and a resistance value of the second resistor 7422, and the first comparator 7423 compares the distributed output voltage VOUT with a first reference voltage Vref1 to provide an output signal to the current controller 7425.
The current controller 7425 may adjust the current of the output signal of the first comparator 7423 and provide it to the second comparator 7424. Referring to
The second comparator 7424 may receive an output signal of the current controller 7425 and a second reference voltage Vref2 and provide an output signal to the PWM controller 7426. In an embodiment of the inventive concept, the output signal of the current controller 7425 may have a DC voltage, and the second reference voltage Vref2 and the output signal of the second comparator 7424 may be pulse wave.
The PWM controller 7426 may control the pulse of the output signal of the second comparator 7424. For example, the PWM controller 7426 may change the pulse width or the frequency of the signal from the second comparator 7424 and output a pulse signal PWM.
The DC-DC converter 7410 may receive the pulse signal PWM of the PWM controller 7426 and change or maintain the level of the output voltage VOUT.
Herein, a relationship between the signal controller 200, the memory 800, and the voltage generator 700 will be described in more detail with reference to
The receiver 210 receives the image data signal RGB from an external device. The frame rate of the image data signal RGB received by the receiver 210 may vary. In an embodiment, for example, the frame rate of the image data signal RGB may vary between 30 Hz and 140 Hz, but is not limited thereto.
The image signal converter 220 may generate the converted image data signal R′G′B′ by processing the image data signal RGB received by the receiver 210.
The first interface 240 loads data into the memory 800 and provides the loaded data into the first register 250. Accordingly, at least a part of the data stored in the memory 800 is loaded in the first register 250.
In an embodiment, the data loaded from the memory 800 into the first register 250 may be a look-up table including information on changes in the output voltages AVDD, VON, VOFF, TVDD1, and TVDD2 of the voltage generator 700 depending on the frame rate of the image data signal R′G′B′ or changes in the electrical signals in the output circuits 740. The contents of the look-up table will be described later in more detail.
The power controller 230 may include a frequency detector 231 and an operation controller 232.
The frequency detector 231 may detect the frame rate (or frequency) of the image data signal RGB received by the receiver 210. The frequency detector 231 may provide the operation controller 232 with a signal corresponding to the detected frame rate.
The operation controller 232 generates a control signal based on the data corresponding to the frame rate of the image data signal R′G′B′ detected by the frequency detector 231 among the data loaded in the first register 250. The control signal generated in the operation controller 232 may be provided to the second interface 710 of the voltage generator 700 through the first interface 240. The control signal received by the second interface 710 is stored in the second register 720, and the compensator 730 outputs the signals corresponding to the control signal stored in the second register 720 to the output circuits 740. The compensator 730 may control the feedback circuit 7420 or the DC-DC converter 7410 of the output circuits 740. That is, the voltage generator 700 may control the output voltages AVDD, VON, VOFF, TVDD1, and TVDD2 or the electrical signals in the output circuits 740 based on the control signal outputted from the operation controller 232.
In an embodiment, for example, the lookup table loaded in the first register 250 may include information corresponding to Table 1 below.
Table 1 shows the values of the output voltages AVDD, VON, VOFF, TVDD1, and TVDD2 of the output circuits 740 according to the frame rate of the image data signal R′G′B′. Referring to Table 1, the output voltages AVDD, VON, VOFF, TVDD1, and TVDD2 of the output circuits 740 may change when the frame rate of the image data signal R′G′B′ changes. In an embodiment, as the frame rate of the image data signal R′G′B′ increases, the output voltages AVDD, VON, VOFF, TVDD1, and TVDD2 of the output circuits 740 are also increased.
However, the data in Table 1 are illustrative, and the data in Table 1 may be changed according to the size or resolution of the display panel 100.
Referring to
Referring to
Referring to
In addition, as the frame rate increases, the load of the display panel DP increases, and, accordingly, voltage drop in which the voltage drop AVDD, VON, VOFF, TVDD1, TVDD2 of the output circuit 740 becomes smaller may occur. Therefore, by arbitrarily increasing the voltage as shown in Table 1, it is possible to prevent or substantially prevent the display quality from being degraded by such a voltage drop.
In an embodiment of the inventive concept, the lookup table loaded into the first register 250 may include information corresponding to Table 2 below.
Table 2 shows an example of the value of the output current of the current controller 7425 according to the frame rate of the image data signal R′G′B′. Referring to Table 2, the output current of the current controller 7425 may change when the frame rate of the image data signal R′G′B′ changes. In an embodiment, when the frame rate of the image data signal R′G′B′ increases, the output current of the current controller 7425 also increases.
If the frame rate of the image data signal R′G′B′ increases, the ripple voltage becomes large. If the output current of the current controller 7425 also increases, the feedback circuit 7420 may quickly respond to the voltage fluctuation.
Also, a crosstalk phenomenon occurring in the display device DD may be reduced.
However, the data in Table 2 are illustrative, and the data in Table 2 may be changed according to the size or resolution of the display panel 100.
In an embodiment of the inventive concept, the lookup table loaded into the first register 250 may include information corresponding to Table 3 below.
Table 3 shows the frequency of the pulse signal PWM outputted from the PWM controller 7426 according to the frame rate of the image data signal R′G′B′. Referring to Table 3, when the frame rate of the image data signal R′G′B′ changes, the frequency of the pulse signal PWM outputted from the PWM controller 7426 may change. In an embodiment, when the frame rate of the image data signal R′G′B′ increases, the frequency of the pulse signal PWM outputted from the PWM controller 7426 also increases.
As the frame rate of the image data signal R′G′B′ increases, the ripple voltage increases. When the frequency of the pulse signal PWM outputted from the PWM controller 7426 increases, the magnitude of the ripple voltage may be reduced.
In addition, electromagnetic interference (EMI) generated in the display device DD may be prevented or substantially prevented.
However, the data in Table 3 are illustrative, and the data in Table 3 may be changed according to the size or resolution of the display panel 100.
In an embodiment of the inventive concept, the lookup table loaded into the first register 250 may include information corresponding to Table 4 below.
Table 4 shows settings in which some of the pulse signal PWM outputted from the PWM controller 7426 are skipped according to the frame rate of the image data signal R′G′B′.
Referring to
Referring to Table 4 and
As the frame rate of the image data signal R′G′B′ increases, the ripple voltage becomes larger. As the pulses of the signal outputted from the second comparator 7424 are skipped more, the ripple voltage may be reduced.
In addition, electromagnetic interference (EMI) generated in the display device DD may be prevented or substantially prevented.
However, the data of Table 4 and the waveforms of
According to an embodiment of the inventive concept, even when the frame rate of the image data signal applied from the outside changes, IR-drop, voltage ripple, crosstalk, or EMI may be prevented or substantially prevented from occurring inside the display device. Accordingly, a display device that displays high-quality images may be provided.
Although some exemplary embodiments of the inventive concept have been described, it is understood that the inventive concept should not be limited to these exemplary embodiments, but various changes and modifications can be made by one of ordinary skill in the art within the spirit and scope of the inventive concept as herein claimed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2018-0002399 | Jan 2018 | KR | national |
