The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not intended to limit the present invention, and wherein:
Hereinbelow, the display device of the present invention will be described in detail in conjunction with the embodiments with reference to the drawings.
The plurality of source side drivers 102 are arranged in a straight line along one side of the LCD panel 101. The plurality of gate side drivers 103 are arranged in a straight line along another side that intersects the one side of the LCD panel 101.
The LCD panel 101 includes panel side wiring lines 110, which are placed between mutually adjacent source side drivers 102, 102 and between mutually adjacent gate side drivers 103, 103 to electrically connect the signal lines of the mutually adjacent source side drivers 102, 102 together and connect the signal lines of the mutually adjacent gate side drivers 103, 103 together.
The display device connects the control signals and signals of power sources and so on of the source side drivers 102 and the gate side drivers 103 by way of the panel side wiring lines 110 and transfers the signals among the plurality of source side drivers 102 and the plurality of gate side drivers 103 to provide a display.
The source side drivers 102 output display data of the LCD panel 101, and the gate side drivers 103 control the gates of TFT's (Thin Film Transistors) 1 formed on the LCD panel 101.
In concrete, the plurality of source side drivers 102 receive inputs of a clock signal, gray-scale data, a control signal such as a signal that represents control timing and power via the panel side wiring lines 110. The inputted control signal and power are transferred to the adjacent source side driver 102 by way of wiring lines and buffers provided for the source side drivers 102. As described above, the control signal is inputted while being sequentially transferred, and driving signals are outputted to the LCD panel 101. That is, the control signal is inputted from a controller (not shown) to the source side driver 102 located at the left-hand end and sequentially transferred to the source side driver 102 located on the right-hand side.
On the other hand, the plurality of gate side drivers 103 receive inputs of a clock signal, a control signal such as a signal that represents control timing and power via the panel side wiring lines 110. The inputted control signal and power are transferred to the adjacent gate side driver 103 by way of wiring lines and buffers provided for the gate side drivers 103. As described above, the control signal is inputted while being sequentially transferred, and driving signals are outputted to the LCD panel 101. That is, the control signal is inputted from a controller (not shown) to the gate side driver 103 located at the upper end and sequentially transferred to the gate side driver 103 located on the lower side.
The LCD panel 101 is driven by the driving signals outputted from the source side drivers 102 and driving signals outputted from the gate side drivers 103.
The structure of one LCD pixel of the LCD panel 101 is herein described. The LCD pixel has a TFT 1, a pixel capacitance (capacitor) 2 and an auxiliary capacitance (capacitor) 3.
A gate line 5 that extends from the gate side driver 103 is connected to the gate of the TFT 1, and a source line 4 that extends from the source side driver 102 is connected to the source of the TFT 1.
A pixel electrode is connected to the TFT 1, and a common electrode Vcom is provided facing the pixel electrode. The common electrode Vcom faces in common a plurality of pixel electrodes connected to each of the TFT's 1. Liquid crystals are sealed in between the pixel electrode and the common electrode Vcom, forming the pixel capacitance 2.
Then, the TFT 1 is turned on by a signal from the gate line 5 to apply the voltage of the source line 4 to the pixel capacitance 2. The LCD pixel provides a display by varying the optical transmittance by a voltage difference between the applied voltage and the common electrode Vcom.
The auxiliary capacitance 3 has operation to assist the retention of voltage of the pixel capacitance 2, and the auxiliary capacitance 3 is placed between the drain of the TFT 1 and an electrode Vcs. The electrode Vcs may be in common with the common electrode Vcom or connected to another gate signal or provided with another voltage.
Next, the connection portion of the mutually adjacent source side drivers 102, 102 in a portion A of
The source side driver 102 is constructed of a TCP (Tape Carrier Package) 108 on which the semiconductor chips are mounted. On the back surface (on the surface located on the LCD panel 101 side) of the TCP 108 are formed driver side wiring lines 109 that are the wiring lines (as signal lines) for receiving and delivering the control signal from and to the adjacent source side driver 102, and driving signal wiring lines 120 that are the wiring lines for transferring the driving signal outputted from the drive semiconductor chip to the LCD panel 101. Then, the mutually adjacent source side drivers 102, 102 have the respective driver side wiring lines 109 connected together via the panel side wiring lines 110.
A capacitor 106 formed in the steps of fabricating the LCD panel 101 is provided for the LCD panel 101. That is, the capacitor 106 is formed of the same construction as that of the auxiliary capacitance 3 shown in
In concrete, the capacitor 106 is connected between the power line of the panel side wiring lines 110 and the GND line of the panel side wiring lines 110. That is, the capacitor 106 can be used as a bypass capacitor for preventing the voltage drop due to the influence of the impedance of the panel side wiring lines 110 and so on.
It is noted that the capacitor 106 may be connected between the control signal line of the panel side wiring lines 110 and the GND line of the panel side wiring lines 110, and the capacitor 106 can be used as a noise preventing capacitor for preventing the noises of the control signal line.
It is noted that the connection portion of the mutually adjacent gate side drivers 103, 103 has a construction similar to that of the connection portion of the mutually adjacent source side drivers 102, 102 although not shown.
According to the display device of the above construction, the capacitor 106 connected to the panel side wiring lines 110 is provided for the LCD panel 101, and the capacitor 106 is formed in the step of fabricating the LCD panel 101. Therefore, the capacitor 106 can be collectively formed on the LCD panel 101 together with the LCD pixels in the step of fabricating the LCD pixels on the LCD panel 101. This obviates the need for mounting capacitors on the drivers 102, 103 and allows the cost of the drivers 102, 103 to be reduced.
In concrete, the capacitor 106 is connected between the power line of the panel side wiring lines 110 and the common electrode Vcom of the panel side wiring lines 110. That is, the capacitor 106 can be used as a bypass capacitor for preventing the voltage drop due to the influence of the impedance of the panel side wiring lines 110 and so on.
It is noted that the capacitor 106 may be connected between the control signal line of the panel side wiring lines 110 and the common electrode Vcom, and the capacitor 106 can be used as a noise preventing capacitor for preventing the noises of the control signal line.
In concrete, the capacitor 106 is connected between the power line of the panel side wiring lines 110 and the prescribed electrode Vtmp. That is, the capacitor 106 can be used as a bypass capacitor for preventing the voltage drop due to the influence of the impedance of the panel side wiring lines 110 and so on.
It is noted that the capacitor 106 may be connected between the control signal line of the panel side wiring lines 110 and prescribed electrode Vtmp, and the capacitor 106 can be used as a noise preventing capacitor for preventing the noises of the control signal line.
With regard to the configurations of
In concrete, an end portion (terminal) of the driver side wiring 109 and an end portion (terminal) of the driving signal wiring 120 are placed along an identical side of the TCP 108. Moreover, the driver side wiring lines 109 of the mutually adjacent source side drivers 502, 502 are connected together via the panel side wiring lines 110.
The capacitor 106 is the capacitor fabricated in a step identical to that of the pixels and so on of the LCD panel 101 shown in
It is noted that the connection portion of the mutually adjacent gate side drivers 503, 503 has a construction similar to that of the connection portion of the mutually adjacent source side drivers 502, 502 although not shown.
The present invention is limited to none of the aforementioned embodiments. For example, the capacitor 106 may be provided so that it is connected to the panel side wiring line 110 between mutually adjacent gate side drivers 503, 503. Moreover, the capacitor 106 may be provided so that it is connected to at least one of all the panel side wiring lines 110.
Embodiments of the invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
Number | Date | Country | Kind |
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2006-171053 | Jun 2006 | JP | national |