Patent Application
20240257705
The present application claims priority to Republic of Kore Patent Application No. 10-2023-0012225, filed on Jan. 31, 2023, which is incorporated by reference in its entirety.
The present disclosure relates to a display device.
With the progress of the information-oriented society, various types of demands for display devices which display an image are increasing. Further, various types of display devices such as a liquid crystal display device, and an organic light emitting display device have been used.
The images displayed in the display device may be still images or moving images. If the images are moving images, the images may be various kinds such as sports images, game images, movies, and the like. The display device may reduce power consumption and extend its lifespan when the display device is driven in a variable refresh rate (VRR) mode that varies the driving frequency depending on kinds of images.
When there is little change in an input image on the display device, the pixels may be driven at a low frequency (e.g., driving at a low speed) to reduce power consumption of the display device. However, when the pixels are driven at a low speed, difference in pixel brightness may occur due to discharge of voltages of the pixels, thereby quality deterioration such as image distortion, flicker and the like may occur.
An object of the embodiments is to provide a display device capable of securing a sensing period and/or a driving preparation period during a vertical blanking period.
The objects of the embodiments of the present disclosure are not limited to the above-mentioned object, and the other technical object may be inferred from the embodiments described below.
In one embodiment, a display device comprises: a display panel including a plurality of pixels configured to display images during a first frame, a second frame that is after the first frame, and a third frame that is after the second frame, each of the first frame, the second frame, and the third frame including an active period and a blanking period that is after the active period: a counting circuit configured to count a duration of the blanking period of the first frame after termination of the active period of the first frame: a comparison circuit configured to compare the counted duration of the blanking period of the first frame with a threshold time required for sensing at least one pixel from the plurality of pixels or a threshold time required to prepare for driving the plurality of pixels during the second frame; and a delay decision circuit configured to determine whether to increase a duration of the blanking period of the first frame based on the comparison.
In one embodiment, a display device comprises: a display panel including a plurality of pixels, a plurality of data lines, and a plurality of gate lines that intersect the plurality of data lines, the plurality of pixels driven during a first frame and during a second frame that is after the first frame, each of the first frame and the second frame including an active period and a blanking period that is after the active period: a data driver configured to provide data voltages to the plurality of data lines during the active period of the first frame and the active period of the second frame, the data voltages corresponding to image data: a gate driver configured to output gate signals to the plurality of gate lines during the active period of the first frame and the active period of the second frame; and a timing controller configured to increase a duration of the blanking period of the first frame responsive to determining that a duration of the blanking period of the first frame is less than at least one of a threshold time required for sensing at least one pixel from the plurality of pixels or a threshold time required to prepare for driving the plurality of pixels during the second frame.
In one embodiment, a display device comprises: a display panel including a plurality of pixels, a plurality of data lines, and a plurality of gate lines that intersect the plurality of data lines, the plurality of pixels driven during a first frame and during a second frame that is after the first frame, and each of the first frame and the second frame including an active period and a blanking period that is after the active period: a data driver configured to provide data voltages to the plurality of data lines during the active period of the first frame and the active period of the second frame, the data voltages corresponding to image data: a gate driver configured to output gate signals to the plurality of gate lines during the active period of the first frame and the active period of the second frame; and a timing controller configured generate a non-synchronization signal responsive to a determining that a duration of the blanking period is less than at least one of a threshold time required for sensing at least one pixel from the plurality of pixels or a threshold time required to prepare for driving the plurality of pixels during the second frame, wherein the non-synchronization signal is indicative that an input active period of the second frame is not synchronized with an output active period of the second frame.
Other embodiment specifics are included in the detailed description and drawings.
According to the display device according to the embodiments, a sensing period and/or driving preparation period during a vertical blanking period may be secured.
However, the effects of the present disclosure are not limited to the above-described effects and other effects which are not described herein may be derived by those skilled in the art from the following description of the embodiments of the present disclosure.
Hereinafter, embodiments are described in more detail with reference to accompanying drawings. When an arbitrary component is described as “being on”, “being connected to “or” being linked to” another component, this should be understood to mean that still another component(s) may exist between them, although the arbitrary component may be directly connected to, or linked to, the second component.
Like reference numerals generally denote like elements. In addition, a thickness, ratio, and dimension of each component illustrated in the drawing are exaggerated for convenience of explanation. The term “and/or” includes any and all combinations of one or more of the associated listed items.
Terms used in the specification, ‘first’, ‘second’, etc. can be used to describe various components, but the components are not to be construed as being limited to the terms. The terms are only used to differentiate one component from other components. For example, the ‘first’ component may be named the ‘second’ component without departing from the scope of the present disclosure, and the ‘second’ component may also be similarly named the ‘first’ component. A singular expression includes a plural expression unless a description to the contrary is specifically pointed out in context.
Terms such as ‘below’, ‘at a lower side’, ‘on’, ‘at an upper side’ and the like are used to describe position relation of parts illustrated in the accompanying drawings. Such terms are of relative concept, and are explained based on the directions marked in the drawings.
It should be understood that terms such as ‘comprise’, or ‘have’ and the like are used only to designate that there are features, numbers, steps, operations, components, parts or combination thereof, however such terms do not preclude existence or addition of one or more another features, numbers, steps, operations, components, parts or combination thereof.
Referring to
The timing controller 10 (e.g., a circuit) may receive a video signal (RGB) and a control signal (CS) from an external host system and the like. The video signal (RGB) may include a plurality of grayscale data. The control signal (CS) may include, for example, a horizontal synchronization signal, a vertical synchronization signal and a main clock signal.
The timing controller 10 processes the video signal (RGB) and the control signal (CS) to be suitable to operational conditions of the display panel 60, and may generate and output video data (DATA), a gate driving control signal (CONT1), a data driving control signal (CONT2), an emission driving control signal (CONT3), and a power supply control signal (CONT4).
The gate driving control signal (CONT1) may include a scan timing control signal such as a gate start pulse, a gate shift clock and a gate output enable signal. The data driving control signal (CONT2) may include a data timing control signal such as a source sampling clock, a polarity control signal, a source output enable signal, and the like.
The timing controller 10 may be disposed in a control printed circuit board connected via a flexible flat cable (FFC) or a connecting medium of a flexible printed circuit (FPC) to a source printed circuit board to which the data driver 30 is bonded. For example, the timing controller 10 may be connected to the data driver 30 through an embedded clock P-P interface (EPI) wiring pair to transmit and receive data.
The gate driver 20 (e.g., a circuit) may sequentially output a gate signal by one horizontal period within one frame through a gate line (GL), in response to a gate driving control signal (CONT1) provided by the timing controller 10. Accordingly, a pixel row connected to each gate line (GL) is turned on by one horizontal period. During one horizontal period, a data signal may be applied to a pixel row which is turned on by a gate line (GL).
The gate driver 20 may comprise of stage circuits each of which is connected to a plurality of gate lines (GL), and may be configured in a in a Gate-In-Panel (GIP) method in the display panel 60. The gate driver 20 may include a shift register, or a level shifter, and the like.
The data driver 30 (e.g., a circuit) converts image data (DATA) in a digital format provided by the timing controller 10 into an analogue data signal according to the data driving control signal (CONT2). The data driver 30 may apply the analogue data signal to the corresponding pixels PX through a data line (DL).
The data driver 30 may be configured as a source drive circuit or source drive integrated circuit. The data driver 30 may be connected to a bonding pad of the display panel 60 in a tape automated bonding (TAB) or chip on glass (COG) method, or disposed directly in the display panel 60. In some instances, the data driver 30 may be integrated with the display panel 60.
The light emission driver 40 (e.g., a circuit) may generate light emission signals based on the emission driving control signal (CONT3) output by the timing controller 10. The light emission driver 40 may provide the generated gate signals to the pixels PX through a plurality of emission lines (EL).
The power supplying unit 50 (e.g., a power supplying circuit) may convert a voltage input from the outside into a high potential driving voltage (ELVDD) and a low potential driving voltage (ELVSS), which are standard voltages used inside the display device 1, based on the power supply control signal (CONT4). The power supplying unit 50 may output the generated voltages (ELVDD, ELVSS) to components through power supply lines PL1 and PL2. The power supplying unit 50 may be disposed in the control printed circuit board in which the timing controller 10 is disposed. The power supplying unit 50 may be referred to as a power management integrated circuit (PMIC).
A plurality of pixels PX (or, referred to as sub-pixels) are disposed in the display panel 60. The pixels PX may be, for example, disposed in a form of a matrix in the display panel 60. The pixels PX disposed in one pixel row are connected to the same gate line GL, and the pixels PX disposed in one column are connected to the same data line DL. The pixels PX may emit light at luminance corresponding to the gate signals supplied through the data lines.
In an embodiment, each pixel PX may display one color among red, green and blue. In another embodiment, each pixel PX may display one color among cyan, magenta and yellow. In various embodiments, each pixel PX may display one color among red, green, blue and white.
The timing controller 10, the gate driver 20, the data driver 30, the light emission driver 40, and the power supplying unit 50 each may be configured as a separate integrated circuit (IC), or at least some of them may be integrated into an integrated circuit. Moreover, at least one among the gate driver 20 and the light emission driver 40 may be configured in In-Panel method through which the drivers are integrated into the display panel 60.
The display device 1 according to the embodiment of the present disclosure may operate by using a variable refresh rate (VRR) mode by which the driving frequencies can be varied. The refresh rate may mean an interval/frequency at which the data voltage is supplied (programmed) to the pixels. For example, the display device 1 may be driven at a refresh rate which is lower or higher than a certain reference refresh rate. Driving the display device 1 at a refresh rate that is less than a reference refresh rate may be referred to as ‘a low speed driving’, and driving the display device 1 at a refresh rate that is greater than the reference refresh rate may be referred to as ‘a high speed driving’. At low speed driving, the display device 1 programs data voltages in pixels at a lower interval/frequency than the reference refresh rate, and at high speed driving, the display device 1 programs data voltages in pixels at a higher interval/frequency than the reference refresh rate. The refresh rate may be determined according to kinds of images being displayed and the like, but is not limited thereto.
Referring to
The pixels PX may drive organic light-emitting diodes OLED by controlling a driving current flowing in the organic light-emitting diodes OLED. The pixel PX may include a driving transistor DT, a scan transistor T1, an initialization transistor T2, and a storage capacitor CST. Each of the transistors DT and T1 to T2 may include a respective first electrode, a respective second electrode, and a respective gate electrode. One among the first electrode and the second electrode may be a source electrode, and the other among them may be a drain electrode.
Each of the transistors DT and T1 to T2 may be a PMOS transistor or an NMOS transistor. Hereinafter, it will be mainly described that each of the transistors DT and T1 to T2 is an NMOS transistor. Accordingly, the transistors DT and T1 to T2 may be turned on when a high-level voltage is applied thereto.
The OLED may include an anode electrode and a cathode electrode. The anode electrode of the OLED may be connected to a second node N2, and a cathode electrode may be connected to the low potential driving voltage (ELVSS).
The driving transistor DT may include the first electrode receiving the high potential driving voltage (ELVDD), the second electrode connected to the second node N2, and the gate electrode connected to a first node N1. The driving transistor DT may provide the driving current to the OLED based on a voltage of the first node N1 (or, the data voltage stored in the storage capacitor CST to be described later).
A first transistor T1 may include the first electrode receiving the data voltage Vdata, the second electrode connected to the first node N1, and the gate electrode receiving a first scan signal SCAN1 through one gate line GL among the gate lines (GL in
A second transistor T2 may include the first electrode receiving an initialization voltage Vref, the second electrode connected to the second node N2, and the gate electrode receiving the second scan signal SCAN2 through one gate line GL among the gate lines (GL in
The storage capacitor CST may be connected between the first node N1 and a second node N2. The storage capacitor CST may store or maintain a difference voltage obtained between the data voltage Vdata supplied to the first node N1 and the initialization voltage Vref supplied to the second node N2.
Referring to
The timing controller 10 may include, for example, a counting unit 11 (e.g., a circuit), a comparison unit 13 (e.g., a circuit), a delay decision unit 15 (e.g., a circuit), a data enable output unit 17 (e.g., a circuit), and a synchronization signal generation unit 18 (e.g., a circuit).
Although not illustrated, image data (DATA in
The input active period may be a period in which a data enable supplying unit 35 (e.g., a circuit) of an external device of the timing controller 10 in
The input blank period may be a period obtained by subtracting the input active period from the predetermined duration of the frames F1 to F3. In
The output active period may be a period in which the data enable supplying unit 35 of the external device of the timing controller 10 in
The output blank period may be a period obtained by subtracting the output active period from the duration of the frames F1 to F3 determined by the delay decision unit 15. In
In the first active period ta1, the input active period and the output active period (or the first active period ta1) may be synchronized. Synchronization of the input active period and the output active period (or the first active period ta1) may be controlled by the synchronization signal generation unit 18. When a synchronization signal SY1 is provided to the data enable output unit 17 by the synchronization signal generation unit 18, the data enable output unit 17 is synchronized with the input active period in the first active period ta1, and may supply the data enable signal DE to the data driver 30. The data enable signal DE may have a first voltage level VDE1 and a second voltage level VDE2 that is less than the first voltage level VDE1 that are repeated according to interval of the horizontal synchronization signal hsync. The scan transistor T1 may be turned on in response to the data enable signal DE at the first voltage level VDE1 and the data voltage Vdata may be supplied from the first electrode.
After termination of the first active period ta1, the first blanking period tb1 begins. In the first blanking period tb1, the data enable signal DE is maintained at the second voltage level VDE2. The counting unit 11 counts a duration (a) of the first blanking period tb1 in the first blanking period tb1 (refer to S10 in
In the comparison unit 13, data on a minimum time (e.g., a threshold time) required for sensing a pixel and data on a minimum time for preparing driving is stored. In the present disclosure, data on a minimum time for sensing may be data on a threshold time required for sensing some pixels PX of the display panel 60. For example, the data on a minimum time for sensing may be data on a minimum time required for sensing characteristics of pixels PX of at least one color (for example, red, green, blue, or white) of one pixel row of the display panel 60. The characteristics may be a threshold voltage of the driving transistor DT and the mobility of the driving transistor DT, for example. The data on a minimum time for preparing driving may be data on a threshold time required for reading image data output through the image data output unit from a storage medium of an external device during the second active period ta2 of the next frame (e.g., F2) and storing the data in the memory of the timing controller 10. As a result of the synchronization signal check (S20), when the synchronization signal SY1 is provided to the data enable output unit 17 by the synchronization signal generation unit 18, the sensing of the display device and the driving preparation of the display device may be performed in the first blanking period tb1. For example, the sensing of the display device may be sensing of a mobility value of the driving transistor DT, but is not limited thereto. Since sensing of the mobility value of the driving transistor DT is a technique widely known in the art, a detailed description thereof will be omitted.
As a result of the synchronization signal check (S20), when the synchronization signal SY1 is provided to the data enable output unit 17 by the synchronization signal generation unit 18, the comparison unit 13 compares the counted duration (a) of the first blanking period tb1 with the minimum time for sensing (refer to S30). The minimum time for preparing driving may be shorter than the minimum time for sensing. When it is determined that the counted duration (a) of the first blanking period tb1 is longer than the minimum time for sensing (refer to N), the delay decision unit 15 controls the synchronization signal generation unit 18 to provide a synchronization signal SY1 to the data enable output unit 17. After termination of the first blanking period tb1_R, the data enable supplying unit 35 of the external device reads data enable signals to be provided to the data enable output unit 17 from an external memory according to the synchronization signal SY1. At the same time, the data enable supply unit of the external device supplies the data enable signals DE to the data enable output unit 17 (input active period=output active period, refer to synchronization of an input/output sync (S43) in
On the other hand, when it is determined that the counted duration (a) of the first blanking period tb1_R is shorter than the minimum time for sensing (refer to Y in
The delay decision unit 15 controls the synchronization signal generation unit 18 to provide a non-synchronization signal SY2 to the data enable output unit 17, and at the same time, calculates the first time of delay tb. The first time of delay tb may be equal to an above-described difference between the counted duration (a) of the first blanking period tb1_R and the minimum time (e.g., threshold time) for sensing the characteristic of pixels or the difference between the counted duration (a) of the first blanking period tb1_R and the minimum time (e.g., threshold time) to prepare for driving the pixels during the second frame F2.
After termination of the first blanking period tb1, the second active period ta2 of the second frame F2 begins. The second active period ta2 may be unsynchronized with the second input active period B by the non-synchronization signal SY2. Thus, the non-synchronization signal SY2 indicates that the input active period B of the second frame F2 is not synchronized with the output active period B of the second frame F2 as shown in
After termination of the second active period ta2, the second blanking period tb2 begins. In the second blanking period tb2, the data enable signal DE at the second voltage level VDE2 is maintained. The counting unit 11 counts a duration (b) of the second blanking period tb2 in the second blanking period tb2 (refer to S10 in
As a result of the synchronization signal check (S20), when the non-synchronization signal SY2 is provided to the data enable output unit 17 by the synchronization signal generation unit 18 due to the non-synchronization, only the driving preparation of the display device may be performed in the second blanking period tb2 without performing the sensing of the display device.
As a result of the synchronization signal check (S20), when the non-synchronization signal SY2 is provided to the data enable output unit 17 by the synchronization signal generation unit 18, the comparison unit 13 compares the counted duration (b) of the second blanking period tb2 with the minimum time for sensing. (refer to S40 in
On the other hand, as illustrated in
The delay decision unit 15 controls the synchronization signal generation unit 18 to provide a non-synchronization signal SY2 to the data enable output unit 17, and at the same time, calculates the second time of delay tb_1. The second time of delay tb_1 may be equal to an above-described difference between the counted duration (b) of the second blanking period tb2_R and the minimum time for preparing driving.
According to an embodiment, as described above, it is possible to secure a blanking period equal to or greater than the minimum time for sensing pixels or the minimum time for preparing driving, by measuring a duration of the blanking period of the current frame, comparing the measured duration of the blanking period with the minimum time for sensing or the minimum time for preparing driving, and extending the blanking period of the corresponding frame when it is determined that the duration of the blanking period is shorter than the minimum time for sensing or the minimum time for preparing driving. By doing so, sensing or driving preparation of the display device may be sufficiently performed in the display device having different driving frequencies.
Hereinafter, the display device according to another embodiment is described.
Referring to
The other descriptions are described above with reference to
For example, a display device may include: a first frame, a second frame, and a third frame each including an active period and a blanking period: a counting unit configured to count a duration of a blanking period of the first frame after termination of an active period of the first frame; a comparison unit configured to compare the counted duration of the blanking period of the first frame with a minimum time for sensing or a minimum time for preparing driving: and a delay decision unit configured to determine whether to delay the blanking period of the first frame based on the comparison result of the comparison unit.
For example, the display device may further include: a synchronization signal generation unit, and the synchronization signal generation unit may generate a non-synchronization signal when the delay decision unit determines to delay the blanking period of the first frame.
For example, the synchronization signal generation unit may generate a synchronization signal when the delay decision unit determines not to delay the blanking period of the first frame.
For example, the synchronization signal generation unit may calculate a time of delay of the blanking period of the first frame by comparing the minimum time for sensing or the minimum time for preparing driving with the duration of the blanking period of the first frame.
For example, the display device may further include: a data enable output unit, and the data enable output unit may provide a data enable signal delayed according to data on the time of delay calculated by the delay decision unit and the non-synchronization signal, when the delay decision unit determines to delay the blanking period of the first frame.
For example, the display device may further include: a data enable output unit, and the data enable output unit may provide a data enable signal synchronized during the active period of the second frame, when the delay decision unit determines not to delay the blanking period of the first frame.
For example, the minimum time for sensing may be a minimum time required for sensing pixels of a display panel.
For example, the display device may further include: a plurality of pixels: a data driver configured to convert a data voltage provided to the pixels into image data: and an image data output unit configured to output the image data to the data driver.
For example, the minimum time for preparing driving may be a minimum time required for reading the image data provided by the second frame to the data driver from a storage medium of an external device and storing the image data in a memory device.
The present disclosure has been described in more detail with reference to the exemplary embodiments, but the present disclosure is not limited to the exemplary embodiments. It will be apparent to those skilled in the art that various modifications can be made without departing from the technical sprit of the invention. Accordingly, the exemplary embodiments disclosed in the present disclosure are used not to limit but to describe the technical spirit of the present disclosure, and the technical spirit of the present disclosure is not limited to the exemplary embodiments. Therefore, the exemplary embodiments described above are considered in all respects to be illustrative and not restrictive. The protection scope of the present disclosure must be interpreted by the appended claims and it should be interpreted that all technical spirits within a scope equivalent thereto are included in the appended claims of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0012225 | Jan 2023 | KR | national |
