The present disclosure relates generally to a display device. More particularly, the present disclosure relates to a display device that can change operating conditions by a communication between a timing controller and a power management integrated circuit.
Generally, a display device includes a display panel, a display panel driving circuit including a scan driver, a data driver, a timing controller, ortho like that drives the display panel, and a power management integrated circuit that generates driving voltages for driving the display panel and the display panel driving circuit. The timing controller and the power management integrated circuit may communicate with each other to change an operating condition (e.g., change of levels of the driving voltages for driving the display panel and the display panel driving circuit).
An I2C communication that supports a simple connection between hardware devices is widely used due to its simplicity of having an SDA line for transferring a data signal and an SCL line for transferring a clock signal. Usually, performance of the power management integrated circuit is determined by the efficiency of performing an operating condition change. Thus, a manufacturer of the power management integrated circuit tries to keep their technologies for performing the operating condition change or the like from being leaked to other manufacturers.
The power management integrated circuit may be designed to operate under various operating conditions using the I2C communication after connecting to a display panel and a display panel driving circuit. The specifications of the display panel and/or the display panel driving circuit may be identified to the power management integrated circuit, and one may easily investigate and understand a proprietary technology of the power management integrated circuit for performing the operating condition change or the like after connecting to the display panel and/or the display panel driving circuit. As a result, there is a problem that the proprietary technology (e.g., intellectual property) of a manufacturer of a specific power management integrated circuit can be leaked to other manufacturers.
The present disclosure provides a display device capable of selectively operating a power management integrated circuit in a normal mode (e.g., a high performance mode) or in a protection mode (e.g., a limited performance mode or a shut-down mode). The power management integrated circuit may perform a specific communication (e.g., an I2C communication) with the timing controller to authenticate a change of operating conditions, for example, change of levels of driving voltages for driving the display panel and the display panel driving circuit.
According to one embodiment, a display device may include a display panel, a display panel driving circuit including a timing controller and configured to drive the display panel, and a power management integrated circuit configured to generate a plurality of driving voltages for driving the display panel and the display panel driving circuit, receive driving set data from the timing controller, store driving hex values corresponding to the driving set data in first internal registers, and determine voltage levels of the plurality of driving voltages based on the driving hex values. The power management integrated circuit may divide the driving hex values into upper decimal values and lower decimal values, derive a result decimal value by applying the upper decimal values and the lower decimal values to a first authentication formula, generate a result hex value based on the result decimal value, compare an authentication hex value corresponding to authentication data received from the timing controller with the result hex value, and selectively operate in a normal mode or in a protection mode based on a comparison result between the authentication hex value and the result hex value.
In an embodiment, the power management integrated circuit may operate in the normal mode if the authentication hex value is consistent with the result hex value and operate in the protection mode if the authentication hex value is inconsistent with the result hex value.
In an embodiment, the power management integrated circuit may operate in the normal mode if the authentication hex value is consistent with the result hex value and operate in the protection mode if the authentication hex value is not received from the timing controller within a preset time.
In an embodiment, if first driving set data that are determined in a first image frame is different from second driving set data that are determined in a second image frame following the first image frame, an authentication operation may be performed between the timing controller and the power management integrated circuit during the second image frame.
In an embodiment, the timing controller and the power management integrated circuit may perform an inter integrated circuit (PC) communication for performing the authentication operation. In addition, the timing controller may provide at least one updated driving set data among the driving set data that is changed from the first driving set data to the second driving set data to the power management integrated circuit and provide the authentication data to the power management integrated circuit during the second image frame.
In an embodiment, the timing controller may determine the driving set data based on image data input in each image frame, store the driving hex values corresponding to the driving set data in second internal registers, and transmit the driving set data to the power management integrated circuit.
In an embodiment, the timing controller may compare first driving set data that are determined in a first image frame with second driving set data that are determined in a second image frame following the first image frame. In addition, the timing controller may update at least one updated driving set data among the driving set data that is changedfrom the first driving set data to the second driving set data in the second internal registers and transmit the at least one updated driving set data to the power management integrated circuit during the second image frame.
In an embodiment, the power management integrated circuit may update the at least one updated driving set data received from the timing controller in the first internal registers during the second image frame.
In an embodiment, the timing controller may divide the driving hex values into the upper decimal values and the lower decimal values, derive an authentication decimal value by applying the upper decimal values and the lower decimal values to a second authentication formula, generate the authentication hex value based on the authentication decimal value, and transmit the authentication hex value to the power management integrated circuit.
In an embodiment, the upper decimal values and the lower decimal values may be used as variables in the first authentication formula.
In an embodiment, the power management integrated circuit may have an exclusive access to the first authentication formulathat the timing controller may not have.
In an embodiment, the upper decimal values and the lower decimal values may be used as variables in the second authentication formula.
In an embodiment, the timing controller may have an exclusive access to the second authentication formula that the power management integrated circuit may not have.
In an embodiment, the authentication hex value may be consistent with the result hex value if the first authentication formula is same as the second authentication formula, and the authentication hex value may not inconsistent with the result hex value if the first authentication formula is different from the second authentication formula.
In an embodiment, the power management integrated circuit may further include a first authentication register for storing the result hex value, and a first size of the first authentication register may be half of a second size of each of the first internal registers.
In an embodiment, the timing controller may further include a second authentication register for storing the authentication hex value, and a third size of the second authentication register may be half of a fourth size of each of the second internal registers.
In an embodiment, the first authentication register may be stored in a first portion of at least one of the first internal registers, and the second authentication register may be stored in a second portion of at least one of the second internal registers.
In an embodiment, the power management integrated circuit may operate at high-performance based on the power management integrated circuit operating in the normal mode.
In an embodiment, the power management integrated circuit may operate at limited performance lower than the high performance in the protection mode.
In an embodiment, the power management integrated circuit may be shut down in the protection mode.
The display device disclosed herein may selectively operate the power management integrated circuit in a normal mode (e.g., a high performance mode) or in a protection mode (e.g., a limited performance mode or a shut-down mode) based on an authentication between the timing controller and the power management integrated circuit via a specific communication to change operating conditions (e.g., voltage levels of driving voltages for driving a display panel and a display panel driving circuit). The power management integrated circuit generates the driving voltages, receives driving set data from the timing controller included in the display panel driving circuit, stores driving hex values corresponding to the driving set data in first internal registers, and determines the operating conditions based on the driving hex values. The power management integrated circuit divides the driving hex values into upper decimal values and lower decimal values, derives a result decimal value by applying the upper decimal values and the lower decimal values to a first authentication formula, generates a result hex value based on the result decimal value, compares an authentication hex value corresponding to authentication data received from the timing controller with the result hex value, and selectively operates in the normal mode or in the protection mode based on a comparison result between the authentication hex value and the result hex value. As a result, when a display panel and/or a display panel driving circuit are connected to the power management integrated circuit, the power management integrated circuit may not operate in the normal mode if the authentication between the timing controller and the power management integrated circuit fails, so that a proprietary technology applied to the power management integrated circuit by a manufacturer of the power management integrated circuit may be prevented from being leaked to other manufacturers. However, the effects of the present inventive concept are not limited thereto. It is understood that the present inventive concept may be extended without departing from the spirit and the scope of the present disclosure.
Illustrative, non-limiting embodiments of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.
Hereinafter, embodiments of the present disclosure will be explained in detail with reference to the accompanying drawings.
Referring to
The display panel 110 may include a plurality of pixels 111. The pixels 111 may be arranged in various configurations (e.g., a matrix) in the display panel 110. Each of the pixels 111 may correspond to at least one of a red displaying pixel, a green displaying pixel, and a blue displaying pixel. The display panel driving circuit 120 may drive the display panel 110. The display panel driving circuit 120 may include a scan driver (not shown), a data driver (not shown), and a timing controller 125. The scan driver may be electrically connected to the display panel 110 via scan lines and provide a scan signal SS to the pixels 111 of the display panel 110 via the scan lines. The data driver may be electrically connected to the display panel 110 via data lines and provide a data signal DS to the pixels 111 of the display panel 110 via the data lines. The timing controller 125 may control the scan driver and the data driver. In addition, the timing controller 125 may perform a specific processing (e.g., a deterioration compensation processing) on image data that is input from an external component. In some embodiments, the timing controller 125 may perform a specific communication (e.g., an I2C communication) with the power management integrated circuit 130 to change operating conditions. For example, the timing controller 125 may communicate with the power management integrated circuit 130 to control the power management integrated circuit 130 to change voltage levels of driving voltages (e.g., a high power voltage ELVDD, a low power voltage ELVSS, and an analog high voltage AVDD) for driving the display panel 110 and the display panel driving circuit 120. Hereinafter, the high power voltage ELVDD, the low power voltage ELVSS, and the analog high voltage AVDD may be collectively referred to as driving voltages. In another example, the timing controller 125 may communicate with the power management integrated circuit 130 to control the power management integrated circuit 130 to perform a specific operation for the display panel 110 and the display panel driving circuit 120.
The power management integrated circuit 130 may generate a plurality of driving voltages denoted as POW for driving the display panel 110 and the display panel driving circuit 120, receive driving set data DSD from the timing controller 125 included in the display panel driving circuit 120, store driving hex values corresponding to the driving set data DSD in first internal registers FDR, and determine operating conditions including the voltage levels of the driving voltages based on the driving hex values denoted as CTL. As illustrated in
The power management integrated circuit 130 may include a first authentication register FAR for storing the result hex value that is derived (or calculated) based on the driving hex values. A size of the first authentication register FAR may be smaller than a size of each of the first internal registers FDR. For example, the size (e.g., 4 bits) of the first authentication register FAR may be half of the size (e.g., 8 bits) of each of the first internal registers FUR. In an embodiment, as illustrated in
According to one embodiment, the power management integrated circuit 130 may divide a driving hex value stored in the first internal registers FDR in an upper decimal value corresponding to the upper 4 bits and a lower decimal value corresponding to the lower 4 bits. In this case, the upper decimal value may have a value between 0 and 15, and the lower decimal may also have a value between 0 and 15. For example, when ‘A3’ (i.e., a binary value of ‘10100011’) is stored as a k-th driving hex value in the first internal register FDR corresponding to the k-th register address REG-ADR(k)), where k is an integer between 1 and n, the k-th driving hex value may be divided into a hex value ‘A’ (i.e., ‘1010’) corresponding to the upper 4 bits and a hex value ‘3’ (i.e., ‘0011’) corresponding to the lower 4 bits. In this case, the hex value ‘A’ (i.e., ‘1010’) corresponding to the upper 4 bits may be expressed by a decimal value ‘10’ (also referred to as an upper decimal value), and the hex value ‘3’ (i.e., ‘0011’) corresponding to the lower 4 bits may be expressed by a decimal value ‘3’ (also referred to as a lower decimal value).
Next, the power management integrated circuit 130 may derive a result decimal value by applying the upper decimal value and the lower decimal value that that correspond to the driving hex value stored in the first internal registers FDR to a first authentication formula and generate a result hex value based on the result decimal value. The power management integrated circuit 130 may use the upper decimal value and the lower decimal value as variables in the first authentication formula to generate the result decimal value, convert the result decimal value to a hex value, and determine at least a portion (e.g., a hex value corresponding to the upper 4 bits and/or a hex value corresponding to the lower 4 bits) of the hex value as the result hex value. Because only the power management integrated circuit 130 can access the first authentication formula and determine the result decimal value, the result hex value that is generated based on the result decimal value can be used as a password for performing an authentication operation between the timing controller 125 and the power management integrated circuit 130.
Subsequently, the power management integrated circuit 130 may compare an authentication hex value corresponding to authentication data AD received from the timing controller 125 with the result hex value and selectively operate in a normal mode or in a protection mode based on the consistency between the authentication hex value and the result hex value. For example, the power management integrated circuit 130 may operate at high performance when the power management integrated circuit 130 operates in the normal mode. On the other hand, the power management integrated circuit 130 may operate at limited performance that is lower than the high performance or may be shut down or power off when the power management integrated circuit 130 operates in the protection mode.
In an embodiment, the power management integrated circuit 130 may operate in the normal mode if the authentication hex value corresponding to the authentication data AD received from the timing controller 125 is consistent with (or matches) the result hex value generated in the power management integrated circuit 130 and operate in the protection mode if the authentication hex value corresponding to the authentication data AD received from the timing controller 125 is inconsistent with (or does not match) the result hex value generated in the power management integrated circuit 130. In another embodiment, the power management integrated circuit 130 may operate in the normal mode if the authentication hex value corresponding to the authentication data AD received from the timing controller 125 is consistent with the result hex value generated in the power management integrated circuit 130 and operate in the protection mode if the authentication hex value corresponding to the authentication data AD is not received from the timing controller 125 within a preset time. That is, the power management integrated circuit 130 may determine not to operate at the high performance if the authentication hex value corresponding to the authentication data AD received from the timing controller 125 is inconsistent with the result hex value generated in the power management integrated circuit 130 or if the authentication hex value corresponding to the authentication data AD is not received from the timing controller 125 within a preset time. In this case, the power management integrated circuit 130 may operate at the limited performance that is lower than the high performance or may be shut down. In this manner, a proprietary technology (e.g., intellectual property) applied to the power management integrated circuit 130 may be prevented from being leaked to other manufacturers.
The power management integrated circuit 130 may receive the authentication hex value corresponding to the authentication data AD from the timing controller 125 and compare it with the result hex value. The timing controller 125 may determine the driving set data DSD based on the input image data in each image frame, store the driving hex values corresponding to the driving set data DSD in the second internal registers SDR, and transmit the driving set data DSD to the power management integrated circuit 130. As illustrated in
According one embodiment, the timing controller 125 may divide a driving hex value stored in the second internal registers SDR in an upper decimal value corresponding to the upper 4 bits and a lower decimal value corresponding to the lower 4 bits. The timing controller 125 may derive an authentication decimal value by applying the upper decimal value and the lower decimal value that correspond to the driving hex value stored in the second internal registers SDR to a second authentication formula, generate the authentication hex value based on the authentication decimal value, and transmit the authentication data AD corresponding to the authentication hex value to the power management integrated circuit 130. The timing controller 125 may use the upper decimal value and the lower decimal value as variables in the second authentication formula to generate the authentication decimal value, convert the authentication decimal value to a hex value, and determine at least a portion (e.g., a hex value corresponding to the upper 4 bits and/or a hex value corresponding to the lower 4 bits) of the hex value as the authentication hex value. Because only the timing controller 125 can access the second authentication formula and determine the authentication decimal value, the authentication hex value that is generated based on the authentication decimal value can be used as a password for performing the authentication operation between the timing controller 125 and the power management integrated circuit 130.
The timing controller 125 may include a second authentication register SAR for storing the authentication hex value that is derived (or calculated) based on the driving hex values. A size of the second authentication register SAR may be smaller than a size of each of the second internal registers SDR. For example, the size (e.g., 4 bits) of the second authentication register SAR may be half of the size (e.g., 8 bits) of each of the second internal registers SDR. In an embodiment, as illustrated in
As described above, the authentication operation between the timing controller 125 and the power management integrated circuit 130 may be performed by determining whether the authentication hex value generated in the timing controller 125 is consistent with the result hex value generated in the power management integrated circuit 130. In a case where the first internal registers FDR included in the power management integrated circuit 130 and the second internal registers SDR included in the timing controller 125 store the same driving hex values (i.e., the same driving set data), the authentication hex value generated in the timing controller 125 may be consistent with the result hex value generated in the power management integrated circuit 130 as long as the first authentication formula of the power management integrated circuit 130 is the same as the second authentication formula of the timing controller 125. In this case, the authentication between the timing controller 125 and the power management integrated circuit 130 may be successful if the first authentication formula of the power management integrated circuit 130 is the same as the second authentication formula of the timing controller 125. On the other hand, the authentication hex value generated in the timing controller 125 may be inconsistent with the result hex value generated in the power management integrated circuit 130 if the first authentication formula of the power management integrated circuit 130 is different from the second authentication formula of the timing controller 125 (or if the timing controller 125 does not include the second authentication formula for deriving the authentication hex value). In this case, the authentication between the timing controller 125 and the power management integrated circuit 130 may be unsuccessful if the first authentication formula of the power management integrated circuit 130 is different from the second authentication formula of the timing controller 125 (or if the timing controller 125 does not include the second authentication formula for deriving the authentication hex value). For example, in a case where the timing controller 125 is not manufactured by a manufacturer of the power management integrated circuit 130, the timing controller 125 may not possess the first authentication formula of the power management integrated circuit 130 for deriving the result hex value, and thus the authentication hex value generated in the timing controller 125 may be inconsistent with the result hex value generated in the power management integrated circuit 130 or the timing controller 125 may not even provide the authentication hex value. Thus, the power management integrated circuit 130 may determine not to operate at the high performance but to operate at the limited performance lower than the high performance or may be shut down. As a result, the power management integrated circuit 130 may not allow the timing controller 125 that does not possess a proper authentication formula to operate in the high performance mode. In this manner, a proprietary technology (e.g., intellectual property) applied to the power management integrated circuit 130 may be prevented from being leaked to other manufacturers.
In some embodiments, the authentication operation between the timing controller 125 and the power management integrated circuit 130 may be performed according to an update of the driving set data DSD that are determined based on the input image data in each image frame. For example, if a first driving set data corresponding to a first image frame (also referred to as a previous image frame) is different from a second driving set data corresponding to a second image frame (also referred to as a current image frame) following the first image frame, the authentication operation may be performed during the second image frame. In this case, the timing controller 125 may provide the second driving set data that is different from the first driving set data to the power management integrated circuit 130 and then may provide the authentication data AD for performing the authentication operation to the power management integrated circuit 130 during the second image frame. Specifically, if the timing controller 125 determines that the second driving set data in the second image frame is different from the first driving set data in the first image frame, the timing controller 125 may update the driving set data DSD in the second internal registers SDR and transmit the updated driving set data DSD to the power management integrated circuit 130 during the second image frame. Since the driving hex values are divided into the upper decimal values and the lower decimal values, the timing controller 125 may derive the authentication decimal value by applying the upper decimal values and the lower decimal values to the second authentication formula and store the authentication decimal value in the second authentication registers SAR. The power management integrated circuit 130 may receive the updated driving set data DSD from the timing controller 125 and update the driving set data DSD in the first internal registers FDR during the second image frame. Since the updated driving set data DSD is divided into the upper decimal values and the lower decimal values, the power management integrated circuit 130 may derive the result decimal value by applying the upper decimal values and the lower decimal values to the first authentication formula and store the result decimal value in the first authentication registers FAR. Next, the timing controller 125 may transmit the authentication data AD corresponding to the authentication decimal value stored in the second authentication register SAR to the power management integrated circuit 130, and the power management integrated circuit 130 may compare the authentication decimal value received from the timing controller 125 with the result decimal value stored in the first authentication register FAR and determine to selectively operate in the normal mode or in the protection mode according to according to a comparison result between the authentication hex value and the result hex value.
Referring back to
Referring to
For example, as illustrated in
Next, the first image frame 1F may start in response to the periodic signal TE, the second I2C communication (denoted as TB) may be performed between the timing controller 125 and the power management integrated circuit 130 at a rising edge of the periodic signal TE, and the driving set data DSD may be determined based on the image data input in the first image frame 1F. The voltage levels of the analog high voltage AVDD, the high power voltage ELVDD, and the low power voltage ELVSS may be determined based on the driving hex values corresponding to the driving set data DSD in the first image frame 1F. In
Subsequently, the second image frame 2F may start in response to the periodic signal TE, the third I2C communication (denoted as TC) may be performed between the timing controller 125 and the power management integrated circuit 130 at a rising edge of the periodic signal TE, and the driving set data DSD may be determined based on the image data input in the second image frame 2F. The voltage levels of the analog high voltage AVDD, the high power voltage ELVDD, and the low power voltage ELVSS may be determined based on the driving hex values corresponding to the driving set data DSD in the second image frame 2F. In the present example of
Subsequently, the third image frame 3F may start in response to the periodic signal TE, the fourth PC communication (denoted as TD) may be performed between the timing controller 125 and the power management integrated circuit 130 at a rising edge of the periodic signal TE, and the driving set data DSD may be determined based on the image data input in the third image frame 3F. The voltage levels of the analog high voltage AVDD, the high power voltage ELVDD, and the low power voltage ELVSS may be determined based on the driving hex values corresponding to the driving set data DSD in the third image frame 3F. In the present example of
Referring to
The timing controller 125 may receive the image data IMG from an external component (e.g., an image processor or the like) according to an image frame (S210) and determine the driving set data DSD and the authentication data AD based on the image data IMG (S220). Here, the timing controller 125 may store the driving set data DSD in the second internal register SDR and the authentication data AD in the second authentication register SAR, respectively.
In an embodiment, as illustrated in
In the example of
In the example of
When storing the driving set data DSD that are determined based on the image data IMG in the second internal registers SDR, the timing controller 125 may not update all of the driving set data DSD in the second internal registers SDR in each image frame. Instead, the timing controller 125 may update only anupdated driving set data UDSD. In other words, the timing controller 125 may compare the previous driving set data DSD determined in the previous image frame with the current driving set data DSD determined in the current image frame and update only the driving set data DSD that is updated from the previous driving set data DSD to the current driving set data DSD that is different from the previous driving set data DSD in the second internal registers SDR. For example, as illustrated in
In addition, the timing controller 125 may divide the driving hex values stored in the second internal registers SDR into the upper decimal values and the lower decimal values, derive the authentication decimal value by applying the upper decimal values and the lower decimal values to the second authentication formula, and generate the authentication hex value AHV based on the authentication decimal value. In the example of
For example, the timing controller 125 may generate the authentication hex value AHV (i.e., ‘1’) by converting the authentication decimal value (i.e., ‘1’) to a hex value. Since the authentication hex value AHV is stored in the second authentication register SAR as a portion of the second internal register SDR corresponding to the ninth register address ‘08h’ and have a value of ‘1’, ‘1E’ may be stored in the second authentication register SAR (i.e., the upper 4 bits UDV) and the second internal register SDR (i.e., the lower 4 bits LDV). The timing controller 125 may compare the previous driving set data DSD determined in the previous image frame with the current driving set data DSD determined in the current image frame and update only the updated driving set data UDSD that is changed from the previous driving set data DSD to the current driving set data DSD in the second internal registers SDR. As illustrated in
Subsequently, the timing controller 125 may transmit the driving set data DSD that are determined based on the image data IMG to the power management integrated circuit 130 (S230). Here, the power management integrated circuit 130 may store the driving set data DSD in the first internal register FDR and the result hex value RHV in the first authentication register FAR, respectively.
In an embodiment, as illustrated in
In the example of
In the example of
The timing controller 125 may not transmit all of the driving set data DSD that are determined based on the image data IMG in each image frame to the power management integrated circuit 130. Instead, the timing controller 125 may transmit only the updated driving set data UDSD to the power management integrated circuit 130. Thus, the power management integrated circuit 130 may update only the updated driving set data UDSD in the first internal registers FDR. For example, as illustrated in
In addition, the power management integrated circuit 130 may divide the driving hex values stored in the first internal registers FDR into the upper decimal values and the lower decimal values, derive the result decimal value by applying the upper decimal values and the lower decimal values to the first authentication formula, and generate the result hex value RHV based on the result decimal value (S240). In the example of
For example, the power management integrated circuit 130 may generate the result hex value RHV (i.e., ‘1’) by converting the result decimal value (i.e., ‘1’) to a hex value. Since the result hex value RHV stored in the first authentication register FAR as a portion of the first internal register FDR corresponding to the ninth register address ‘08h’ and has a value of ‘1’, ‘1E’ may be stored in the first authentication register FAR (i.e., the upper 4 bits UDV) and the first internal register FDR (i.e., the lower 4 bits LDV) that correspond to the ninth register address (i.e., ‘08h’). The power management integrated circuit 130 may update only the updated driving set data UDSD among the driving set data DSD that is changed from the previous driving set data DSD to the current driving set data DSD in the first internal registers FDR. As illustrated in
Next, the timing controller 125 may transmit the driving set data DSD and the authentication data AD corresponding to the authentication hex value AHV to the power management integrated circuit 130 (S250). The power management integrated circuit 130 may compare the authentication hex value AHV received from the timing controller 125 with the result hex value RHV (S260) and determine an operating mode of the power management integrated circuit 130 according to a comparison result between the authentication hex value AHV and the result hex value RHV (S270).
If the authentication hex value AHV is consistent with the result hex value RHV, the power management integrated circuit 130 may operate in the normal mode (e.g., the high performance mode). On the other hand, if the authentication hex value AHV is inconsistent with the result hex value RHV or if the authentication hex value AHV is not received from the timing controller 125 within a preset time, the power management integrated circuit 130 may operate in the protection mode (e.g., the limited performance mode or the shut-down mode). In the example of
Subsequently, the power management integrated circuit 130 may change the operating conditions, for example, the voltage levels of the driving voltages for driving the display panel 110 and the display panel driving circuit 120 based on the operating mode that is determined according to the comparison result between the authentication hex value AHV and the result hex value RHV (S280). As described above, because the first internal registers FDR included in the power management integrated circuit 130 and the second internal registers SDR included in the timing controller 125 store the same driving hex values (i.e., the driving set data DSD), the authentication hex value AHV may be consistent with the result hex value RHV if the first authentication formula of the power management integrated circuit 130 for deriving the result hex value RHV is the same as the second authentication formula of the timing controller 125 for deriving the authentication hex value AHV. Thus, the power management integrated circuit 130 may operate in the normal mode if the authentication between the timing controller 125 and the power management integrated circuit 130 is determined to be successful as a result of the authentication hex value AHV being consistent with the result hex value RHV. On the other hand, if the first authentication formula of the power management integrated circuit 130 for deriving the result hex value RHV is different from the second authentication formula of the timing controller 125 for deriving the authentication hex value AHV (or when the timing controller 125 does not include the second authentication formula for deriving the authentication hex value AHV), the authentication hex value AHV generated in the timing controller 125 may be inconsistent with the result hex value RHV generated in the power management integrated circuit 130. Thus, the power management integrated circuit 130 may operate in the protection mode because the authentication between the timing controller 125 and the power management integrated circuit 130 is unsuccessful as a result of the authentication hex value AHV being inconsistent with the result hex value RHV=. Therefore, in the case that the timing controller 125 is not manufactured by the manufacturer of the power management integrated circuit 130, the timing controller 125 does not possess the first authentication formula of the power management integrated circuit 130 for deriving the result hex value RHV, and thus the authentication hex value AHV generated in the timing controller 125 may be inconsistent with the result hex value RHV generated in the power management integrated circuit 130. Thus, the power management integrated circuit 130 may determine not to operate at the high performance but to operate at the limited performance lower than the high performance or may be shut down. As a result, the power management integrated circuit 130 may not provide the high performance operation to the timing controller 125 that does not possess the first authentication formula of the power management integrated circuit 130 for deriving the result hex value RHV, and a proprietary technology (e.g., intellectual property) applied to the power management integrated circuit 130 may be prevented from being leaked to other manufacturers.
Referring to
The processor 1010 may perform various computing tasks. The processor 1010 may be a micro-processor, a central processing unit (CPU), an application processor (AP), or the like. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. Further, the processor 1010 may be coupled to an extended bus such as a peripheral component interconnection (PCI) bus. The memory device 1020 may store data of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, or the like and/or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, or the like. The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, or the like. The I/O device 1040 may include an input device such as a keyboard, a keypad, a mouse device, a touch-pad, a touch-screen, or the like and an output device such as a printer, a speaker, or the like. In some embodiments, the display device 1060 may be included as the I/O device 1040. The power supply 1050 may provide power for operating the electronic device 1000.
The display device 1060 may display an image corresponding to visual information of the electronic device 1000. The display device 1060 may be coupled to other components via buses and/or communication links. The display device 1060 may include a display panel (e.g., the display panel 110 of
The power management integrated circuit may store driving hex values corresponding to the driving set data in first internal registers FDR and determines operating conditions such as voltage levels of the driving voltages based on the driving hex values. Here, the power management integrated circuit may divide the driving hex values stored in the first internal registers FUR into upper decimal values UDV and lower decimal values LDV, derive a result decimal value by applying the upper decimal values and the lower decimal values to a first authentication formula, generate a result hex value (in some embodiment, the result hex value may be stored in the first authentication register included in the power management integrated circuit) based on the result decimal value, compare an authentication hex value corresponding to authentication data received from the timing controller with the result hex value, and selectively operate in a normal mode or in a protection mode according to a comparison result between the authentication hex value and the result hex value.
The power management integrated circuit may operate in the normal mode if the authentication hex value is consistent with the result hex value. On the other hand, the power management integrated circuit may operate in the protection mode if the authentication hex value is inconsistent with the result hex value or the power management integrated circuit does not receive the authentication hex value from the timing controller within a preset time. In addition, the timing controller may determine the driving set data based on input image data in each image frame, store the driving hex values corresponding to the driving set data in the second internal registers SDR, and transmit the driving set data to the power management integrated circuit. The timing controller may divide the driving hex values stored in the second internal registers SDR into the upper decimal values and the lower decimal values, derive an authentication decimal value by applying the upper decimal values and the lower decimal values to a second authentication formula, generate the authentication hex value based on the authentication decimal value (in some embodiments, the authentication hex value may be stored in the second authentication register included in the timing controller), and transmit the authentication data corresponding to the authentication hex value to the power management integrated circuit. The display device 1060 may selectively operate the power management integrated circuit in the normal mode (e.g., a high performance mode) or in the protection mode (e.g., a limited performance mode or a shut-down mode) according to the authentication between the timing controller and the power management integrated circuit via a specific communication (e.g., an PC communication). As a result, the display device 1060 may prevent a technology applied to a specific power management integrated circuit by a manufacturer of the specific power management integrated circuit from being leaked to other manufacturers. Since these are described above, duplicated description related thereto is not repeated.
The present inventive concept may be applied to a display device and an electronic device including the display device. For example, the present inventive concept may be applied to a smart phone, a cellular phone, a video phone, a smart pad, a smart watch, a tablet PC, a car navigation system, a television, a computer monitor, a laptop, a head mounted display (HMD) device, an MP3 player, or the like.
The foregoing is illustrative of the exemplary embodiments of the present disclosure and is not to be construed as limiting thereof. Although some embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the disclosed embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, such modifications are intended to be included within the scope of the present inventive concept. Therefore, it is to be understood that the foregoing is illustrative of various embodiments of the present disclosure and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the present disclosure including the appended claims.
Number | Date | Country | Kind |
---|---|---|---|
10-2020-0026014 | Mar 2020 | KR | national |
This application is a continuation application of U.S. patent application Ser. No. 17/154,943 filed on Jan. 21, 2021, which claims priority under 35 USC § 119 to Korean Patent Application No. 10-2020-0026014 filed on Mar. 2, 2020 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated by reference in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
6067645 | Yamamoto et al. | May 2000 | A |
20140168047 | Kim et al. | Jun 2014 | A1 |
20160063918 | Choi | Mar 2016 | A1 |
20180059470 | Nam et al. | Mar 2018 | A1 |
20180158397 | Nam et al. | Jun 2018 | A1 |
20180196301 | Choi et al. | Jul 2018 | A1 |
20220197467 | Kim | Jun 2022 | A1 |
Number | Date | Country |
---|---|---|
10-0193737 | Jun 1999 | KR |
Entry |
---|
Ronald Rivest, Deacon Vorbis, “MD5 message-digest algorithm”, Journals or serial, Feb. 29, 2020, 12 pages, MD5—Wikipedia, U.S., https://en.wikipedia.org/w/index.php?title=MD5&oldid=943217009. |
Number | Date | Country | |
---|---|---|---|
20220165196 A1 | May 2022 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 17154943 | Jan 2021 | US |
Child | 17669862 | US |