Patent Grant
8552953
The present invention relates to a display device and more particularly relates to a liquid crystal display device.
A liquid crystal display (LCD) is a flat-panel display that has a number of advantageous features including high resolution, drastically reduced thickness and weight, and low power dissipation. The LCD market has been rapidly expanding recently as a result of tremendous improvements in its display performance, significant increases in its productivity, and a noticeable rise in its cost effectiveness over competing technologies.
Among other things, an inplane switching (IPS) mode liquid crystal display device (see Patent Document No. 1) and a multi-domain vertical aligned (MVA) mode liquid crystal display device (see Patent Document No. 2) are often used in liquid crystal TV monitors as a wide viewing angle mode liquid crystal display device that can avoid problems such as a significant decrease in contrast ratio or the inversion of display grayscales, which will happen when the image on the screen is viewed obliquely.
Although the display qualities of LCDs have been further improved nowadays, a viewing angle characteristic problem in a different phase has arisen just recently.
Specifically, the γ characteristic of LCDs would vary with the viewing angle. That is to say, the γ characteristic when an image on the screen is viewed straight is different from the characteristic when it is viewed obliquely. As used herein, the “γ characteristic” refers to the grayscale dependence of display luminance. That is why if the γ characteristic when the image is viewed straight is different from the characteristic when the same image is viewed obliquely, then it means that the grayscale display state changes according to the viewing direction. This is a serious problem particularly when a still picture such as a photo is presented or when a TV program is displayed.
The viewing angle dependence of the γ characteristic is more significant in the MVA mode rather than in the IPS mode. According to the IPS mode, however, it is more difficult to make panels that realize a high contrast ratio when the image on the screen is viewed straight with good productivity rather than in the MVA mode. Taking these circumstances into consideration, it is particularly necessary to reduce the viewing angle dependence of the γ characteristic of MVA mode liquid crystal display devices, among other things.
To overcome such a problem, the applicant of the present application disclosed a liquid crystal display device that can reduce the viewing angle dependence of the γ characteristic (or an excessively high contrast ratio of white portions of an image, among other things) by dividing a single pixel into a number of subpixels, and a method for driving such a device in Patent Document No. 3. Such a display or drive mode will sometimes be referred to herein as “area-grayscale display”, “area-grayscale drive”, “multi-pixel display” or “multi-pixel drive”.
Patent Document No. 3 discloses a liquid crystal display device in which storage capacitors Cs are provided for respective subpixels SP of a single pixel P. In the storage capacitors, the storage capacitor counter electrodes (which are connected to CS bus lines) are electrically independent of each other between the subpixels. And by varying the voltages applied to the storage capacitor counter electrodes (which will be referred to herein as “storage capacitor counter voltages”), mutually different effective voltages can be applied to the respective liquid crystal layers of multiple subpixels by utilizing a capacitance division technique.
Hereinafter, the pixel division structure of the liquid crystal display device 200 disclosed in Patent Document No. 3 will be described with reference to
The pixel 10 is split into a subpixel 10a and another subpixel 10b. To the subpixels 10a and 10b, connected are their associated TFTs 16a and 16b and their associated storage capacitors (CS) 22a and 22b, respectively. The gate electrodes of the TFTs 16a and 16b are both connected to the same scan line 12. And the source electrodes of the TFTs 16a and 16b are connected to the same signal line 14. The storage capacitors 22a and 22b are connected to their associated storage capacitor lines (CS bus lines) 24a and 24b, respectively. The storage capacitor 22a includes a storage capacitor electrode that is electrically connected to the subpixel electrode 18a, a storage capacitor counter electrode that is electrically connected to the storage capacitor line 24a, and an insulating layer (not shown) arranged between the electrodes. The storage capacitor 22b includes a storage capacitor electrode that is electrically connected to the subpixel electrode 18b, a storage capacitor counter electrode that is electrically connected to the storage capacitor line 24b, and an insulating layer (not shown) arranged between the electrodes. The respective storage capacitor counter electrodes of the storage capacitors 22a and 22b are independent of each other and have such a structure as receiving mutually different storage capacitor counter voltages from the storage capacitor lines 24a and 24b, respectively.
Hereinafter, it will be described with reference to the accompanying drawings on what principle mutually different effective voltages can be applied to the respective liquid crystal layers of the two subpixels 10a and 10b of the liquid crystal display device 200.
The liquid crystal capacitors Clca and Clcb are supposed to have the same electrostatic capacitance CLC (V). The value of CLC (V) depends on the effective voltages (V) applied to the liquid crystal layers of the respective subpixels 10a and 10b. Also, the storage capacitors 22a and 22b that are connected independently of each other to the liquid crystal capacitors of the respective subpixels 10a and 10b will be identified herein by Ccsa and Ccsb, respectively, which are supposed to have the same electrostatic capacitance CCS.
In the subpixel 10a, one electrode of the liquid crystal capacitor Clca and one electrode of the storage capacitor Ccsa are connected to the drain electrode of the TFT 16a, which is provided to drive the subpixel 10a. The other electrode of the liquid crystal capacitor Clca is connected to the counter electrode. And the other electrode of the storage capacitor Ccsa is connected to the storage capacitor line 24a. In the subpixel 10b, one electrode of the liquid crystal capacitor Clcb and one electrode of the storage capacitor Ccsb are connected to the drain electrode of the TFT 16b, which is provided to drive the subpixel 10b. The other electrode of the liquid crystal capacitor Clcb is connected to the counter electrode. And the other electrode of the storage capacitor Ccsb is connected to the storage capacitor line 24b. The gate electrodes of the TFTs 16a and 16b are both connected to the scan line 12 and the source electrodes thereof are both connected to the signal line 14.
Portions (a) through (f) of
Specifically, portion (a) of
Hereinafter, it will be described with reference to portions (a) through (f) of
First, at a time T1, the voltage Vg rises from VgL to VgH to turn the TFTs 16a and 16b ON simultaneously. As a result, the voltage Vs on the signal line 14 is transmitted to the subpixel electrodes 18a and 18b of the subpixels 10a and 10b to charge the subpixels 10a and 10b with the voltage Vs. In the same way, the storage capacitors Csa and Csb of the respective subpixels are also charged with the voltage on the signal line.
Next, at a time T2, the voltage Vg on the scan line 12 falls from VgH to VgL to turn the TFTs 16a and 16b OFF simultaneously and electrically isolate the subpixels 10a and 10b and the storage capacitors Csa and Csb from the signal line 14. It should be noted that immediately after that, due to the feedthrough phenomenon caused by a parasitic capacitance of the TFTs 16a and 16b, for example, the voltages Vlca and Vlcb applied to the respective subpixel electrodes decrease by approximately the same voltage Vd to:
Vlca=Vs−Vd
Vlcb=Vs−Vd
respectively. Also, in this case, the voltages Vcsa and Vcsb on the storage capacitor lines are:
Vcsa=Vcom−Vad
Vcsb=Vcom+Vad
respectively.
Next, at a time T3, the voltage Vcsa on the storage capacitor line 24a connected to the storage capacitor Csa rises from Vcom−Vad to Vcom+Vad and the voltage Vcsb on the storage capacitor line 24b connected to the storage capacitor Csb falls from Vcom+Vad to Vcom−Vad. That is to say, these voltages Vcsa and Vcsb both change twice as much as Vad. As the voltages on the storage capacitor lines 24a and 24b change in this manner, the voltages Vlca and Vlcb applied to the respective subpixel electrodes change into:
Vlca=Vs−Vd+2×Kc×Vad
Vlcb=Vs−Vd−2×Kc×Vad
respectively, where Kc=CCS/(CLC(V)+CCS) and × indicates multiplication.
Next, at a time T4, Vcsa falls from Vcom+Vad to Vcom−Vad and Vcsb rises from Vcom−Vad to Vcom+Vad. That is to say, these voltages Vcsa and Vcsb both change twice as much as Vad again. In this case, Vlca and Vlcb also change from
Vlca=Vs−Vd+2×Kc×Vad
Vlcb=Vs−Vd−2×Kc×Vad
into
Vlca=Vs−Vd
Vlcb=Vs−Vd
respectively.
Next, at a time T5, Vcsa rises from Vcom−Vad to Vcom+Vad and Vcsb falls from Vcom+Vad to Vcom−Vad. That is to say, these voltages Vcsa and Vcsb both change twice as much as Vad again. In this case, Vlca and Vlcb also change from
Vlca=Vs−Vd
Vlcb=Vs−Vd
into
Vlca=Vs−Vd+2×Kc×Vad
Vlcb=Vs−Vd−2×Kc×Vad
respectively.
After that, every time a period of time that is an integral number of times as long as one horizontal scanning period (or one horizontal write period) 1H has passed, the voltages Vcsa, Vcsb, Vlca and Vlcb alternate their levels at the times T4 and T5. Consequently, the effective values of the voltages Vlca and Vlcb applied to the subpixel electrodes become:
Vlca=Vs−Vd+Kc×Vad
Vlcb=Vs−Vd−Kc×Vad
respectively.
Therefore, the effective voltages V1 and V2 applied to the liquid crystal layers 13a and 13b of the subpixels 10a and 10b become:
V1=Vlca−Vcom
V2=Vlcb−Vcom
That is to say,
V1=Vs−Vd+Kc×Vad−Vcom
V2=Vs−Vd−Kc×Vad−Vcom
respectively.
As a result, the difference V12 (=V1−V2) between the effective voltages applied to the liquid crystal layers 13a and 13b of the subpixels 10a and 10b becomes
V12=2×Kc ×Vad (where Kc=CCS/(CLC(V)+CCS)). Thus, mutually different voltages can be applied to the liquid crystal layers 13a and 13b.
V12 in the liquid crystal display device 200. Since
V12 increases as the V1 value decreases in this manner, the excessively high contrast ratio can be reduced, among other things.
However, if the multi-pixel structure disclosed in Patent Document No. 3 were applied to either a high-resolution LCD TV monitor or a big LCD TV monitor, the oscillating voltage would have a shorter period of oscillation as the resolution or the size of the display panel increases. Thus, it would be increasingly difficult (and expensive) to make a circuit for generating the oscillating voltage, the power dissipation would increase too much, or the influence of waveform blunting due to the electrical load impedance of the CS bus lines would be more and more significant. However, if a plurality of electrically independent CS trunks are arranged and connected to the multiple CS bus lines as disclosed in Patent Document No. 4, one period of oscillation of the oscillating voltage applied to the storage capacitor counter electrodes by way of the CS bus line can be extended.
If the arrangement disclosed in Patent Document No. 4 is adopted, however, the waveform (phase) of the CS voltage (oscillating voltage) should be controlled to prevent the display quality from decreasing (e.g., to prevent the presented image from having noticeable bright and dark stripes) due to a disagreement between one period of the oscillating voltage (CS voltage) applied to the CS bus lines and one vertical scanning period. For that purpose, Patent Document No. 4 discloses the following method, for example.
Specifically, in one vertical scanning period V-Total of an input video signal, the CS voltage should have a waveform that oscillates with a constant period PA (which will be referred to herein as a “first type of waveform”) in an effective display period V-Disp (which will also be referred to herein as an “effective scanning period”) in which a display operation needs to be performed. But in a vertical blanking interval V-Blank in which no display operation is performed, the CS voltage should have its waveform defined such that the effective value of the CS voltage becomes a predetermined constant value every predetermined number of continuous vertical scanning periods. Such a waveform will be referred to herein as a “second type of waveform”. And the predetermined number is at most equal to 20 but is typically four or less. That is to say, by shaping the waveform of the CS voltage in a vertical blanking interval in which there is no need to write data on any pixel, the effective value of the CS voltage is kept constant through the predetermined number of continuous vertical scanning periods with the waveform of the CS voltage kept constant in each effective display period. It should be noted that not every effective display period is the period in which the CS voltage has the first type of waveform and that not every vertical blanking interval is the period in which the CS voltage has the second type of waveform, either.
The CS voltage waveform controlling method disclosed in Patent Document No. 4 supposes that there is no need to write data on any pixel within a vertical blanking interval as described above. That is why if a driving method that is designed to write image data in an effective display period and black data in a vertical blanking interval (such a method is called either a “black insert drive” or a “pseudo-impulse drive”) is combined with such a method in order to improve the moving picture display performance of the liquid crystal display device, for example, then not every pixel can have the same phase relation between the timing to write the black data in the vertical blanking interval and the oscillating waveform of the CS voltage. As a result, the image may have a noticeable luminance difference (i.e., a significant difference between its bright and dark portions). Such a problem found by the present inventors will be described in detail later.
In order to overcome the problems described above, the present invention has an object of, first and foremost, making the area grayscale display technique disclosed in Patent Document No. 3 applicable to a driving method that is designed to write data in a vertical blanking interval. Another object of the present invention is to provide a liquid crystal display device and its driving method that can always use the area grayscale display technique of Patent Document No. 3, no matter how long one vertical scanning period or one vertical blanking interval is and what type of driving method is adopted (i.e., whether data needs to be written in a vertical blanking interval or not).
A display device according to the present invention includes a display panel with multiple pixels and a display controller that receives an input video signal and a sync signal and gets an image presented on the display panel. If one horizontal scanning period and one vertical scanning period of the input video signal are represented by 1H and V-Total, respectively, the display controller is able to form one vertical scanning period V-Total of a first period in which one horizontal scanning period of the display panel is 1Ho, which is as long as 1H, and a second period (which will also be referred to herein as an “adjustment period”) in which one horizontal scanning period of the display panel is 1Hn, which is not as long as 1H.
Another display device according to the present invention includes a display panel with multiple pixels and a display controller that receives an input video signal and a sync signal and gets an image presented on the display panel. If one standard horizontal scanning period and one vertical scanning period to write image data on the display panel are represented by 1H and V-Total, respectively, the display controller is able to form one vertical scanning period V-Total of a first period in which one horizontal scanning period of the display panel is 1Ho, which is as long as 1H, and a second period in which one horizontal scanning period of the display panel is 1Hn, which is not as long as 1H.
In one preferred embodiment, V-total is represented as the sum of an effective display period V-Disp and a vertical blanking interval V-Blank and the second period is included in the vertical blanking interval V-Blank.
In another preferred embodiment, the second period is made up of a number of continuous horizontal scanning periods.
In still another preferred embodiment, the second period is an integral number of times as long as 1Hn.
In yet another preferred embodiment, the pixels are arranged in columns and rows so as to form a matrix pattern. Each pixel includes a liquid crystal layer and a plurality of electrodes for applying a voltage to the liquid crystal layer. Each pixel includes: a first subpixel and a second subpixel, having liquid crystal layers to which mutually different voltages are applicable; and two switching elements that are provided for the first and second subpixels, respectively. Each of the first and second subpixels includes a liquid crystal capacitor formed by a counter electrode and a subpixel electrode that faces the counter electrode through the liquid crystal layer, and a storage capacitor formed by a storage capacitor electrode that is electrically connected to the subpixel electrode, an insulating layer, and a storage capacitor counter electrode that is opposed to the storage capacitor electrode with the insulating layer interposed between them. The counter electrode is a single electrode provided in common for the first and second subpixels, while the storage capacitor counter electrodes of the first and second subpixels are electrically independent of each other. A storage capacitor counter voltage applied to each storage capacitor counter electrode by way of an associated storage capacitor line oscillates in a cycle time that is an integral number of times as long as Ho during the first period included in V-Total but oscillates in a cycle time that is an integral number of times as long as Hn during the second period.
In this particular preferred embodiment, if one vertical scanning period V-Total is represented as the sum of an effective display period V-Disp and a vertical blanking interval V-Blank and if V-Total=m×H and V-Disp=m0×H, then V-Disp=m0×Ho, V-Blank=m1×Ho+m2×Hn and m2×Hn is an integral number of times as long as one cycle time of the storage capacitor counter voltage during the second period.
In a specific preferred embodiment, (m0+m1)×Ho is either an integral or a half-integral number of times as long as one cycle time of the storage capacitor counter voltage during the first period.
In yet another preferred embodiment, the display device further includes a plurality of storage capacitor trunks, which are electrically independent of each other and each of which is electrically connected to an associated one of the storage capacitor counter electrodes of the first and second subpixels of the pixels by way of its associated storage capacitor line. The storage capacitor trunks include an even number L of electrically independent storage capacitor trunks. The storage capacitor counter voltage supplied through each of the storage capacitor trunks to its associated storage capacitor line oscillates in a cycle time that is either K×L or 2×K×L times as long as Ho during the first period, where K is a positive integer and either K×L or 2×K×L is equal to or greater than four, and oscillates in a cycle time that is either K×L or 2×K×L times as long as Hn during the second period.
If one horizontal scanning period and one vertical scanning period of an input video signal are represented by 1H and V-Total, respectively, the display device of the present invention can form one vertical scanning period V-Total of a first period in which one horizontal scanning period of the display panel is 1Ho, which is as long as 1H, and a second period in which one horizontal scanning period of the display panel is 1Hn, which is not as long as 1H. That is why according to the present invention, the area grayscale display technique disclosed in Patent Document No. 3 can be applied to such a driving method that is designed to write data even in a vertical blanking interval. The present invention also provides a liquid crystal display device and its driving method that can always use the area grayscale display technique of Patent Document No. 3, no matter how long one vertical scanning period or one vertical blanking interval is and what type of driving method is adopted (i.e., whether data needs to be written in a vertical blanking interval or not). Optionally, 1H may be a standard horizontal scanning period for writing image data on the display panel, instead of one horizontal scanning period of the input video signal. The present invention is applicable to not only a liquid crystal display device but also any other types of display device to which a line sequential driving method is applied just like a liquid crystal display device.
a) and 7(b) show the averages of the voltages applied to respective subpixels during the video write period and the black write period in the liquid crystal display device shown in
Hereinafter, preferred embodiments of a liquid crystal display device and its driving method according to the present invention will be described with reference to the accompanying drawings. It should be noted that in a liquid crystal display device according to a preferred embodiment of the present invention, the structure of pixels is similar to the one disclosed in Patent Document No. 3, but the connection pattern of storage capacitor lines (which are typically CS bus lines) may be any of the ones disclosed in Patent Document No. 4. The entire disclosure of Patent Documents Nos. 3 and 4 are hereby incorporated by reference.
Hereinafter, the problems with the liquid crystal display device and its driving method as disclosed in Patent Document No. 4 will be described with reference to
Such a problem is caused by a difference in phase between the timing to write data and the oscillating waveform of the CS voltage. Thus, first of all, it will be described how the oscillating waveform of a CS voltage changes according to the length of one vertical scanning period.
As used herein, one “vertical scanning period V-Total” is defined to be an interval between a point in time when one scan line is selected to write a display signal voltage and a point in time when the same scan line is selected again to write the next display signal voltage. Also, each of one frame period of a non-interlaced drive input video signal and one field period of an interlaced drive input video signal will be referred to herein as “one vertical scanning period V-Total of the input video signal”. Normally, one vertical scanning period of a liquid crystal display device corresponds to one vertical scanning period of the input video signal. In the example to be described below, one vertical scanning period is supposed to be one frame period and one vertical scanning period of the liquid crystal display panel is supposed to correspond to that of the input video signal for the sake of simplicity. However, the present invention is in no way limited to that specific preferred embodiment. Alternatively, the present invention is also applicable to a so-called “2×drive” with a vertical scanning frequency of 120 Hz in which two vertical scanning periods of the liquid crystal display panel (that lasts 2× 1/120 sec, for example) are allocated to one vertical scanning period of the input video signal (that lasts 1/60 sec, for example).
One vertical scanning period V-Total of an input video signal is made up of an effective display period V-Disp in which video is presented and a vertical blanking interval V-Blank in which no video is presented. The effective display period for presenting video is determined by the display area (or the number of rows of effective pixels) of an LCD panel. On the other hand, the vertical blanking interval is an interval for signal processing, and therefore, is not always constant but changes from one manufacturer of TV receivers to another. For instance, if the display area has 1,080 rows of pixels, the effective display period is fixed at 1,080× one horizontal scanning period (H) (which will be identified herein by “1,080H”). However, in one case, one vertical blanking interval may be 30H and one vertical scanning period V-Total may be 1,110H. In another case, one vertical blanking interval may be 36H and one vertical scanning period V-Total may be 1,116H. Furthermore, the length of one vertical blanking interval may even alternate between an odd number and an even number every vertical scanning period.
Hereinafter, a situation where one vertical scanning period V-Total is 1,110H, one effective display period V-Disp is 1,080H and one vertical blanking interval V-Blank is 30H will be described with reference to
As shown in
Suppose in the Type II liquid crystal display panel with ten types (ten phases) of CS voltages (or CS trunk lines) as disclosed in Patent Document No. 4, the CS voltage oscillates with a period PA of 20H. In that case, if V-Total is 1,110H, then the V-Total value becomes a half-integral number of times (i.e., 55.5 times) as long as 20H. That is why in a situation where a frame inversion drive, in which the write polarity inverts every frame, is carried out, then the CS voltage will have a continuous rectangular wave with a period of 20H over multiple frames as shown at the top of
The voltage waveforms identified by Line_1, Line_a, Line_b, Line_c, Line_d, and Line_e in
Look at the ath row. First, in the frame in which a positive voltage is written, an image data write pulse is applied (i.e., the gate signal is raised to High level), an image data signal is written on the subpixel through a source bus line, and the voltage applied to the subpixel rises. Thereafter, when the CS voltage changes for the first time (i.e., rises in this case) after the image data write pulse has been applied, the voltage applied to subpixel rises and then oscillates synchronously with the CS voltage. This subpixel is a bright subpixel and has an average voltage (i.e., a difference from Vcom) of V1_a in the video write period of 825H. A black write pulse is applied when 825H has passed since the image data write pulse was applied. As a result, a black voltage is written on the subpixel and the voltage applied to the subpixel decreases. In this case, if the subpixel has an ideal chargeability, for example, the voltage applied to the subpixel decreases to a black voltage Vcom. Thereafter, when the CS voltage changes for the first time (i.e., falls in this case) after the black write pulse has been applied, the voltage applied to the subpixel falls and then oscillates synchronously with the CS voltage. In the example illustrated in
Next, in the frame in which a negative voltage is written, an image data write pulse is applied while the voltage applied to the subpixel has a black voltage level, an image data signal is written on the subpixel through a source bus line, and the voltage applied to the subpixel falls. Thereafter, when the CS voltage changes for the first time (i.e., falls in this case) after the image data write pulse has been applied, the voltage applied to subpixel falls and then oscillates synchronously with the CS voltage. This subpixel has an average voltage (i.e., a difference from Vcom) of V2_a in the video write period of 825H.
As can be seen from
A waveform representing the response of liquid crystal molecules in each subpixel in such a situation is schematically illustrated in
As described above, if one vertical scanning period V-Total has a length of 1,110H and if the CS voltage oscillates with a period PA of 20H, then it is possible to satisfy the requirement that V-Total be a half-integral number of times as long as one period PA of oscillation of the CS voltage. That is why no matter whether data should be written in the effective display period or in the vertical blanking interval (i.e., in the video write period or in the black write period in this case), every pixel has the same phase relation between the timing to write the data and the waveform of its associated CS voltage. As a result, a display operation can be performed with a uniform luminance over the entire screen.
Next, a situation where one vertical scanning period V-Total has a length of 1,116H, one effective display period V-Disp has a length of 1,080H and one vertical blanking interval V-Blank has a length of 36H will be described with reference to
As shown in
By performing the equalization processing with the second type of waveform provided in this manner, if only the video write operation needs to be performed during each vertical scanning period, the write operation can get done on every pixel within the effective display period and the continuity of the CS voltage waveform can be maintained over two consecutive frames as can be seen from
On the other hand, if the video write operation and the black write operation need to be both performed during each vertical scanning period, part of the black write operation cannot be finished within the effective display period but should be carried out during the vertical blanking interval as can be seen from
Just like
Although it will not be described in detail, if the video write period has a length of 825H and the black insert period has a length of 291H, then the black voltage is also written even during the equalization processing periods (including vertical blanking intervals) as indicated by the crosses × on the uppermost CS voltage waveform shown in
That is why as can be seen from
Next, a liquid crystal display device and its driving method according to this preferred embodiment will be described with reference to
As already described with reference to
If one horizontal scanning period and one vertical scanning period of the input video signal are represented by 1H and V-Total, respectively, one vertical scanning period V-Total may consist of a first period in which one horizontal scanning period of the liquid crystal display panel is 1Ho, which is as long as 1H, and a second period (adjustment period) in which one horizontal scanning period of the liquid crystal display panel is 1Hn, which is not as long as 1H, in the liquid crystal display device of this preferred embodiment of the present invention. That is to say, by partially using 1Hn, which is not as long as one horizontal scanning period (1H) of the input video signal, as one horizontal scanning period of the display panel, the number of horizontal scanning periods included in one vertical scanning period can be adjusted. That is why even if V-Total of the input video signal has deviated from its ideal length, the number of horizontal scanning periods included in one vertical scanning period of the display panel can still be the ideal value by determining Hn appropriately. It should be noted that one vertical scanning period of the display panel is as long as one vertical scanning period of the input video signal.
The liquid crystal display device of this preferred embodiment includes a display panel with multiple pixels and a display controller that receives an input video signal and a sync signal and gets an image presented on the display panel. The input video signal and the sync signal may be supplied as a composite video signal.
The display controller controls the length of one horizontal scanning period by the number of gate clock pulses GCK applied to the display panel. That is why a control operation needs to be carried out such that the number of gate clock pulses GCK per frame becomes equal to an ideal value such as 1,110. According to this method, V-Total can always have an ideal length without depending on V-Total of the input video signal.
However, there is no need to change the lengths of one horizontal scanning period over the entire V-Total period. But only in a fraction (i.e., the second period) of V-Total, one horizontal scanning period preferably has a length of 1Hn that is not as long as 1H. In that case, the CS voltage will have a waveform that oscillates with two different periods that are an integral number of times as long as Ho and Hn in the first and second periods, respectively.
Also, the second period is preferably a single continuous period. In other words, the second period preferably consists of a number of consecutive horizontal scanning periods. Furthermore, the second period is preferably an integral number of times as long as 1Hn. By adjusting the length of one horizontal scanning period in this manner, one period of oscillation of the CS voltage in the second period can also be an integral number of times as long as 1Hn.
In cases of the frame inversion drive, one period of oscillation of the CS voltage in the second period is preferably an integral number of times as long as one horizontal scanning period. For instance, as will be described in the following example, each of CS voltages with ten phases oscillates with a period of 20 horizontal scanning periods and those CS voltages have ten different waveforms, which shift from each other by one-tenth of one oscillation period (i.e., by two horizontal scanning periods). Thus, if the second period consists of 20 consecutive horizontal scanning periods (which is as long as one period of oscillation of the CS voltage), then the CS voltage can have the same average in the first and second periods.
Furthermore, the second period is preferably provided within the vertical blanking interval V-Blank in order to avoid making a read error of the display data. A normal liquid crystal display device receives data corresponding to one row of pixels every 1H and writes data corresponding to one row of pixels every 1H, too. That is why if the rate of the input signal were different from the rate of the write signal, then the relation described above could not be satisfied anymore. And to avoid such an error, a memory that can store data for one frame would be needed, thus increasing the cost significantly. Meanwhile, the vertical blanking interval V-Blank is an interval in which no effective input signals are received. For that reason, even if the (real time) length of one horizontal scanning period changed in that period, the relation described above should not be affected.
A liquid crystal display device to be described as a preferred embodiment of the present invention with reference to
In this preferred embodiment of the present invention, the length of one horizontal scanning period is adjusted, and therefore, there are multiple horizontal scanning periods with mutually different real time lengths. Thus, those horizontal scanning periods will be distinguished in the following manner.
First of all, H will also represent one horizontal scanning period of the input video signal as in the foregoing description. That is why as for the input video signal, V-Total=m×H, V-Disp=m0×H, and V-Blank=(m−m0)×H (where m and m0 are positive integers) need to be satisfied. In this example, m=1,116, m0=1,080 and (m−m0)=36.
Meanwhile, as for the liquid crystal display panel, m1, m2 and Hn should be determined such that V-Disp=m0×Ho, V-Blank=m1×Ho+m2×Hn and the ideal value is m0+m1+m2. In this example, the ideal value is 1,110. Ho and H actually have the same real time length but are both used here in order to represent one horizontal scanning period of the liquid crystal display panel definitely.
Just like
As indicated by 1110H′ in
In the example illustrated in
As described above, by providing the second period, of which one horizontal scanning period Hn is different from H of the input video signal, as an adjustment period, every row of pixels can have the same phase relation between the timing to write the black voltage and the oscillation waveform of the CS voltage, although the black voltage is written during the vertical blanking interval as indicated by the crosses × on the CS voltage waveform at the top of
As a result, as can be seen from
A waveform representing the response of liquid crystal molecules in each subpixel in such a situation is schematically illustrated in
Hereinafter, it will be described how to determine m1, m2 and Hn. Suppose the CS voltage has one period of oscillation of PA and the number of horizontal scanning periods included in PA is Tsc during the first period.
First, m1 is calculated by the following equation:
m1=Tcs×(n1+1/2)−m0
where 0≦m1≦m0 and n1 is a positive integer. But the best m1 value satisfies 0≦m1≦Tcs.
Next, m2 is calculated by the following equation:
m2=Tcs×n2
where n2 is a positive integer. But the best m2 value satisfies:
(Tcs/2)×n2+(Tcs/2)×(n2−1)≦(m−m0)−m1≦(Tcs/2)×n2+(Tcs/2)×(n2+1)
And then m0+m1+m2 is calculated.
Hn is calculated by the following equation:
[m×Ho−(m0+m1)×Ho]÷m2
Hereinafter, the foregoing example will be described with specific figures. First of all, m=1,116, m0=1,080 and Tsc=20 are determined by the input signal.
Next, m1 is calculated by the following equation:
m1=20×(n1+1/2)−1080
As 0≦m1, 54≦n1 needs to be satisfied. And
If n1=54, then 20×54.5−1080=10, but
if n1=55, then 20×55.5−1080=30.
Since the best m value satisfies 0≦m<20, m1=10 (if n1=54).
Subsequently, m2 is calculated by the following equation:
m2=20×n2
As the best n2 value needs to satisfy
(20/2)×n2+(20/2)×(n2−1)≦36−10≦(20/2)×n2+(20/2)×(n2+1)
If n2=0, then −10≦26≦10, which is NG,
If n2=1, then 10≦26≦30, which is OK, and
If n2=2, then 30≦26≦50, which is NG,
Therefore, the best n2 value becomes 1 and m2=20.
Consequently, m0+m1+m2=1080+10+20=1110.
And Hn is calculated by
(1116×Ho−(1080+10)×Ho)÷20=1.3Ho
As shown in
In the preferred embodiments described above, the number of electrically independent storage capacitor trunks is supposed to be smaller than that of storage capacitor lines (i.e., CS bus lines), which corresponds to Type I or Type II arrangement disclosed in Patent Document No. 4. Naturally, however, an arrangement in which CS voltages are supplied to the respective storage capacitor lines independent of each other may also be adopted. In that case, a CS voltage should change its levels at least once after the gate voltage has gone low during one vertical scanning period. Also, in a liquid crystal display device that includes storage capacitor lines that are twice as many as the gate bus lines and has an arrangement for supplying CS voltages to those storage capacitor lines independent of each other, if the CS voltage should change its levels only once after the gate voltage has gone low, then either the interval between the fall of the gate voltage to low level and the first change of the CS voltage levels or the interval between the change of the CS voltage levels and the rise of the gate voltage to high level next time during one vertical scanning period is preferably defined to be the same on every display line.
Conversely, if an arrangement in which a single storage capacitor. trunk is provided for multiple storage capacitor lines is adopted, then the CS voltages on those storage capacitor lines that are all connected to a single storage capacitor trunk can have exactly the same amplitude of oscillation. Naturally, the circuit configuration can be simplified compared to a situation where a lot of voltages are provided independent of each other.
Hereinafter, a black insert driving method, to which a liquid crystal display device as a preferred embodiment of the present invention is applicable effectively, will be described.
The display section 50 has any of the multi-pixel structures of the liquid crystal display devices disclosed in Patent Documents Nos. 3 and 4. To achieve a high pixel aperture ratio, among other things, the Type II arrangement disclosed in Patent Document No. 4 is preferably adopted (see
The display controller 60 receives a digital video signal Dv representing an image to present, a horizontal sync signal HSY and a vertical sync signal VSY associated with the digital video signal Dv, and a control signal Dc to control the display operation from external signal sources. Then, based on these signals Dv, HSY, VSY and Dc, the display controller 60 outputs a data start pulse signal SSP, a data clock signal SCK, a short-circuit control signal Csh, and a digital image signal DA representing the image to present (corresponding to the digital video signal Dv) to the source driver 70 as signals for getting the image represented by the digital video signal Dv presented on the display section 50. In this case, the short-circuit control signal Csh is a signal unique to the black insert drive done by the liquid crystal display device of this preferred embodiment as will be described later, and is a signal for controlling the timing to short-circuit two adjacent source bus lines (e.g., source bus lines SL1 and SL2 or SL2 and SL3), to which signal voltages with mutually different polarities are supplied in the one dot inversion drive.
The display controller 60 also outputs the gate start pulse signal GSP, the gate clock signal GCK and the gate driver output control signal GOE to the gate driver 80 and further outputs the gate start pulse signal GSP and the gate clock signal GCK to the CS controller 90. In this case, the display controller 60 in the liquid crystal display device 100 of this preferred embodiment determines the length of one horizontal scanning period Hn for adjustment based on V-Total (corresponding to one period of VSY) and one horizontal scanning period H (corresponding to one period of HSY) of the digital video signal Dv that has been input to the display controller 60, generates a GCK signal to control the duration and timing of Ho and Hn, and then outputs it to the gate driver 80 and the CS voltage controller 90. As a result of this operation, the device is controlled such that the oscillation waveforms of the CS voltage are changed every predetermined count of GCK irrespective of V-Total of the digital video signal as an input video signal, thus realizing a high display quality with no brightness unevenness just as already described. Optionally, if the adjustment period to change the lengths of one period of GCK is defined within the vertical blanking interval, then SSP and SCK for controlling the input and output of data to/from the source driver do not have to be changed but values defined by the input signal could be used. This is because the vertical blanking interval includes no effective display data.
Based on a digital image signal DA and the start pulse signal SSP and clock signal SCK for the source driver, the source driver 70 sequentially generates data signal voltages S(1), S(2), . . . and S(m) every horizontal scanning period as analog voltages representing pixel values on respective horizontal scan lines of the image represented by the digital image signal DA, and then supplies those data signal voltages S(1), S(2), . . . and S(m) onto the respective source bus lines SL1, SL2, . . . and SLm. The liquid crystal display device 100 of this preferred embodiment performs a drive operation so as to invert the polarity of the voltage applied to the liquid crystal layer (with respect to the counter voltage) not only every vertical scanning period (which corresponds with one frame in this case) but also every gate bus line and every source bus line. That is to say, the liquid crystal display device performs a so-called “one dot inversion drive”.
The source driver 70 performs the black insert drive operation by providing a period in which a source bus line is electrically short-circuited with one of its adjacent source bus lines with the opposite polarity (i.e., those two source bus lines are made to share the same charge) when the polarity of a data signal voltage is inverted. Such a black insert driving method will be referred to herein as a “charge sharing impulse (CSI) driving” method. It should be noted, however, that during this charge sharing period, pixels do not have to have a perfectly black display state (i.e., at the 0th grayscale) but could have a luminance (or grayscale) that is about 40% as high as in the white display state (e.g., at the 255th grayscale if the display operation is performed in 256 grayscales). Furthermore, during one vertical scanning period, the number of times the charge sharing period is provided for each pixel does not have to be only once but may also be twice or more. In general, a data signal voltage is written (which is also called “video writing”) once a vertical scanning period. For that reason, to leave time for writing the data signal voltage sufficiently (i.e., to charge the pixel capacitor fully), the charge sharing period is preferably defined to be shorter than the data signal voltage write period. Furthermore, to achieve the effect of the pseudo-impulse drive, the black display period preferably accounts for 20% to 50% of one vertical scanning period.
According to the CSI driving method, not just can the power dissipation be cut down but also can the load on the source driver 70 be lightened compared to a driving method in which the black voltage, as well as the data signal voltage, should be supplied from the source driver 70.
Hereinafter, a configuration for the output section that is included in the source driver 70 to perform the CSI drive operation will be described with reference to
As shown in
Hereinafter, it will be described with reference to portions (a) through (d) of
As shown in portion (a) of
The display controller 60 generates the short-circuit control signal Csh shown in portion (b) of
Strictly speaking, the voltage waveform identified by S(i) in portion (c) of
To write the respective data signal voltages S(1), S(2), . . . and S(m) onto the respective pixels at predetermined timings (i.e., to charge the pixel capacitors), the gate driver 80 sequentially selects one of the gate bus lines GL1, GL2, . . . and GLn after another for substantially one horizontal scanning period (1H) each in every frame period (i.e., every vertical scanning period V shown in
TFTs that are connected to the gate bus line, to which the image data write pulse Pw and the black voltage application pulse Pb are applied, are turned ON. Such a state will be sometimes referred to herein as a state in which “the gate bus line is selected”. Naturally, a gate bus line, connected to TFTs in OFF state, is in a non-selected state. In this case, the image data write pulse Pw remains high for an effective scanning period corresponding to the effective display period within one horizontal scanning period (1H), but the black voltage application pulse Pb goes high for just the short-circuit period Tsh corresponding to the horizontal retrace interval (or horizontal blanking interval) within one horizontal scanning period (1H). In this example, in each scan signal voltage G(j), the interval between the image data write pulse Pw and the first black voltage application pulse Pb that appears earlier than any other black voltage application pulse after the image data write pulse Pw has been applied is two-thirds of one frame period ((⅔)×V) and three black voltage application pulses Pb appear at a regular interval of one horizontal scanning period (1H) in one frame period.
Next, it will be described with reference to portion (f) of
When the image data write pulse Pw is applied to the gate bus line GLj as shown in portion (d) of
Next, when the black voltage application pulse Pb is applied during a period Tsh in which the short-circuit control signal Csh is high (which will be referred to herein as a “short-circuit period”), the pixel capacitor gets connected to the source bus line SLi that has had a potential VSdc by that time as shown in portion (b) of
Thereafter, through a period Tbk (black display period) until the next image data write pulse Pw is applied to the gate bus line GLj, the black display state is maintained. By inserting the black display period Tbk into each frame in this manner, a display operation of a hold-type liquid crystal display device can be a pseudo-impulse type.
As can be seen from portions (d) and (e) of
It should be noted that the black insert drive does not have to be performed by the method just described but may be carried out by any other known technique (such as the methods disclosed in Japanese Patent Applications Laid-Open Publications Nos. 2000-105575 and 2001-265287). Also, in the example described above, a black insert driving method is supposed to be adopted as a driving method for writing data in a vertical blanking interval. However, the present invention is in no way limited to that specific preferred embodiment. The entire disclosure of the two publications cited above is hereby incorporated by reference.
In the foregoing description, a normal a situation where one horizontal scanning period of an input video signal is as long as one horizontal scanning period for writing image data on a display panel has been described as an example. According to a special driving method for changing the timings to drive using a frame memory, for example, not one horizontal scanning period of the input video signal but a standard horizontal scanning period for writing image data on the display panel may be defined as 1H. The standard horizontal scanning period is either defined in advance according to the use of the display device or determined based on one horizontal scanning period of the input video signal. Thus, one horizontal scanning period of the input video signal in the foregoing description may be replaced with the standard horizontal scanning period as it is.
In the foregoing description of preferred embodiments, the present invention has been described as being applied to a liquid crystal display device. However, this technique for adjusting the number of horizontal scanning periods included in one vertical scanning period by partially using 1Hn, which is different from one horizontal scanning period (1H) of an input video signal, as one horizontal scanning period for a display panel does not have to be used in a liquid crystal display device but is broadly applicable to any other type of display device to be driven line-sequentially.
Industrial Applicability
The present invention can be used effectively in a liquid crystal display device for a TV receiver with a big screen size of 30 inches or more, for example.
| Number | Date | Country | Kind |
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