Patent Grant
12159584
Exemplary embodiments of the present disclosure relate to a display device.
A display device may include a plurality of pixel regions spaced apart from one another, or may have a display region in which one portion is partially concavely recessed, in addition to typical shapes such as a single quadrangular shape.
Exemplary embodiments of the present disclosure provide a display device that includes first and second pixel regions spaced apart from each other with at least one non-pixel region interposed therebetween. Such a display device reduces the area of a non-pixel region included in the display device.
According to an exemplary embodiment of the present disclosure, a display device includes a first pixel region including a plurality of first pixels and a plurality of first gate control lines coupled to the first pixels, and a second pixel region spaced apart from the first pixel region. The second pixel region includes a plurality of second pixels and a plurality of second gate control lines coupled to the second pixels. The display device further includes a first non-pixel region disposed between the first pixel region and the second pixel region, and a first coupling line disposed in the first non-pixel region. The first coupling line commonly couples at least two first gate control lines and at least two second gate control lines.
In an exemplary embodiment, the first gate control lines include at least some of a plurality of first scan lines, a plurality of first initialization control lines, and a plurality of first emission control lines, which control driving of the first pixels. Further, the second gate control lines include at least some of a plurality of second scan lines, a plurality of second initialization control lines, and a plurality of second emission control lines, which control driving of the second pixels.
In an exemplary embodiment, the first coupling line commonly couples ith and (i+1)th first emission control lines disposed on ith and (i+1)th horizontal lines of the first pixel region, and ith and (i+1)th second emission control lines disposed on ith and (i+1)th horizontal lines of the second pixel region, in which i is a natural number.
In an exemplary embodiment, the display device further includes a second coupling line disposed at one side of the first pixel region or the second pixel region. The second coupling line couples the ith and (i+1)th first emission control lines or the ith and (i+1)th second emission control lines.
In an exemplary embodiment, the display device further includes an emission control driver including a kth emission control stage that supplies an emission control signal to the ith and (i+1)th first emission control lines and the ith and (i+1)th second emission control lines, in which k is a natural number.
In an exemplary embodiment, the emission control driver includes a plurality of emission control stages sequentially disposed at one side of the first pixel region or the second pixel region. The plurality of emission control stages includes the kth emission control stage.
In an exemplary embodiment, the emission control driver includes a plurality of emission control stages alternately disposed at one side of the first pixel region and one side of the second pixel region. The plurality of emission control stages includes the kth emission control stage.
In an exemplary embodiment, the first coupling line commonly couples an ith first scan line and an ith second scan line, which are respectively disposed on ith horizontal lines of the first and second pixel regions, and an (i+1)th first initialization control line and an (i+1)th second initialization control line, which are respectively disposed on an (i+1)th horizontal line of the first and second pixel regions, in which i is a natural number.
In an exemplary embodiment, the display device further includes a second coupling line disposed at one side of the first pixel region or the second pixel region. The second coupling line couples the ith first scan line and the (i+1)th first initialization control line, or the ith second scan line and the (i+1)th second initialization control line.
In an exemplary embodiment, the display device further includes a scan driver including an ith scan stage that supplies a scan signal to the ith first scan line, the ith second scan line, the (i+1)th first initialization control line, and the (i+1)th second initialization control line.
In an exemplary embodiment, the scan driver includes a plurality of scan stages sequentially disposed at one side of the first pixel region or the second pixel region, in which the plurality of scan stages includes the ith scan stage.
In an exemplary embodiment, the scan driver includes a plurality of scan stages alternately disposed at one side of the first pixel region and one side of the second pixel region. The plurality of scan stages includes the ith scan stage.
In an exemplary embodiment, the display device further includes a third pixel region disposed at one side of the first and second pixel regions and contacting the first and second pixel regions. The third pixel region includes a plurality of third pixels.
In an exemplary embodiment, the display device further includes a fourth pixel region disposed opposite to the third pixel region. The first pixel region, the second pixel region, and the first non-pixel region are interposed between the third pixel region and the fourth pixel region.
In an exemplary embodiment, the display device further includes an opening disposed in the first non-pixel region.
In an exemplary embodiment, the display device further includes a plurality of first coupling lines including the first coupling line. The plurality of first coupling lines is disposed in the first non-pixel region, and the first coupling lines are disposed in the first non-pixel region at an upper end of the opening and at a lower end of the opening.
In an exemplary embodiment, the display device further includes a substrate. The first and second pixels are arranged on one surface of the substrate. The substrate includes a plurality of protrusion parts corresponding to the first and second pixel regions, and a concave part corresponding to the first non-pixel region.
According to an exemplary embodiment of the present disclosure, a display device includes a first pixel region including a plurality of first pixels and a plurality of first gate control lines coupled to the first pixels, and a second pixel region spaced apart from the first pixel region. The second pixel region includes a plurality of second pixels and a plurality of second gate control lines coupled to the second pixels. The display device further includes a first non-pixel region disposed between the first pixel region and the second pixel region. The first non-pixel region includes a recess. The display device further includes a first coupling line disposed in the first non-pixel region. The first coupling line commonly couples at least two of the first gate control lines and at least two of the second gate control lines.
In an exemplary embodiment, the first gate control lines include at least some of a plurality of first scan lines, a plurality of first initialization control lines, and a plurality of first emission control lines, which control driving of the first pixels. Further, the second gate control lines include at least some of a plurality of second scan lines, a plurality of second initialization control lines, and a plurality of second emission control lines, which control driving of the second pixels.
In an exemplary embodiment, the first coupling line commonly couples ith and (i+1)th first emission control lines disposed on ith and (i+1)th horizontal lines of the first pixel region, and ith and (i+1)th second emission control lines disposed on ith and (i+1)th horizontal lines of the second pixel region, in which i is a natural number.
In an exemplary embodiment, the display device further includes a second coupling line disposed in a second non-pixel region at one side of the first pixel region or the second pixel region. The second coupling line couples the ith and (i+1)th first emission control lines or the ith and (i+1)th second emission control lines.
In an exemplary embodiment, the first coupling line commonly couples an ith first scan line and an ith second scan line, which are respectively disposed on ith horizontal lines of the first and second pixel regions, and an (i+1)th first initialization control line and an (i+1)th second initialization control line, which are respectively disposed on an (i+1)th horizontal line of the first and second pixel regions, in which i is a natural number.
In an exemplary embodiment, the display device further includes a second coupling line disposed in a second non-pixel region at one side of the first pixel region or the second pixel region. The second coupling line couples the ith first scan line and the (i+1)th first initialization control line, or the ith second scan line and the (i+1)th second initialization control line.
According to an exemplary embodiment of the present disclosure, a display device includes a substrate including a first protrusion part, a second protrusion part, and a notch region disposed between the first and second protrusion parts. The display device further includes a first pixel region disposed on the first protrusion part, in which the first pixel region includes a first row of first pixels and a first gate control line coupled to the first row of first pixels, and a second row of first pixels and a second gate control line coupled to the second row of first pixels. The display device further includes a second pixel region disposed on the second protrusion part, in which the second pixel region includes a first row of second pixels and a third gate control line coupled to the first row of second pixels, and a second row of second pixels and a fourth gate control line coupled to the second row of second pixels. The display device further includes a first non-pixel region disposed in the notch region, and a first coupling line disposed in the first non-pixel region, in which the first coupling line is coupled to the first gate control line, the second gate control line, the third gate control line, and the fourth gate control line.
The above and other features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:
Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings.
It will be understood that when a component is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another component, it can be directly on, connected, coupled, or adjacent to the other component, or intervening components may be present. It will also be understood that when a component is referred to as being “between” two components, it can be the only component between the two components, or one or more intervening components may also be present.
It will be understood that the terms “first,” “second,” “third,” etc. are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a “first” element in an exemplary embodiment may be described as a “second” element in another exemplary embodiment.
Referring to
The substrate 101 may be made of a glass or plastic material. However, exemplary embodiments of the present disclosure are not limited thereto. For example, the substrate 101 may be a flexible substrate including at least one of polyethersulfone (PES), polyacrylate (PA), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), triacetate cellulose (TAC), and cellulose acetate propionate (CAP). Further, the substrate 101 may be a rigid substrate including one of glass or tempered glass. Further, the substrate 101 may be made of a transparent material such as, for example, a light transmitting substrate. However, exemplary embodiments of the present disclosure are not limited thereto. Further, the substrate 101 may be configured to have different materials and/or different structures according to regions, so that different characteristics are exhibited for the respective regions. Further, the substrate 101 may have a single- or multi-layered structure. However, the structure of the substrate 101 is not limited thereto.
The display region DA includes the first pixel region AA1 and the second pixel region AA2, which are spaced apart from each other with the first non-pixel region NA1 interposed therebetween. In exemplary embodiments, the display region DA may further include a third pixel region AA3 disposed at one side of the first and second pixel regions AA1 and AA2. For example, the third pixel region AA3 may be disposed at one side of the first and second pixel regions AA1 and AA2 to be in contact with the first and second pixel regions AA1 and AA2. As an example, the first pixel region AA1 may be disposed at a left upper end of the third pixel region AA3, and the second pixel region AA2 may be disposed at a right upper end of the third pixel region AA3 to be spaced apart from the first pixel region AA1. In this case, the first non-pixel region NA1 may be disposed at an upper center of the third pixel region AA3.
At least two pixel regions among the first, second, and third pixel regions AA1, AA2, and AA3 may have different widths and/or different areas. For example, the third pixel region AA3 may occupy the widest area in the display region DA while having the widest width, and each of the first pixel region AA1 and the second pixel region AA2 may have an area smaller than that of the third pixel region AA3 while having a width narrower than that of the third pixel region AA3. In addition, the first pixel region AA1 and the second pixel region AA2 may have the same width and/or the same area, or may have different widths and/or different areas.
A plurality of first pixels PXL1, a plurality of second pixels PXL2, and a plurality of third pixels PXL3 may be disposed in the first pixel region AA1, the second pixel region AA2, and the third pixel region AA3, respectively. The first pixel region AA1, the second pixel region AA2, and the third pixel region AA3 may have the same structure, or at least some of the first pixel region AA1, the second pixel region AA2, and the third pixel region AA3 may have different structures. That is, in exemplary embodiments of the present disclosure, the structure of the first, second, and third pixels PXL1, PXL2, and PXL3 is not particularly limited. Each of the first, second, and third pixels PXL1, PXL2, and PXL3 may be a self-luminescent pixel including an organic light emitting diode. However, exemplary embodiments of the present disclosure are not limited thereto.
The first, second, and third pixels PXL1, PXL2, and PXL3 are disposed on the substrate 101 on which the first, second, and third pixel regions AA1, AA2, and AA3 are defined. For example, the first, second, and third pixels PXL1, PXL2, and PXL3 may be formed on the same one surface of the substrate 101.
Pixels are not disposed in the first non-pixel region NA1 and the second non-pixel region NA2. For example, the first non-pixel region NA1 and the second non-pixel region NA2 constitute a non-display region in which no pixels are included. Lines for driving the pixels PXL1, PXL2, and PXL3 of the display region DA may be disposed in the first non-pixel region NA1 and/or the second non-pixel region NA2. For example, lines for supplying various driving signals and/or various driving power sources to the pixels PXL1, PXL2, and PXL3 may be disposed in the first non-pixel region NA1 and/or the second non-pixel region NA2. Further, in exemplary embodiments, at least one driving circuit unit for driving the pixels PXL1, PXL2, and PXL3 may be disposed in the first non-pixel region NA1 and/or the second non-pixel region NA2. As an example, at least one of a scan driver, an emission controller, and a data driver may be disposed in the second non-pixel region NA2. Herein, the scan driver may also be referred to as a scan driver circuit, the emission controller may also be referred to as an emission controller circuit, and the data driver may also be referred to as a data driver circuit.
The shapes of the display region DA and the first non-pixel region NA1 may be variously modified. For example, the display region DA and/or the first non-pixel region NA1 may have a polygonal shape, a circular shape, an elliptical shape, or a combined shaped thereof.
In exemplary embodiments, the substrate 101 may include a recess (also referred to as a partial opening or an indentation) disposed between the first and second pixel regions AA1 and AA2. As an example, the substrate 101 may include a protrusion part 101a corresponding to each of the first and second pixel regions AA1 and AA2, and a concave part 101b (also referred to as a notch region) corresponding to the first non-pixel region NA1. For example, in exemplary embodiments, one region in the first non-pixel region NA1 may be recessed. When the substrate 101 includes the concave part 101b, the internal space of the display device can be more efficiently used. For example, a component such as a camera, a speaker, etc., may be disposed at the concave part 101b.
It is to be understood that the shape of the substrate 101 is not limited to the shape described above. For example, in an exemplary embodiment, the substrate 101 does not include a recess between the first and second pixel regions AA1 and AA2 as shown in
The shape of each of the first pixel region AA1, the second pixel region AA2, the third pixel region AA3, and/or the first non-pixel region NA1 may also be variously modified. For example, as shown in
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In addition, in exemplary embodiments, the substrate 101 may have a shape corresponding to that of the display region DA. As an example, at least one region (e.g., at least one corner part) of the substrate 101 may have a diagonal shape, a step shape, a curved shape, etc., corresponding to the shape of the display region DA. However, exemplary embodiments of the present disclosure are not limited thereto. For example, the substrate 101 may have a corner part (e.g., a right-angled corner part indicated by a dotted line in the figures) that has a right angle regardless of the shape of the display region DA.
Although exemplary embodiments in which the display region DA includes three pixel regions (e.g., the first, second, and third pixel regions AA1, AA2, and AA3) is disclosed with reference to
Alternatively, in exemplary embodiments, the display region DA may further include at least one pixel region in addition to the first, second, and third pixel regions AA1, AA2, and AA3. For example, as shown in
In addition, in an exemplary embodiment, at least one opening OPN may be disposed in the first non-pixel region NA1. Alternatively, in an exemplary embodiment, the first non-pixel region NA1 does not include the at least one opening OPN. For example, the substrate 101 may or may not include the opening OPN disposed in the first non-pixel region NA1.
Referring to
The organic light emitting diode OLED is coupled between a first power source ELVDD and a second power source ELVSS. As an example, an anode electrode of the organic light emitting diode OLED may be coupled to the first power source ELVDD via the pixel circuit PXC, and a cathode electrode of the organic light emitting diode OLED may be coupled to the second power source ELVSS. The organic light emitting diode OLED emits light with a luminance corresponding to a driving current supplied from the pixel circuit PXC.
The pixel circuit PXC controls the driving current flowing through the organic light emitting diode OLED corresponding to a data signal supplied through a corresponding data line (e.g., a jth data line) for every frame period. To this end, the pixel circuit PXC includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.
A first electrode of the first transistor T1 (also referred to herein as a driving transistor T1) is coupled to the first power source ELVDD via the fifth transistor T5, and a second electrode of the first transistor T1 is coupled to the anode electrode of the organic light emitting diode OLED via the sixth transistor T6. In addition, a gate electrode of the first transistor T1 is coupled to a first node N1. The first transistor T1 controls a driving current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode OLED corresponding to a voltage of the first node N1.
The second transistor T2 is coupled between the corresponding data line Dj and the first electrode of the first transistor T1. In addition, a gate electrode of the second transistor T2 is coupled to a corresponding scan line (e.g., an ith scan line) Si. The second transistor T2 is turned on when a scan signal is supplied to the ith scan line Si, thereby allowing the data line Dj and the first electrode of the first transistor T1 to be electrically coupled to each other. Here, the scan signal may be set as a signal having a gate-on voltage.
The third transistor T3 is coupled between the second electrode of the first transistor T1 and the first node N1. In addition, a gate electrode of the third transistor T3 is coupled to the ith scan line Si. The third transistor T3 is turned on when a scan signal is supplied to the ith scan line Si, thereby allowing the second electrode of the first transistor T1 and the first node N1 to be electrically coupled to each other. Therefore, if the third transistor is turned on, the first transistor T1 is diode-coupled.
The fourth transistor T4 is coupled between the first node N1 and an initialization power source Vint. In addition, a gate electrode of the fourth transistor T4 is coupled to an ith initialization control line CLi. The fourth transistor T4 is turned on when an initialization control signal is supplied to the ith initialization control line CLi, thereby supplying the voltage of the initialization power source Vint to the first node N1. Here, the initialization control signal may be set as a signal having the gate-on voltage, and the voltage of the initialization power source may be set as the lowest voltage or less of the data signal.
The ith initialization control line CLi is a control line that initializes pixels PXL disposed on the ith horizontal line, and the initialization control signal having the gate-on voltage is supplied to the ith initialization control line CLi before the scan signal is supplied to the ith scan line Si. As an example, the ith initialization control line CLi may be coupled to a scan line of a directly adjacent previous horizontal line (e.g., an (i−1)th scan line Si−1). In this case, a scan signal supplied to the (i−1)th scan line (e.g., a current scan signal of the directly adjacent previous horizontal line) may be used as the initialization control signal of the ith horizontal line. As described above, when the pixel PXL is initialized using a scan signal of another horizontal line, the pixels PXL can be initialized without providing a control line driver for generating a separate initialization control signal.
The fifth transistor T5 is coupled between the first power source ELVDD and the first transistor T1. In addition, a gate electrode of the fifth transistor T5 is coupled to a corresponding emission control line (e.g., an ith emission control line) Ei. The fifth transistor T5 is turned off when an emission control signal is supplied to the ith emission control line Ei, and is otherwise turned on. Here, the emission control signal may be set as a signal having a gate-off voltage.
The sixth transistor T6 is coupled between the first transistor T1 and the organic light emitting diode OLED. In addition, a gate electrode of the sixth transistor T6 is coupled to the ith emission control line Ei. The sixth transistor T6 is turned off when the emission control signal is supplied to the ith emission control line Ei, and is otherwise turned on.
The seventh transistor T7 is coupled between the initialization power source Vint and the anode electrode of the organic light emitting diode OLED. In addition, a gate electrode of the seventh transistor T7 is turned on when the scan signal is supplied to the ith scan signal Si, thereby supplying the voltage of the initialization power source Vint to the anode electrode of the organic light emitting diode OLED.
The storage capacitor Cst is coupled between the first power source ELVDD and the first node N1. The storage capacitor Cst stores a voltage corresponding to the data signal and the threshold voltage of the first transistor T1.
First, referring to
Subsequently, when a scan signal is supplied to the ith initialization control line CLi (e.g., the (i−1)th scan line Si−1), the fourth transistor T4 of the pixel PXL disposed on the ith horizontal line is turned on. When the fourth transistor T4 is turned on, the voltage of the initialization power source Vint is supplied to the first node N1. Then, the first node N1 is initialized to the voltage of the initialization power source Vint.
After the first node N1 is initialized to the voltage of the initialization power source Vint, a scan signal is supplied to the ith scan line Si. When the scan signal is supplied to the ith scan line Si, the second transistor T2, the third transistor T3, and the seventh transistor T7 of the pixel PXL disposed on the ith horizontal line are turned on.
When the seventh transistor T7 is turned on, the voltage of the initialization power source Vint is supplied to the anode electrode of the organic light emitting diode OLED. Then, a parasitic capacitor structurally formed in the organic light emitting diode OLED is discharged, and accordingly, the ability to accurately display a black gray scale is enhanced.
For example, the parasitic capacitor of the organic light emitting diode OLED is charged with a predetermined voltage corresponding to a current supplied in a previous frame period. When a black gray scale is to be displayed in a current frame, the organic light emitting diode OLED is to maintain the non-emission state during the corresponding frame period. However, when the parasitic capacitor of the organic light emitting diode OLED maintains a charged state, light may be easily emitted from the organic light emitting diode OLED by a small leakage current.
Alternatively, when the parasitic capacitor of the organic light emitting diode OLED is charged before each pixel PXL emits light, the leakage current of the first transistor T1 first charges the parasitic capacitor of the organic light emitting diode OLED. Accordingly, the organic light emitting diode OLED can stably maintain the non-emission state during a frame period in which the corresponding pixel PXL displays the black gray scale.
When the third transistor T3 is turned on, the first transistor T1 is diode-coupled.
When the second transistor T2 is turned on, a data signal supplied through the data line Dj of the corresponding pixel PXL is transferred to the first electrode of the first transistor T1. At this time, since the first node N1 is initialized to the voltage of the initialization power source Vint, which is lower than the lowest voltage of the data signal, the first transistor T1 is turned on. When the first transistor T1 is turned on, a voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data signal is applied to the first node N1. Accordingly, the storage capacitor Cst stores a voltage corresponding to the data signal applied to the first node N1 and the threshold voltage of the first transistor T1.
After the voltage corresponding to the data signal and the threshold voltage of the first transistor T1 is stored in the storage capacitor Cst, the supply of the emission control signal to the ith emission control line Ei is stopped. Therefore, the voltage of the ith emission control line may be changed to a gate-on voltage.
When the voltage of the ith emission control line Ei is changed to the gate-on voltage, the fifth transistor T5 and the sixth transistor T6 are turned on. Then, a current path of a driving current flowing from the first power source ELVDD to the second power source ELVSS via the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the organic light emitting diode OLED is formed. At this time, the first transistor T1 controls an amount of driving current flowing through the organic light emitting diode OLED corresponding to the voltage of the first node N1. Then, the organic light emitting diode OLED emits light with a luminance corresponding to the amount of driving current.
The pixel PXL generates light with a luminance corresponding to the data signal while repeating the above-described process. It is to be understood that the pixel structure of the pixel PXL (e.g., the structure of the pixel circuit PXC) and the driving method thereof are not limited to the exemplary embodiment described with reference to
An ith emission control signal supplied to the ith emission control line Ei is supplied to overlap with an ith scan signal. As a result, pixels PXL disposed on the ith horizontal line can maintain the non-emission state during a period in which the data signal is transferred to and stored in the pixels PXL. In addition, the ith emission control signal may be supplied to overlap with an ith initialization control signal (or an (i−1)th scan signal). As a result, pixels PXL disposed on the ith horizontal line can maintain the non-emission state during a period in which the pixels PXL are initialized. The supply timing of the emission control signal may be set using various methods.
Further, in exemplary embodiments, the emission of pixels PXL disposed on a plurality of horizontal lines may be simultaneously controlled. For example, an emission control signal may be simultaneously supplied to pixels PXL disposed on two consecutive horizontal lines for every two consecutive horizontal lines. As an example, the ith emission control line Ei and an (i+1)th emission control line Ei+1 may be coupled to each other to be implemented as one substantially integrated emission control line.
When the ith and (i+1)th emission control lines Ei and Ei+1 are coupled to each other, an emission control signal supplied to the ith and (i+1)th emission control lines Ei and Ei+1, as shown in
Referring to
In exemplary embodiments, the display region DA includes first, second, and third pixel regions AA1, AA2, and AA3. In addition, the first and second pixel regions AA1 and AA2 may be spaced apart from each other with a first non-pixel region NA1 interposed therebetween.
The first pixel region AA1 includes first pixels PXL1, and first gate control lines and data lines D1 to Dp (p is a natural number), which are coupled to the first pixels PXL1. Here, the first gate control lines refer to control lines for controlling driving of the first pixels PXL1. For example, the first gate control lines may include at least some of first scan lines S10, S11, S12, . . . , first initialization control lines (e.g., first scan lines on a directly adjacent previous horizontal line), and first emission control lines E11, E12, . . . , which control driving timings of the first pixels PXL1.
As an example, a first group of the first horizontal pixels PXL1, and a tenth scan line S10, an eleventh scan line S11, and an eleventh emission control line E11, which supply an initialization control signal (or previous scan signal), a scan signal (or current scan signal), and an emission control signal to each of the pixels in the first group of the first horizontal pixels PXL1, may be disposed on a first horizontal line of the first pixel region AA1. In addition, a second group of the first horizontal pixels PXL1, and the eleventh scan line S11, a twelfth scan line S12, and a twelfth emission control line E12, which supply an initialization control signal (or previous scan signal), a scan signal (or current scan signal), and an emission control signal to each of the pixels in the second group of the first horizontal pixels PXL1, may be disposed on a second horizontal line of the first pixel region AA1.
In exemplary embodiments, each initialization control line for initialization of the first pixels PXL1 may be coupled to and/or integrated with a current scan line of a previous horizontal line. However, exemplary embodiments of the present disclosure are not limited thereto. Further, in exemplary embodiments, the first emission control lines E11, E12, . . . may form a pair for every at least two first emission control lines to be coupled to and/or integrated with each other. However, exemplary embodiments of the present disclosure are not limited thereto. The type and/or number of control lines included in the first gate control lines may be variously changed depending on the structure of the first pixels PXL1.
The first non-pixel region NA1 is disposed at one side of the first pixel region AA1. No pixels are disposed in the first non-pixel region NA1, and therefore, the first non-pixel region NA1 may be set as a non-display region.
The second pixel region AA2 is disposed at one side of the first non-pixel region NA1. For example, the second pixel region AA2 and the pixel region AA1 may be disposed adjacent to each other with the first non-pixel region NA1 interposed therebetween.
The second pixel region AA2 includes second pixels PXL2, and second gate control lines and data lines Dp+q+1 to Dp+q+r (p, q, and r are natural numbers), which are coupled to the second pixels PXL2. Here, the second gate control lines refer to control lines that control driving the second pixels PXL2. For example, the second gate control lines may include at least some of second scan lines S20, S21, S22, . . . , second initialization control lines (e.g., second scan lines on a directly adjacent previous horizontal line), and second emission control lines E21, E22, . . . , which control driving timings of the second pixels PXL2. As an example, a first group of second horizontal pixels PXL2, and a twentieth scan line S20, a twenty-first scan line S21, and a twenty-first emission control line E21, which supply an initialization control signal (or previous scan signal), a scan signal (or current scan signal), and an emission control signal to each of the pixels in the first group of the second horizontal pixels PXL2, may be disposed on a first horizontal line of the second pixel region AA2. In addition, a second group of the second horizontal pixels PXL2, and the twenty-first scan line S21, a twenty-second scan line S22, and a twenty-second emission control line E22, which supply an initialization control signal (or previous scan signal), a scan signal (or current scan signal), and an emission control signal to each of the pixels in the second group of the second horizontal pixels PXL2, may be disposed on a second horizontal line of the second pixel region AA2.
In exemplary embodiments, each initialization control line that initializes the second pixels PXL2 may be coupled to and/or integrated with a current scan line of a previous horizontal line. However, exemplary embodiments of the present disclosure are not limited thereto. Further, in exemplary embodiments, the second emission control lines E21, E22, . . . may form a pair for every at least two first emission control lines to be coupled to and/or integrated with each other. However, exemplary embodiments of the present disclosure are not limited thereto. The type and/or number of control lines included in the second gate control lines may be variously changed depending on the structure of the second pixels PXL2.
The third pixel region AA3 is disposed at one side of the first and second pixel regions AA1 and AA2 and the first non-pixel region NA1. For example, the third pixel region AA3 may be disposed at a lower end of the first and second pixel regions AA1 and AA2 and the first non-pixel region NA1.
The third pixel region AA3 includes third pixels PXL3, and third gate control lines and the data lines D1 to Dp+q+r. Here, the third gate control lines refer to control lines that control driving of the third pixels PXL3. For example, the third gate control lines may include at least some of the third scan lines S31, S32, . . . , third initialization control lines (e.g., the last first and second scan lines of the first and second pixel regions AA1 and AA2, or third scan lines of a directly adjacent previous horizontal line), and third emission control lines E31, E32, . . . , which control driving timings of the third pixels PXL3.
In exemplary embodiments, each initialization control line that initializes the third pixels PXL3 may be coupled to and/or integrated with a current scan line of a previous horizontal line. However, exemplary embodiments of the present disclosure are not limited thereto. Further, in exemplary embodiments, the third emission control lines E31, E32, . . . may form a pair for every at least two first emission control lines to be coupled to and/or integrated with each other. However, exemplary embodiments of the present disclosure are not limited thereto. The type and/or number of control lines included in the third gate control lines may be variously changed depending on the structure of the third pixels PXL3.
The first scan driver 110a may be disposed at one side of the first pixel region AA1 and the third pixel region AA3. As an example, the first scan driver 110a may be disposed at a left side of the first pixel region AA1 and the third pixel region AA3. The first scan driver 110a sequentially supplies a scan signal to the first scan lines S10, S11, S12, . . . and the third scan lines S31, S32, . . . .
The second scan driver 110b may be disposed at one side of the second pixel region AA2 and the third pixel region AA3. As an example, the second scan driver 110b may be disposed at a right side of the second pixel region AA2 and the third pixel region AA3. The second scan driver 110b sequentially supplies a scan signal to the second scan lines S20, S21, S22, . . . and the third scan lines S31, S32, . . . .
In exemplary embodiments, the second scan driver 110b may supply a scan signal to the second scan lines S20, S21, S22, . . . to be synchronized with the time when a scan signal is supplied to the first scan lines S10, S11, S12, . . . . That is, the first and second pixel regions AA1 and AA2 may be simultaneously scanned.
The first emission control driver 120a may be disposed at one side of the first pixel region AA1 and the third pixel region AA3. As an example, the first emission control driver 120a may be disposed at a left side of the first pixel region AA1 and the third pixel region AA3. The first emission control driver 120a sequentially supplies an emission control signal to the first emission control lines E11, E12, . . . and the third emission control lines E31, E32, . . . .
The second emission control driver 120b may be disposed at one side of the second pixel region AA2 and the third pixel region AA3. As an example, the second emission control driver 120b may be disposed at a right side of the second pixel region AA2 and the third pixel region AA3. The second emission control driver 120b sequentially supplies an emission control signal to the second emission control lines E21, E22, . . . and the third emission control lines E31, E32, . . . .
In exemplary embodiments, the second emission control driver 120b may supply an emission control signal to the second emission control lines E21, E22, . . . to be synchronized with the time when an emission control signal is supplied to the first emission control lines E11, E12, . . . . That is, the first and second pixel regions AA1 and AA2 may be simultaneously driven. In exemplary embodiments, the first and second emission control drivers 120a and 120b may be omitted according to the structure of the pixels PXL1, PXL2, and PXL3 arranged in the display region DA and/or the driving method thereof.
The data driver 130 is supplied with image data from the outside (e.g., a timing controller, etc.), and generates a data signal corresponding to the image data. The data driver 130 supplies a data signal to the data lines D1 to Dp+q+r for every horizontal period to be synchronized with the scan signal supplied to the first and second scan lines S10, S11, S12, . . . and S20, S21, S22, . . . and the third scan lines S31, S32, . . . .
First, referring to
The first sub-scan driver 111 includes a plurality of first scan stages SST11, SST12, . . . . The first sub-scan driver 111 sequentially supplies a scan signal to the first scan lines S11, S12, . . . using a first start signal FLM1 and first and second clock signals CLK1 and CLK2. In exemplary embodiments, when at least one initialization control line (e.g., the tenth scan line S10) for initialization of the first pixels PXL1 disposed on the first horizontal line of the first pixel region AA1 is further provided, the first sub-scan driver 111 may further include at least one first scan stage for supplying a scan signal (or initialization control signal) to the tenth scan line S10 before a scan signal is supplied to the eleventh scan line S11.
The second sub-scan driver 112 includes a plurality of third scan stages SST31, SST32, . . . . The second sub-scan driver 112 subsequently supplies a scan signal to the third scan lines S31, S32, . . . , using the output signal of the first sub-scan driver 111 (e.g., the current scan signal supplied to the last horizontal line of the first pixel region AA1) (or the separate start signal) and the first and second clock signals CLK1 and CLK2.
Referring to
The third sub-scan driver 113 includes a plurality of second scan stages SST21, SST22, . . . . The third sub-scan driver 113 sequentially supplies a scan signal to the second scan lines S21, S22, . . . using a second start signal FLM2 and the first and second clock signals CLK1 and CLK2. In exemplary embodiments, the second start signal FLM2 may be supplied to be synchronized with the first start signal FLM1. In exemplary embodiments, when at least one initialization control line (e.g., the twentieth scan line S20) for initialization of the second pixel PXL2 disposed on the first horizontal line of the second pixel region AA2 is further provided, the third sub-scan driver 113 may further include at least one second scan stage for supplying a scan signal (or initialization control signal) to the twentieth scan line S20 before a scan signal is supplied to the twenty-first scan line S21.
The fourth sub-scan driver 114 includes a plurality of third scan stages SST31, SST32, . . . . The fourth sub-scan driver 114 sequentially supplies a scan signal to the third scan lines S31, S32, . . . using the output signal of the third sub-scan driver 113 (e.g., the current scan signal supplied to the last horizontal line of the second pixel region AA2) (or the separate start signal) and the first and second clock signals CLK1 and CLK2. In exemplary embodiments, the third scan stages SST31, and SST32, . . . provided in the second and fourth sub-scan drivers 112 and 114 may have substantially the same configuration, and thus, may be driven in synchronization with each other.
In an exemplary embodiment of the present disclosure, the configuration of the first to third scan stages SST11, SST12, SST21, SST22, . . . , and SST31, SST32, . . . is not particularly limited. That is, the first to third scan stages SST11, SST12, SST21, SST22, and SST31, SST32, . . . may be implemented with various types of scan stage circuits.
First, referring to
The third sub-emission control driver 123 includes a plurality of second emission control stages EST21, EST22, . . . . The third sub-emission control driver 123 sequentially supplies an emission control signal to the second emission control lines E21, E22, E23, E24, using a fourth start signal EFLM2 and the third and fourth clock signals CLK3 and CLK4. In exemplary embodiments, the fourth start signal EFLM2 may be supplied to be synchronized with the third start signal EFLM1. When the second emission control lines E21, E22, E23, E24, form a pair for every plurality of, for example, two second emission control lines to be coupled to each other, the third sub-emission control driver 123 may sequentially supply an emission control signal to the pairs of second emission control lines E21 and E22, E23 and E24, . . . .
The fourth sub-emission driver 124 includes a plurality of third emission control stages EST31, EST32, . . . . The fourth sub-emission control driver 124 sequentially supplies an emission control signal to the third emission control lines E31, E32, E33, E34, . . . using the output signal of the third sub-emission control driver 123 (e.g., the emission control signal supplied to the last horizontal line of the second pixel region AA2) (or the separate start signal). In exemplary embodiments, when the third emission control lines E31, E32, E33, E34, . . . form a pair for every plurality of, for example, two third emission control lines to be coupled to each other, the fourth sub-emission control driver 124 may sequentially supply an emission control signal to the pairs of third emission control lines E31 and E32, E33 and E34, In exemplary embodiments, the third emission control stages SST31, SST32, . . . provided in the second and fourth sub-emission control drivers 122 and 124 may have substantially the same configuration, and thus, may be driven in synchronization with each other.
In an exemplary embodiment of the present disclosure, the configuration of the first to third emission control stages EST11, EST12, EST21, EST22, . . . , and EST31, EST32, . . . is not particularly limited. For example, the first to third emission control stages EST11, EST12, EST21, EST22, . . . , and EST31, EST32, . . . may be implemented with various types of emission control stages.
According to the exemplary embodiments shown in
First, referring to
In addition, the first and second emission control drivers 120a and 120b described in the above-described exemplary embodiments may also be integrated as one emission control driver 120. For example, the integrated emission control driver 120 may be disposed at any one side (e.g., a right side) of the display region DA, and sequentially drives the first, second, and third emission control lines E11/E21, E12/E22, E31, E32, . . . in units of horizontal lines of the display region DA. The emission control driver 120 may be disposed at the same one side as the scan driver 110, or may be disposed at one side different from that of the scan driver 110. As an example, the scan driver 110 may be disposed at a left side of the display region DA, and the emission control driver 120 may be disposed at a right side of the display region DA, as illustrated in
First coupling lines CNL1 may be disposed in the first non-pixel region NA1 so as to drive the first, second, and third pixel regions AA1, AA2, and AA3, using one scan driver 110 and one emission control driver 120. Here, the first coupling lines CNL1 may connect lines corresponding to each other among the first and second gate lines disposed in the first and second pixel regions AA1 and AA2.
As an example, first initialization control lines (e.g., the tenth scan line S10 and the twentieth scan line S20) disposed on a first horizontal line of the first and second pixel regions AA1 and AA2 may be coupled to each other by any one of the first coupling lines CNL1 (e.g., a first coupling line), and first current scan lines (e.g., the eleventh scan line S11 and the twenty-first scan line S21) disposed on the first horizontal line may be coupled to each other by another one of the first coupling lines CNL1 (e.g., a second first coupling line). In addition, first emission control lines (e.g., the eleventh emission control line E11 and the twenty-first emission control line E21) disposed on the first horizontal line may be coupled to each other by another one of the first coupling lines CNL1 (e.g., a third first coupling line). In this manner, first and second gate control lines disposed on each horizontal line of the first and second pixel regions AA1 and AA2 may be coupled to each other by each of the first coupling lines CNL1.
In exemplary embodiments, each of the scan driver 110 and the emission driver 120 may be disposed to be divided into two blocks. For example, as shown in
In this case, although each of the scan driver 110 and the emission control driver 120 is divided into two blocks 110c and 110d or 120c and 120d to be provided at different sides of the display region DA, the area of a stage circuit provided in the display panel 100 may be substantially similar to that in the exemplary embodiment of
According to the exemplary embodiments of
First, referring to
For example, ith and (i+1)th first emission control lines E1i and E1i+1 respectively disposed on ith and (i+1)th horizontal lines of the first pixel region AA1 may be coupled to each other to be supplied with the same first emission control signal. As an example, the ith and (i+1)th first emission control lines E1i and E1i+1 may be commonly coupled to a kth (k is a natural number) emission control stage ESTk, and thus, are simultaneously supplied with a first emission control signal from the kth emission control stage ESTk.
In addition, (i+2)th and (i+3)th first emission control lines E1i+2 and E1i+3 respectively disposed on (i+2)th and (i+3)th horizontal lines of the first pixel region AA1 may be coupled to each other, and thus, are supplied with the same first emission control signal. As an example, the (i+2)th and (i+3)th first emission control lines E1i+2 and E1i+3 may be commonly coupled to a (k+1)th emission control stage ESTk+1, and thus, are simultaneously supplied with a first emission control signal from the (k+1)th emission control stage ESTk+1.
Similarly, second emission control lines E2i, E2i+1, E2i+2, and E2i+3 are disposed on the respective horizontal lines in the second pixel region AA2. Each of the second emission control lines E2i, E2i+1, E2i+2, and E2i+3 may be coupled to at least one second emission control line adjacent thereto. For example, ith and (i+1)th second emission control lines E2i and E2i+1 respectively disposed on ith and (i+1)th horizontal lines of the second pixel region AA2 may be coupled to each other, and thus, are supplied with the same first emission control signal. In addition, (i+2)th and (i+3)th second emission control lines E2i+2 and E2i+3 respectively disposed on (i+2)th and (i+3)th horizontal lines of the second pixel region AA2 may be coupled to each other, and thus, are supplied with the same first emission control signal.
In this exemplary embodiment, emission control lines simultaneously driven among the first and second emission control lines E1i, E1i+1, E1i+2, E1i+3, E2i, E2i+1, E2i+2, and E2i+3 disposed on the respective horizontal lines of the first and second pixel regions AA1 and AA2 are electrically coupled to each other by any one of the first coupling lines CNL1 disposed in the first non-pixel region NA1. For example, the ith and (i+1)th first emission control lines E1i and E1i+1 respectively disposed on the ith and (i+1)th horizontal lines of the first pixel region AA1, and the ith and (i+1)th second emission control lines E2i and E2i+1 respectively disposed on the ith and (i+1)th horizontal lines of the second pixel region AA2, may be commonly coupled by a kth first coupling line CNL1k. In this case, the ith and (i+1)th first emission control lines E1i and E1i+1 and the ith and (i+1)th second emission control lines E2i and E2i+1 may be simultaneously supplied with first and second emission control signals from any one emission control stage such as, for example, the kth emission control stage ESTk provided in the emission control driver 120.
Similarly, the (i+2)th and (i+3)th first emission control lines E1i+2 and E1i+3 respectively disposed on the (i+2)th and (i+3)th horizontal lines of the first pixel region AA1, and the (i+2)th and (i+3)th second emission control lines E2i+2 and E2i+3 respectively disposed on the (i+2)th and (i+3)th horizontal lines of the second pixel region AA2, may be coupled by any one of the first coupling lines CNL1. As an example, the (i+2)th and (i+3)th first emission control lines E1i+2 and E1i+3 and the (i+2)th and (i+3)th second emission control lines E2i+2 and E2i+3 may be commonly coupled by a (k+1)th first coupling line CNL1k+1. In this case, the (i+2)th and (i+3)th first emission control lines E1i+2 and E1i+3, and the (i+2)th and (i+3)th second emission control lines E2i+2 and E2i+3, may be simultaneously supplied with first and second emission control signals from any one emission control stage such as, for example, the (k+1)th emission control stage ESTk+1 provided in the emission control driver 120.
Herein, when one coupling line is referred to as commonly coupling at least two gate control lines, it is to be understood that the one coupling line connects the at least two gate control lines to each other. For example, as shown in
Referring to
In the above-described manner, the emission control lines simultaneously driven among the first and second emission control lines E1i, E1i+1, E1i+2, E1i+3, E2i, E2i+1, E2i+2, and E2i+3 disposed on the respective horizontal lines of the first and second pixel regions AA1 and AA2 are commonly coupled by one first coupling line (e.g., any one of CNL1k and CNL1k+1) in the non-pixel region NA1. Accordingly, the number of first coupling lines CNL1k and CNL1k+1 disposed in the first non-pixel region NA1 can be decreased as compared with the exemplary embodiments shown in
An exemplary embodiment in which the emission control stages ESTk and ESTk+1 provided in the emission control driver 120 are sequentially disposed at the same one side of the display region DA (e.g., one side of the first pixel region AA1 or the second pixel region AA2) is disclosed in
In addition, although only an exemplary embodiment in which the emission control lines simultaneously driven among the first and second emission control lines E1i, E1i+1, E1i+2, E1i+3, E2i, E2i+1, E2i+2, and E2i+3 are commonly coupled to one first coupling line (e.g., any one of CNL1k and CNL1k+1) is disclosed in
As an example, ith first and second scan lines S1i and S2i respectively disposed on ith horizontal lines of the first and second pixel regions AA1 and AA2, and (i+1)th first and second initialization control lines CL1i+1 and CL2i+1 respectively disposed on (i+1)th horizontal lines of the first and second pixel regions AA1 and AA2, may be commonly coupled to an ith coupling line CNL1i disposed in the first non-pixel region NA1. In addition, the ith first and second scan lines S1i and S2i and the (i+1)th first and second initialization control lines CL1i+1 and CL2i+1 may be commonly coupled to an ith scan stage SSTi provided in the scan driver 110, and thus, are simultaneously supplied with an ith scan signal (or an (i+1)th initialization control signal) from the ith scan stage SSTi.
In addition, (i+1)th first and second scan lines S1i+1 and S2i+1 respectively disposed on (i+1)th horizontal lines of the first and second pixel regions AA1 and AA2, and (i+2)th first and second initialization control lines CL1i+2 and CL2i+2 respectively disposed on (i+2)th horizontal lines of the first and second pixel regions AA1 and AA2, may be commonly coupled to an (i+1)th first coupling line CNL1i+1 disposed in the first non-pixel region NA1. The (i+1)th first and second scan lines S1i+1 and S2i+1 and the (i+2)th first and second initialization control lines CL1i+2 and CL2i+2 may be commonly coupled to an (i+1)th scan stage SSTi+1 provided in the scan driver 110, and thus, are simultaneously supplied with an (i+1)th scan signal (or an (i+2)th initialization control signal) from the (i+1)th scan stage SSTi+1.
In the above-described manner, the initialization control lines and the scan lines, which are simultaneously driven among the first and second initialization control lines CL1i, CL1i+1, CL1i+2, CL1i+3, CL2i, CL2i+1, CL2i+2, and CL2i+3 and the first and second scan lines S1i, S1i+1, S1i+2, S1i+3, S2i, S2i+1, S2i+2, and S2i+3, may be commonly coupled to one first coupling line (e.g., any one of CNLi, CNLi+1, CNLi+2, and CNLi+3) to be driven by the same scan stage (e.g., any one of SSTi, SSTi+1, SSTi+2, and SSTi+3). Accordingly, the number of first coupling lines CNL1 disposed in the first non-pixel region NA1 can be decreased as compared with the exemplary embodiments shown in
Additionally, the scan stages SSTi, SSTi+1, SSTi+2, and SSTi+3 provided in the scan driver 110 may be sequentially disposed at the same one side of the display region DA (e.g., one side of the first pixel region AA1 or the second pixel region AA2), as shown in
According to the exemplary embodiments shown in
Further, according to the above-described exemplary embodiments, the first and second control lines applied with the same control signal are integrally coupled by one first coupling line in the first non-pixel region NA1. As a result, the number of first coupling lines CNL1k, CNL1k+1, CNL1i, CNLli+1, CNLli+2, and CNLli+3 disposed in the first non-pixel region NA1 can be decreased. As an example, when the exemplary embodiments of
Thus, according to the above-described exemplary embodiments, the line structure of the first non-pixel region NA1 can be simplified, and accordingly, the area of the first non-pixel region NA1 can be effectively decreased.
First, referring to
In addition, a pair of second emission control lines E2i and E2i+1, or E2i+2 and E2i+3, may be coupled to each other at both sides of the second pixel region AA2. As an example, the pair of second emission control lines E2i and E2i+1, or E2i+2 and E2i+3, may be coupled to each other in the first non-pixel region NA1 at the left side of the second pixel region AA2 and the second non-pixel region NA2 at the right side of the second pixel region AA2.
To this end, the display panel 100 according to this exemplary embodiment further includes second coupling lines CNL2k and CNL2k+1, each disposed at one side of the first or second pixel region AA1 or AA2. For example, the display panel 100 may include a kth second coupling line CNL2k that couples the ith and (i+1)th first emission control lines E1i and E1i+1, or the ith and (i+1)th second emission control lines E2i and E2i+1, at one side of the first or second pixel region AA1 or AA2. As an example, the kth second coupling line CNL2k may be disposed at the opposite side of the kth emission control stage ESTk that supplies an emission control signal to emission control lines (e.g., the ith and (i+1)th first emission control lines E1i and E1i+1 and the ith and (i+1)th second emission control lines E2i and E2i+1) coupled thereto.
Next, referring to
In addition, a second scan line and a second initialization control line, which are simultaneously driven by substantially the same signal from among the second scan lines S2i, S2i+1, S2i+2, and S2i+3 and the second initialization control lines CL2i, CL2i+1, CL2i+2, and CL2i+3, may be coupled to each other at both sides of the second pixel region AA2. As an example, an ith second scan line S2i and an (i+1)th second initialization control line CL2i+1 may be coupled to each other in the first non-pixel region NA1 at the left side of the second pixel region AA2 and the second non-pixel region NA2 at the right side of the second pixel region AA2.
To this end, the display panel 100 according to this exemplary embodiment further includes third coupling lines CNL3i, CNL3i+1, CNL3i+2, and CNL3i+3 each disposed at one side of the first or second pixel region AA1 and AA2. For example, the display panel 100 may include an ith third coupling line CNL3i that couples the ith first scan line S1i and the (i+1)th first initialization control line CL1i+1, or the ith second scan line S2i and the (i+1)th second initialization control line CL2i+1, at one side of the first or second pixel region AA1 or AA2. As an example, the ith third coupling line CNL3i may be disposed at the opposite side of the ith scan stage SSTi that supplies a scan signal (or initialization control signal) to scan lines and initialization control lines (e.g., the ith first and second scan lines S1i and S2i and the (i+1)th first and second initialization control lines CL1i+1 and CL2i+1) coupled thereto.
According to the exemplary embodiments shown in
Referring to
According to the above-described exemplary embodiments, the area occupied by a driving circuit in the display panel 100 is decreased, and accordingly, the area of the second non-pixel region NA2 can be reduced. Further, although at least one of the first coupling lines CNL1 in the first non-pixel region NA1 may be broken, the first and second gate control lines can be normally driven.
Referring to
As described above, in the display according to exemplary embodiments of the present disclosure, the structure and/or shape of the display panel 100 can be variously modified and implemented.
According to exemplary embodiments of the present disclosure, a display device includes first and second pixel regions spaced apart from each other with a first non-pixel region interposed therebetween. As a result, the number of coupling lines disposed in the first non-pixel region is decreased in exemplary embodiments of the present disclosure. Accordingly, the line structure of the first non-pixel region can be simplified, and thus, the area of the first non-pixel region can be reduced.
While the present disclosure has been particularly shown and described with reference to the exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2017-0178356 | Dec 2017 | KR | national |
This application is a continuation application of U.S. patent application Ser. No. 17/590,490 filed Feb. 1, 2022, which is a continuation application of U.S. patent application Ser. No. 17/020,046 filed Sep. 14, 2020, issued as U.S. Pat. No. 11,250,776 on Feb. 15, 2022, which is a continuation application of U.S. patent application Ser. No. 16/152,597 filed Oct. 5, 2018, issued as U.S. Pat. No. 10,796,636 on Oct. 6, 2020, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0178356 filed on Dec. 22, 2017, the disclosures of which are incorporated by reference herein in their entirety.
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| Number | Date | Country | |
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| Number | Date | Country | |
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| Parent | 17590490 | Feb 2022 | US |
| Child | 18447691 | US | |
| Parent | 17020046 | Sep 2020 | US |
| Child | 17590490 | US | |
| Parent | 16152597 | Oct 2018 | US |
| Child | 17020046 | US |
